JPH11119188A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate black line generation when power is OFF and to improve display quality by supplying reset signals to the low driver of an integrated circuit for driving when power supply is disconnected. SOLUTION: A timing generation circuit 104 is constituted of the timing generation circuit constituted of a delay circuit and an AND circuit for generating pulses from the output of an OR circuit and a level shifter for performing the conversion of a signal voltage level to power supply VDD generated by boosting. Display OFF signals 101 are controlled so as to be 0 V at the same timing as the power supply 106 or the timing before the power supply is turned OFF (0 V). The timing of the edge of the changeover of the signals and the timing of the changeover of frame signals 102 are processed in the OR circuit 103, turned to pulse signals in the timing generation circuit 104a, converted to a voltage suppliable to a common driver by the level shifter 104b, turned to the reset signals TPR of the low driver and transmitted from an output terminal 105 to the low driver.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device having a driving integrated circuit, and more particularly to a reflection type liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device stores transmitted dot-sequential display data in a column driver for every one or two rows, and in a line-sequential manner by a selection signal generated by a row driver for each corresponding row. indicate. This display method is called a voltage averaging method, and the total number of the scanning electrodes is called a division number of the liquid crystal display device. For example, in the case of a liquid crystal display device having 240 divisions, the selection signal voltage is about ± 18 V. The power supply of the liquid crystal driving integrated circuit is, for example, a liquid crystal television,
It is created by boosting the voltage from a power supply such as a liquid crystal monitor and supplied to the integrated circuit.

FIG. 4 shows a block diagram of a conventional liquid crystal display device. A power supply voltage supplied from a main body (hereinafter referred to as a system) is boosted by a 107 booster circuit and supplied to a level shifter and a row driver. The row driver control signal generated by the system is supplied to the row driver after voltage conversion by the level shifter 104b. 401 is n
Represents the scanning electrodes in the row.

When the power supply is cut off (hereinafter referred to as power off), the supply of the boosted power supply is cut off with a delay corresponding to the charge accumulated in the smoothing capacitor. Therefore, the control clock signal generated by the system is cut off earlier than the boost power supply. In the case of a normal liquid crystal display device, since light is supplied from the back by a backlight such as an EL or a fluorescent lamp, the backlight is also turned off when the power is turned off.

[0005]

However, in the case of a reflection type liquid crystal display device which has an optical reflector on one surface of the liquid crystal display device, the display screen can be recognized by utilizing light incident from the outside, Since the supply of the driver's clock is cut off and the boosted power supply, which is the power supply of the row driver, is cut off with a delay, there is an inconvenience that only a specific electrode is supplied with a long selection signal.

For example, if the system is powered off while the scan electrodes in the n-th row are being selected, no clock is generated for selecting the scan electrodes in the n-th and subsequent rows. Therefore, the electrode 40
1, the selection signal is applied until the output of the booster circuit 107 decreases. Therefore, the electrode 40
In the case of a liquid crystal display device in which the effective voltage of No. 1 is increased and becomes black when a voltage is applied, there is a problem that a black line remains on the liquid crystal display surface.

FIG. 5 shows a timing chart of the operation. In the figure, 301 indicates the timing of turning off the power supply, 303 indicates the FRAME signal, 501 indicates the TPR signal, and 30 indicates the TPR signal.
3 is input once per frame, and a row driver reset signal 501 is created from this signal.
Reference numeral 305 denotes a LOAD signal, which is a clock signal that advances the output signal of the row driver by one, and 306 denotes a booster circuit 10.
The output voltage of 7 corresponds to VDD of 108. Reference numeral 307 denotes an output signal of the (n-1) th row of the liquid crystal display device, and 502
Shows the output waveform of the row driver applied to the electrode 401 in the n-th row. The clock signals 303 and 305 are not input at the timing 309 when the power supply is turned off, but the boosted output 306, which is the power supply voltage of the row driver, is turned off with a delay from the timing 309 due to the operation of the smoothing capacitor 109. Therefore, a large portion corresponding to the waveform 503 is applied to the electrode 401. This effective voltage causes the electrode 401 to become black.

An object of the present invention is to solve the above-mentioned problem, to eliminate black lines generated at the time of power-off, and to improve display quality.

[0009]

In order to achieve the above object, the present invention provides a power supply voltage or display-off signal (DispOFF), a means for adding the signal and a frame signal (FRAME), Means for generating a reset signal (TPR) for a row driver, and a row driver for resetting an internal counter by the reset signal, and for supplying a reset signal to the row driver of the driving integrated circuit when the power supply is cut off. 3. A control method for a liquid crystal display device according to claim 1.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a block diagram of the present invention. In the figure, reference numeral 101 denotes a display-off signal (described as DispOFF in the figure), 102 denotes a FRAME signal, 103
Is an OR circuit for adding the signals inputted from 101 and 102, 104 is a timing generating circuit composed of a delay circuit and an AND circuit for generating a pulse from the output of the OR circuit, and a signal to a power supply VDD generated by boosting. A reset signal generation circuit composed of a level shifter for converting a voltage level, a reset signal TPR of a row driver generated from the reset signal generation circuit 105, a power supply input terminal 106 from the system, and a voltage 107 from the power supply
A booster circuit for generating DD, VDD is a power supply for a row driver generated by the booster circuit, and 109 is a power supply for the row driver.
A capacitor for smoothing D, and 110 indicates a scan electrode in the n-th row.

FIG. 2 shows a part of a circuit diagram of the present invention. In the figure, reference numeral 104 denotes a timing generation circuit 104a composed of a delay circuit and an AND circuit for generating a pulse from the output of the OR circuit, and a power supply V generated by boosting.
Level shifter 104 for converting signal voltage level to DD
b. DispOFF signal 101 is the power supply 10
6 is controlled so as to become 0 V at the same timing as that of 6 or at a timing before the supply power is turned off (0 V).
The switching edge of this signal and the switching timing of the FRAME signal 102 are processed by the OR circuit 103, become a pulse signal by the timing generation circuit 104a, are converted into a voltage that can be supplied to the common driver by the level shifter 104b, and become the reset signal TPR of the row driver. The signal is transmitted from the output terminal 105 to the row driver.

FIG. 3 shows a timing chart of each signal. In the figure, reference numeral 301 denotes the timing at which the power supply applied to the power supply 106 is turned off, 302 denotes the timing of the display-off signal (DispOFF) 101, 30
3 is the timing of the FRAME signal 102, 304 is the timing of the TPR signal 105, 305 is a LOAD signal which serves to advance the output signal of the row driver by one, 306 is the output voltage of the booster circuit 107, and is smoothed by the smoothing capacitor 109. Reference numeral 108 denotes the VDD, 307 denotes an output signal of the (n-1) th row of the liquid crystal display device, and 308 denotes an output waveform of the row driver applied to the electrode 110 of the nth row. As in the conventional method, the clock signals 303 and 305 are not input at the timing 309 when the power supply is turned off, but the display-off signal 302 (DispOFF) is displayed.
The row driver is reset by the TPR signal synthesized and created by the step (3), and the boosted output 3 which is the power supply voltage of the row driver is output.
06 is the timing 3 due to the operation of the smoothing capacitor 109.
Even if the electrode 110 is turned off with a delay from 09, the waveform 3
As shown at 08, many selection signals are not applied. Therefore, good display quality can be obtained without displaying a black line.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiment, for the sake of simplicity of description, the case where a power supply voltage applied to a row driver is supplied as a fixed VDD is described. Obviously, it can be easily applied even when it fluctuates. In addition, in the case of an oscillating power supply, since the potential itself of the row driver fluctuates with respect to the system, it becomes difficult to input a signal to a terminal provided for the purpose of turning off the display on the row driver itself. The scheme is more effective.

[0014]

As is apparent from the above description, according to the present invention, the display screen can be recognized by utilizing the light incident from the outside by providing the optical reflector on one surface of the liquid crystal display device. In the control method of the driving integrated circuit of the reflection type liquid crystal display device, by supplying a reset signal to the row driver of the driving integrated circuit when the power supply is cut off, it is possible to eliminate a black line which has conventionally been generated. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a diagram showing a part of a circuit diagram of one embodiment of the present invention.

FIG. 3 is a diagram showing a timing chart of an embodiment of the present invention.

FIG. 4 is a diagram showing a block diagram of a conventional example.

FIG. 5 is a diagram showing a timing chart of a conventional example.

[Explanation of symbols]

 101 Display Off Signal Input Terminal 102 FRAME Signal Input Terminal 103 OR Circuit 104 Timing Generation Circuit 104a Delay Circuit 104b Level Shifter 105 Reset Signal TPR Output Terminal 106 Supply Power Input Terminal 107 Boost Circuit 108 VDD 109 Smoothing Capacitor

Claims (1)

[Claims] 1. A liquid crystal display device having a driving integrated circuit for driving a liquid crystal display element, wherein a reset signal is supplied to a row driver of the driving integrated circuit when a power supply of the driving integrated circuit of the reflection type liquid crystal display device is cut off. A liquid crystal display device characterized by supplying: