JPH11112976A - Error correction circuit for image signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make deterioration in visually conspicuous in a decoded image signal which is deteriorated by data errors. SOLUTION: Input data 111 are decoded via an error detection means 7 and a decoding means 8, and the result is given to a 1st selection means 9. Output data 116 of the selection means 9 are feed directly to a 2nd selection means 11 and feed to both selection means 9, 11 via a field delay means 10. Output data 120 of the selection means 11 are feed directly to a 3rd selection means 13 and via a different field data generating (linear interpolation) means 12. A selection control section 14 controls each selection means according to discrimination result information 113 of an error detection means, and the data of an erroneous frame immediately prior to being replaced with even field data of a frame immediately prior to without an error and odd frame data immediately after. When the data after the replacement are not the data for a prescribed field, the data are replaced with the data of a field which have been passed through the different field data generating means for the correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal error correction circuit, and more particularly to a first field and a second field for performing interlaced scanning of each frame corresponding to a time series.
The present invention relates to an error correction circuit for making a frame portion in which a bit error has occurred in transmission or recording / reproduction visually inconspicuous when decoding compression-coded data of an image signal divided into fields.

[0002]

2. Description of the Related Art When transmitting and recording / reproducing an image signal by compressing and encoding the image signal, bit errors may occur due to noise on a transmission line, scratches and dust on a recording medium, and the like. If the data with a bit error is decoded as it is, decoding becomes impossible, or even if it can be decoded, the reproduced image is greatly deteriorated. For this reason, an error correction code is generally added when transmission or recording / reproduction is performed, so that even if a bit error occurs on the way, it can be corrected before decoding.

However, when a bit error exceeding the capability of the error correction code occurs, the uncorrectable data is input to the decoding circuit, and it is necessary to make the effect of the error data visually inconspicuous. There is. Especially in systems using compression coding, the effect of errors propagates in the direction of spatial and temporal correlation used during compression,
An error correction circuit corresponding to the compression method is required.

In a system using a spatial correlation in a frame as a compression method, the effect of a bit error propagates in a spatial direction, and therefore, error correction is generally performed using a correlation in a time direction. Here, an example of a conventional error correction circuit will be described with reference to the drawings.

In FIG. 11, input data 151
In the error detecting means 31, it is determined whether or not the data contains an error. The determination result information 153 is input to the selection control means 35. The data 152 for which the error determination has been performed is input to the decoding means 32, where the decoding processing of the compressed coded data is performed, and the image signal is reproduced.

[0006] The decrypted data 154 is input to the selection means 33. The output data 156 of the frame delay unit (frame memory) 34 is also input to the selection unit 33. The selection unit 33 selects one of the data 154 and the data 156 according to the selection control signal 157 output from the selection control unit 35. That is, if no error is included in the output data 154 of the decoding means 32, the output data 154 of the decoding means 32 is selected. If an error is included, the output data 156 of the frame delay means 34 is selected.
Is selected.

The output data 155 of the selection means 33 is output as error correction data and is also input to the frame delay means 34. The frame delay means 34 is generally composed of a frame memory and its control circuit.
The output is delayed by the frame period.

The error correction circuit having the configuration shown in FIG. 11 replaces an erroneous part with a pixel at the same position one frame before, and makes deterioration of the erroneous part inconspicuous. FIG. 12 shows the operation timing of an erroneous portion. In FIG.
The decoded data K indicates the field timing of the output data 154 of the decoding means 32 in FIG. 11, and the erroneous field is indicated by oblique lines.

In FIG. 12, the first (odd) of the first frame is shown.
The field timing is represented as 1o, and the second (even) field timing of the first frame is represented as 1e. However, in a system using an intra-frame compression method utilizing correlation between both odd field data and even field timing, In the example of K in FIG. 12, the odd field and the even field are mistaken at the same time due to the propagation of the error.
This indicates that both fields of the frame, the fifth frame, and the sixth frame are incorrect.

Further, the selection control signal of L in FIG.
, And is generated by the error detecting means 31 and the selecting control means 35. When the selection control signal L in FIG. 12 is at a low level, no error is included, so that the decoded data is selected. When the selection control signal L is at a high level, an error is included, so that frame-delayed data is selected. The selection output is as shown by M, where the error portion of the second frame contains the data at the same position of the first frame, and the error portions of the fifth and sixth frames have the same data at the same position of the fourth frame. Each data is replaced, and the error part becomes visually inconspicuous.

[0011]

In the conventional error correction circuit shown in FIG. 11, since the error portion is replaced by the data at the same position one frame before, there is no problem if the error portion is a static area. In the case of a motion area, there is a problem that the motion becomes unnatural.

For example, in FIG. 12, in the error portion of the fifth and sixth frames, data at the same position of the fourth frame is repeatedly reproduced. The odd field data 4o and the even field data 4e of the fourth frame are temporally shifted, and the data to be reproduced in the order of 4o → 4e
o → 4e → 4o, so 4e → 4
The order is reversed in the part to be reproduced with o. as a result,
The reproduced image becomes unnatural because the correct motion and the reversed motion are alternately reproduced.

As a method of solving the unnaturalness of the moving area in the error correction circuit, for example, Japanese Patent Laid-Open No. 7-312 discloses a method.
No. 755 discloses that an error part (block) is a still area or a moving area, the still area is replaced with the same position data of the immediately preceding frame, and the moving area is replaced with a peripheral macro block or a corresponding area of the immediately preceding frame. A method is described in which an interpolation image is created from the immediately preceding frame data using a motion vector, and the interpolation image is replaced with the interpolation image.

However, in the method of the above-mentioned document, it is necessary to determine whether an error portion is a static region or a moving region. However, it is difficult to determine whether or not there is motion with respect to erroneous data. Even if it is possible, if an erroneous determination is made, there are problems that the reproduced image quality is rather deteriorated and that a complicated circuit is required and the circuit scale becomes large.

An object of the present invention is to provide an image signal error correction circuit which does not need to judge the presence or absence of a motion, and does not cause unnatural motion not only in a static region but also in a moving region. I do.

[0016]

An image signal error correction circuit according to a first aspect of the present invention is configured by dividing each frame corresponding to a time series into a first field and a second field for performing an interlace scan. In a circuit for correcting an error of a frame unit of an image signal, data of each of the first and second fields of a frame in which an error has occurred is replaced with data of the second field of a frame immediately before containing no error and data of an error. Is modified by replacing with the data of the first frame of the frame immediately after the first frame.

Further, in the above configuration, error detection means for judging whether or not an error is included in the compressed and coded data of the image signal transmitted or recorded and reproduced, and Decoding means for performing decoding and decompression processing on the compressed and coded data to return to an image signal; and output from the decoding means in accordance with a first selection control signal based on error information detected by the error detection means. First selecting means for selecting one of the image data to be processed and the image data delayed by one field period, and setting the data output from the first selecting means to 1
A field delay unit for delaying by a field period, error information detected by the error detection unit, and a second selection control signal based on a synchronization signal of decoded image data obtained by the decoding unit. And the second selection means for selecting any of the output data of the selection means and the data output from the field delay selection means.

An error correction circuit for an image signal according to a second aspect of the present invention comprises:
The circuit for correcting an error in a frame unit of an image signal configured by dividing each frame corresponding to a time series into a first field and a second field for performing an interlace scan is performed by performing a line interpolation calculation process. The data of the first field is the data of the second field, and the data of the second field is the first field.
And a different field data generating means for converting and outputting the data of each of the first and second fields of the frame in which the error has occurred. And the first frame data of the frame immediately after the error-free frame, and if the data after the replacement is not data for a predetermined field, the data is passed through the different field data generating means. It is characterized in that it is modified by replacing it with field data.

Further, in the above configuration, error detecting means for determining whether or not an error is included in the compressed and encoded data of the image signal transmitted or recorded and reproduced, and Decoding means for performing decoding and decompression processing on the compressed and coded data to return to an image signal; and output from the decoding means in accordance with a first selection control signal based on error information detected by the error detection means. First selecting means for selecting one of the image data to be processed and the image data delayed by one field period, and setting the data output from the first selecting means to 1
A field delay unit for delaying by a field period, error information detected by the error detection unit, and a second selection control signal based on a synchronization signal of decoded image data obtained by the decoding unit. Second selecting means for selecting one of the output data of the selecting means and the data output from the field delay selecting means, and performing line interpolation on the data output from the second selecting means. Performing different field data generating means for generating data of different fields which are spatially shifted by performing, and a third selection control signal based on a synchronization signal of decoded image data obtained by the decoding means,
A configuration may be provided having third selection means for selecting one of the output data of the second selection means and the data output from the different field data generation means.

In the image signal error correction circuit according to a second aspect of the present invention, the different field data generating means includes at least one line delay means for delaying input image data by one line period; By performing a filter operation using the output data of each line delay unit, it is possible to have a configuration including an operation unit for generating data of a new line.

In the image signal error correction circuit according to the first and second aspects of the present invention, the decoding means converts the compressed and coded data into synchronous data representing the head of a frame or a block, and decodes and decompresses the data. Header extraction means for extracting header information containing necessary additional information, variable length decoding means for variable length decoding of data by the compression encoding, and variable length decoding by the variable length decoding means. An inverse quantizer for inversely quantizing the decoded data according to the additional information extracted by the header extractor, and an orthogonal inverse transform for the data extracted by the inverse quantizer. And a scan conversion unit for performing interlace scan conversion on data output from the orthogonal inverse conversion unit and converting the data into an image signal. Kill.

[0022]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of an image signal error correction circuit according to the first invention. In FIG. 1, compression-encoded data 101 of an image signal transmitted or recorded / reproduced is:
It is input to the error detection means 1. The error detecting means 1 determines whether an error is included in the input data.
As the determination method, for example, an error detection code such as a CRC code is added in advance to the compressed and coded data 101, and the error detection means 1 checks the error detection code. As a result of determining whether or not the input data contains an error by the error detection means 1,
The input data is directly input to the decoding means 2 as data 102, and the determination result information 103 is input to the selection control means 6.

The decoding means 2 detects a data synchronizing signal from the header information or the like of the input data, outputs a synchronizing signal 104 to the selection control means 6 and
2 are decoded and decompressed, and the image signal (data 1
05).

Here, a detailed configuration example of the decoding means 2 will be described with reference to FIG. In FIG. 8, first, the compression encoded data 134 is input to the header extracting means 23. The compression coded data usually includes a synchronization signal indicating the beginning of a frame, a synchronization signal indicating the beginning of a block when the screen is divided into a plurality of small area blocks, and a quantization parameter necessary for decoding. The additional information is encoded and included in the data. The header extracting means 23 performs a process of extracting the synchronous data and the additional information. The extracted synchronization data 136 is output as it is, and the quantization parameter 135 is input to the inverse quantization means 25.

The data 137 output from the header extracting means 23 is input to the variable length decoding means 24, where variable length decoding processing such as Huffman code decoding and run length code decoding is performed. The variable-length decoded data 138 is input to the inverse quantization means 25.

In the inverse quantization means 25, the data 138 is inversely quantized according to the quantization parameter 135. The inverse quantization process is the reverse of the quantization process, and converts the data into data before quantization. However, it does not completely return to the value before quantization depending on the roughness of quantization.

The inversely quantized data 139 is input to the inverse DCT means 26. The inverse DCT means performs an inverse transform of a discrete cosine transform (abbreviated as DCT), and performs a process of transforming into a value before DCT processing. Data 140 output from the inverse DCT unit 26 is input to the scan conversion unit 27.

The scan conversion means 27 performs a process of returning data that has been made block scan for DCT to interlace scan and raster scan.
The scan-converted data 141 is output as decoded data.

The data input to the decoding process shown in FIG. 8 needs to be decoded on the transmitting side or the recording side so that the data can be decoded by the configuration shown in FIG. An example of an encoding unit for performing the encoding process will be described with reference to FIG.

In FIG. 9, an image signal 142 of an interlaced scan and a raster scan is inputted, and is converted into a block scan by a scan converting means 41.
In general, a block size of 8 pixels × 8 lines is selected. When constructing a block, interlaced scan data is performed by non-interlaced scan (progressive scan).

Data 14 converted to block scan
3 is input to the DCT means 42 and subjected to DCT processing. The DCT-processed data 144 is input to the quantization means 43 and quantized. When performing quantization, a quantization parameter 146 is generated by the quantization control means 44, and the quantization is performed according to the quantization parameter 146.

The generation of the quantization parameter by the quantization control means 44 is performed, for example, by finely quantizing a block of a fine pattern, or by performing coarse quantization on a block of a flat pattern to minimize image quality as much as possible. Alternatively, control is performed according to the purpose of the system, such as performing coarse quantization on the whole of a screen having many fine parts in order to suppress the generated code amount of one screen to a certain value or less.

The quantization means 43 includes a quantization control means 44
In accordance with the quantization parameter 146 generated by, fine and coarse quantization is adaptively performed. The data 145 subjected to such quantization processing is input to the variable-length encoding unit 45.

The variable-length encoding means 45 performs variable-length encoding processing such as Huffman encoding, run-length encoding, or encoding combining these. The variable-length encoded data 147 is input to the header adding means 46.

The header adding means 46 includes, as headers, the quantization parameters 146 used for performing the quantization processing, a frame start position of data subjected to variable length coding, a synchronization signal 148 for indicating a block start position, and the like. To the data. Then, the data is output as compressed and encoded data 149.

Returning to FIG. 1, the data 105 decoded by the decoding means 2 is input to the selection means 3. The output data 107 of the field delay means (field memory) 4 is also input to the selection means 3 and the selection control signal 10
8, any one of the data 105 and the data 107 is selected. The selection control means 6 determines from the error determination information 103 whether or not the data 105 contains an error.
The selection control signal 108 is input to the selection means 3. That is, if the data 105 input to the selection means 3 does not include an error, the data 105 is selected. If the data 105 includes an error, the output data 107 of the field delay means 4 is selected.
Select

The output data 106 of the first selecting means 3 is
The data is input to the field delay means 4 and the second selection means 5. The field delay means 4 is generally composed of a field memory and its control circuit.
06 is output with a delay of one field period. Output data 107 of the field delay unit 4 is input to the selection unit 3 and the selection unit 5.

The selection means 5 selects one of the output 106 of the selection means 3 and the output 107 of the field delay means 4 in accordance with the selection control signal 109 output from the selection control means 6. In the selection control means 6, the error judgment information 1
03 and the synchronization signal 104, control is performed such that the output 106 of the selection means 3 is selected only for the last field of the error portion, and the output 107 of the field delay means 4 is selected otherwise, and the selection control signal 109 is output. . Selection means 5
Is output as error correction data.

Here, the first selecting means 3 shown in FIG.
The operation of the second selecting means 5 will be described with reference to FIG.

In FIG. 2, similarly to FIG. 12, the decoded data A indicates the field timing of the output data 105 of the decoding means 2 in FIG. 1, and the erroneous field is indicated by oblique lines. In the example of FIG. 2A, the first (odd) and second frames of each of the second frame, the fifth frame, and the sixth frame are shown.
This indicates that both (even) fields are incorrect. Further, the selection control signal 1 of B corresponds to the selection control signal 108 of the selection means 3 in FIG. The output of selection 1 of C indicates the output data 106 of the selection means 3 in FIG. 1, and the delay data of D indicates the output data 107 of the field delay means 4 in FIG.

In FIG. 2, when the selection control signal 1 of B is at a low level, no error is included, and the decoded data A is selected. When the selection control signal 1 is at a high level, an error is included. Field-delayed data D is selected. Therefore, as shown in the selection 1 output of C, the error portion of the second frame contains data at the same position of the even frame of the first frame, and the error portions of the fifth and sixth frames contain the data of the even field of the fourth frame. The data at the same position is replaced respectively.

Next, the selection control signal 2 of E corresponds to the selection control signal 109 of the selection means 5 in FIG. 1, and the output of selection 2 of F corresponds to the output data 110 of the selection means 5 in FIG. . The selection control signal 2 shown at E is set to a high level only in the last field of the fields containing errors, and to a low level in the other fields. It should be noted that the last field among the fields containing an error includes the field delay unit 4 before the selection unit 5 in FIG.
The phase becomes a field-delayed phase, and becomes a high level in the phase of the delay data of D. When the selection control signal 2 of E is at a high level, the selection 1 output of C is selected.
Is selected, the last field data of the delayed data of D is replaced by the subsequent field data as shown by F in the selection 2 output.

By using the error correction circuit described above, for example, as shown in FIG.
Since e → 1e → 3o → 3o → 3e is played back, there is no part that goes back in time, and the number of fields to be played back repeatedly can be reduced, so that errors in visually natural motion can be corrected. become.

In an image signal forming one frame from two fields, each field scans a different position by interlaced scanning. In FIG. 4, the (odd) field 201 and the (even) field 202 constitute one frame with two frames.
1 scans the middle of the line 201 between the line o1 and the line o2. Therefore, when odd field data is output at the timing of outputting even field data in a frame, o1, o2, and o2 in FIG.
.. are scanned at the positions e1, e2, e3,..., and the scanning position is shifted from the original position in the vertical direction. Conversely, in the frame,
The same applies to the case of outputting even field data at the timing of outputting odd field data.

The image signal error correction circuit according to the first aspect of the present invention is effective in that it does not reverse in time and does not cause unnatural motion. For example, the error correction result in FIG. 1o → 1e → 1e → 3o → 3o → 3e
And 1e at the timing when the odd field is output,
In other words, even field data of the first frame is output or even field is output and 3o, that is, odd field data of the third frame is output, so that the vertical spatial position of the error-corrected portion is slightly reduced. There is a problem that they are shifted.

Therefore, even when outputting the even field at the output timing of the odd field, or when outputting the odd field at the output timing of the even field,
The second invention will be described below in which the position in the vertical direction does not shift and becomes unnatural.

FIG. 3 shows an embodiment of an image signal error correction circuit according to the second invention. In FIG. 3, the operations of the error detecting means 7, the decoding means 8, the (first) selecting means 9, the field delaying means 10, and the (second) selecting means 11 are described with reference to the error detecting means 1, the decoding means in FIG. 2, (first
3), the field delay means 4 and the (second) selection means 5 are the same as those of FIG.

In FIG. 3, output data 120 of the second selection means 11 is input to a line interpolation means (different field data generation means) 12 and a third selection means 13.
In the case of outputting odd field data at the output timing of the even field, the line interpolation means 12 performs processing of generating data of a different field, such as generating data of a spatial position of an even field from data of an odd field. . Then, the different field data 121 output from the line interpolation means 12 is input to the selection means 13.

The selection means 13 selects one of the output data 121 of the line interpolation means 12 and the output data 120 of the selection means 11 in accordance with the selection control signal 122 generated by the selection control means 14. That is, the selection control means 14 uses the synchronizing signal 114 to determine whether the data output from the selection means 11 is odd or even field data and whether the output timing is odd or even within the frame. If the field timing does not match the actually output data, the output data 120 of the selection unit 11 is selected.

Here, the configuration and operation of the line interpolation means 12 will be described with reference to FIG. The data 124 input in FIG. 5 is input to the filter operation means 19 and the line delay means (line memory) 15. The line delay means 15 delays the input data by one line period and outputs data 125. The data 125 is input to the filter operation means 19 and the next-stage line delay means 16.
The line delay unit 16 performs the same operation as the line delay unit 15. The output data 126 of the line delay unit 16 is input to the filter operation unit 19 and the next-stage line delay unit 17. Hereinafter, a plurality of line delay means (17,..., 1)
8), data (127,..., 12)
8) is input to the filter operation means 19.

In the filter operation means 19, for example, FIR
Using a filter (linear phase filter), the data of multiple lines are multiplied by a predetermined constant to each value, and an operation of adding them is performed. Generated by The constant by which each line is multiplied is set in advance so that the line at the target spatial position is calculated.

In the configuration of FIG. 5, the arithmetic processing is performed using the data of a plurality of lines obtained by the plurality of line delay means. However, for simpler explanation, it is obtained by using one line delay means. FIG. 6 shows an example of performing an operation using data of two lines.

In FIG. 6, input data 130 is input to a line delay means (line memory) 20 and an adding means 21. In the line delay means 20, the input data 130
Is delayed for one line period, and data 131 is output. The data 131 is input to the adding means 21. The adding means 21 adds the input data 130 and the output data 131 of the line delay means 20 to obtain the addition result data 132
Is input to the dividing means 22. The division unit 22 divides the input data 132 by 2 and outputs operation result data 133.

FIG. 7 shows the operation performed in FIG.
This will be described with reference to FIG. In FIG. 6, since the data of the input line and the data of the previous line are added and divided by 2, the data value of the line located between the two lines is calculated. That is, in FIG. 7, when the data of the lines o1, o2, o3,... Of the odd field is input, the data of the oe1 located in the middle is generated by using the data of the o1 line and the data of the o2 line. Will be. Similarly, o2 line and o3
The oe2 data is generated from the line and the oe3 data is generated from the o3 line and the o4 line. Since the generated data of oe1, oe2, oe3,... Is data at the intermediate position of the odd field, it spatially matches the position of the even field data. Therefore, the data after the operation can be used as even field data.

In the operation of FIG. 6, two line data are added and then divided by two. However, as described in the operation description of FIG. 5, each of the two line data is halved.
, And adding them, the result is the same.

Here, the first selecting means 9 shown in FIG.
FIG. 10 shows the operation of the second selecting means 11 and the third selecting means 13. In FIG. 10, from the decrypted data of A to F
Are the same as those in FIG.

In FIG. 10, the G selection control signal 3 corresponds to the selection control signal 122 of the selection means 13 in FIG.
Output of the selection means 13 in FIG.
Equivalent to 3. When the selection control signal 3 of G is at a low level, the odd / even of the field is the same, so that the output of selection 2 of F (data 120 in FIG. 3) is selected. , F, line-interpolated data from two outputs (data 121 in FIG. 3)
Is selected. That is, the even field data 1e, 4
generate odd field data 1e-o and 4e-o from e,
Then, even field data 3o-e and 7o-e are generated and replaced from odd field data 3o and 7o.

By using the image signal error correction circuit described above, there is no part that returns backward in time, so that there is no visually unnatural movement, and the output timing of an odd field does not occur. Even when outputting even field data or outputting an odd field at the output timing of the even field, it is possible to perform error correction without displacing the vertical position and becoming unnatural.

In the present embodiment, the block size of the DCT has been described as 8 * 8, but other sizes may be used, and larger or smaller blocks may be used.

[0061]

As described above, according to the image signal error correction circuit of the present invention, even if a data error occurs in a system for transmitting or recording / reproducing data compressed in a frame, the frame having the error can be corrected. Since the field data is replaced with the field data immediately before and after the field data, the portion does not return backward in time and becomes unnatural.

Further, even when data of a field different from the original field is output in the frame, by providing means for generating and outputting the original field data, it is possible to prevent unnaturalness in the spatial direction. In particular, DC
When the compression coding using T is used, an error correction method of spatially interpolating an error part cannot be used because of a large deterioration in image quality. Thus, it is possible to provide a practically useful or image signal error correction circuit capable of accurate error correction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the first invention.

FIG. 2 is a diagram for explaining operation signals of respective parts of the image signal error correction circuit shown in FIG. 1;

FIG. 3 is a block diagram showing an embodiment of the second invention.

FIG. 4 is an explanatory diagram of a field configuration of an image signal.

FIG. 5 is a block diagram illustrating a configuration example of a unit that generates different field data by line interpolation.

FIG. 6 is a block diagram showing another configuration example of a means for generating different field data.

FIG. 7 is a diagram illustrating a process of generating different field data by line interpolation.

FIG. 8 is a block diagram illustrating a configuration example of a decoding unit for compressed data.

FIG. 9 is a block diagram illustrating a configuration example of an encoding unit that generates compressed data.

FIG. 10 is a diagram for explaining operation signals of respective parts of the image signal error correction circuit shown in FIG. 3;

FIG. 11 is a configuration diagram of a conventional image signal error correction circuit.

FIG. 12 is a diagram for explaining an operation signal of each section of the conventional image signal error correction circuit.

[Explanation of symbols]

1,7 Error detection means 2,8 Decoding means 3,5,9,11,13 Selection means 6,14 Selection control means 4,10 Field delay means (field memory) 12 Line interpolation means (different field data generation means) 15 , 16, 17, 18, 20 Line delay means (line memory) 19 Filter operation means 21 Addition means 22 Division means 23 Header extraction means 24 Variable length decoding means 25 Inverse quantization means 26 Inverse DCT means 27, 41 Scan conversion means 42 DCT means 43 Quantization means 44 Quantization control means 45 Variable length coding means 46 Header addition means 201, 202 Field

Claims (6)

[Claims] 1. A circuit for correcting an error of a frame unit of an image signal configured by dividing each frame corresponding to a time series into a first field and a second field for performing an interlace scan, wherein an error has occurred. Replacing the data of each of the first and second fields of the frame with the data of the second field of the immediately preceding frame without errors and the data of the first frame of the immediately following frame without errors; An error correction circuit for an image signal, wherein the error correction circuit corrects the error. 2. A circuit for correcting an error in a frame unit of an image signal formed by dividing each frame corresponding to a time series into a first field and a second field for performing an interlace scan. A different field data generating means for converting the data of the first field into the data of the second field and converting and outputting the data of the second field as the data of the first field. The data of each of the first and second fields of the erroneous frame is replaced by the data of the second field of the immediately preceding frame containing no error and the first frame data of the immediately following frame containing no error. And if the data after the replacement is not data for a predetermined field, Error correction circuit of the image signal, characterized in that to correct by replacing the data of the field through the Rudodeta generation means. 3. An error detecting means for judging whether or not an error is included in the compressed and coded data of the image signal transmitted or recorded and reproduced, and said compressed and coded data. Decoding means for performing decoding and decompression processing to return to an image signal; and image data output from the decoding means in accordance with a first selection control signal based on error information detected by the error detection means. First selecting means for selecting any one of image data delayed by one field period, and field delay means for delaying data output from the first selecting means by one field period. According to the error information detected by the error detection means, and a second selection control signal based on the synchronization signal of the decoded image data obtained by the decoding means, And a second selecting means for selecting one of the output data of the first selecting means and the data outputted from the field delay selecting means. 2. The image signal error correction circuit according to claim 1, wherein the correction is performed by substituting the image signal. 4. An error detecting means for judging whether or not an error is included in the compressed coded data of the image signal transmitted or recorded / reproduced, and the compressed coded data. Decoding means for performing decoding and decompression processing to return to an image signal; and image data output from the decoding means in accordance with a first selection control signal based on error information detected by the error detection means. First selecting means for selecting any one of image data delayed by one field period, and field delay means for delaying data output from the first selecting means by one field period. According to the error information detected by the error detection means, and a second selection control signal based on the synchronization signal of the decoded image data obtained by the decoding means, A second selecting means for selecting one of the output data of the first selecting means and the data output from the field delay selecting means, and for the data output from the second selecting means, According to a different field data generating means for generating data of different fields spatially deviated by performing line interpolation, and a third selection control signal based on a synchronization signal of decoded image data obtained by the decoding means, A third selector for selecting one of the output data of the second selector and the data output from the different field data generator.
3. An error correcting circuit for an image signal according to claim 2, wherein the error correcting section corrects the error portion by replacing the error portion with one of data of the preceding and succeeding fields and its line interpolation data. 5. The different field data generating means performs a filter operation using at least one line delay means for delaying input image data by one line period, and output data of each line delay means. 5. An error correcting circuit for an image signal according to claim 2, further comprising: an arithmetic unit for generating data of a new line. 6. A header extracting means for extracting, from the compressed and coded data, synchronous data representing a head of a frame or a block, and header information including additional information necessary for decoding and decompression. A variable-length decoding unit for performing variable-length decoding on the data in the compression encoding; and a variable-length decoding unit that outputs the data obtained by the variable-length decoding unit in accordance with the additional information extracted by the header extracting unit. Inverse quantization means for inverse quantization, orthogonal inverse transformation means for performing orthogonal inverse transformation on data extracted by the inverse quantization means, and data output from the orthogonal inverse transformation means 5. The image signal error correction circuit according to claim 3, further comprising scan conversion means for performing interlace scan conversion and converting the image signal into an image signal.