JPH11112835A - Timing control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate a large capacitance memory and to reduce a cost by synthesizing the outputs of first and second comparators and generating a first timing control signal. SOLUTION: A comparator 103 generates a signal to be a high level only during a prescribed first period within one vertical period. The prescribed first period is stipulated by a phase 104 and the phase 105. A comparator 106 generates the signal to be the high level only for the prescribed second period within one horizontal period. The prescribed second period is stipulated by the phases 107 and 108. Then, the signal outputted from the comparator 103 is synthesized with the one outputted from the comparator 106 by an optional method so as to obtain the timing control signal. Thus, the timing control signal is generated without using the large capacitance memory. In result, the cost in a timing control circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing control circuit, and more particularly to a timing control circuit suitable for a video signal processor and having reduced cost.

[0002]

2. Description of the Related Art In recent years, with the start of digital broadcasting or the enhancement of broadcast image quality, video signal processing circuits incorporated in television receivers and the like are required to have functions of processing video signals of various formats. It is becoming. In addition, the video signal processing circuit is required to have a function of simultaneously displaying more information, such as two-screen display and multi-screen display. Against this background, a programmable video signal processor has been used for the video signal processing circuit. While realizing the above-mentioned advanced functions, further reduction of the cost of the video signal processor is indispensable for further popularization of television receivers and the like. In a video signal processor, its timing control circuit is also programmable, and the circuit scale of this portion is large, which causes an increase in cost.

FIG. 19 shows a configuration of a conventional timing control circuit of a video signal processor. The timing control circuit generates a field identification signal and a memory control signal in synchronization with the vertical synchronization signal, the horizontal synchronization signal, and the video clock.

As shown in FIG. 19, a timing control circuit includes a counter 1501, a counter 1502, a memory 1503, a comparator 1504, a phase 1505,
And a 1-bit memory 1506.

A counter 1501 is initialized by a vertical synchronization signal and counts a horizontal synchronization signal. Counter 1
Reference numeral 502 counts the number of video clocks initialized by the horizontal synchronization signal.

[0006] The count value of the counter 1501 and the count value of the counter 1502 are input to the memory 1503 as addresses. Memory 1503 outputs data corresponding to the address as a memory control signal.

The comparator 1504 compares the count value of the counter 1501 with the phase 1505, and
When the count value is equal to the phase 1505, a high-level signal is output; otherwise, a low-level signal is output. If the vertical synchronizing signal and the horizontal synchronizing signal correspond to the interlaced scanning input signal, the phase 1505
Is set to the number of lines in one of the interlaced scanning fields.

The 1-bit memory 1506 stores the output of the comparator 1504 in response to the rising edge of the vertical synchronizing signal, and outputs the stored value as a field identification signal until the next rising edge of the vertical synchronizing signal. As a result, the next 1 of the field having the same number of lines as the phase 1505
In a field, the field identification signal is at a high level, and in other fields, the field identification signal is at a low level. The field identification signal is used to identify a field during interlaced scanning.

FIGS. 20 (a) to 20 (h) show signal waveforms at various parts of the timing control circuit. In FIG. 20, the vertical axis indicates signal logic (on / off) or the count value of the counter, and the horizontal axis indicates time.

FIG. 1A shows a waveform of a vertical synchronizing signal. FIG. 20B shows a waveform of the horizontal synchronization signal. FIG.
0 (c) indicates the waveform of the video clock. The vertical control signal, the horizontal control signal, and the video clock are input to the timing control circuit.

FIG. 20D shows the count value of the counter 1501. The count value of the counter 1501 is initialized in response to a vertical synchronization signal, and is incremented by one in response to a horizontal synchronization signal. FIG. 20E shows the count value of the counter 1502. The count value of the counter 1502 is initialized in response to a horizontal synchronization signal, and is incremented by one in response to a video clock. The count value of the counter 1501 and the count value of the counter 1502 are input to the memory 1503 as addresses.

FIG. 20F shows a waveform of a memory control signal output from the memory 1503. In the example shown in FIG. 20F, a set of three signals is output as a memory control signal in response to the address input to the memory 1503.

FIG. 20G shows a waveform of a signal output from the comparator 1504.

FIG. 20H shows a 1-bit memory 1506.
2 shows a waveform of a signal output from the oscilloscope.

FIG. 21 shows the relationship between the address of the memory 1503 and the data stored at that address. FIG.
In the example shown in FIG. 9, the address of the memory 1503 is 91
It is represented by 0 × M + N. Here, M is the counter 1
A count value 501 is shown, and takes any value from 0 to 261. N indicates the count value of the counter 1502,
To 909. Each address of the memory 1503 stores 3-bit data. The memory 1503 outputs 3-bit data corresponding to the address as a memory control signal.

For example, assume that the count value of the counter 1501 is 3 and the count value of the counter 1502 is 908. In this case, the address 910 × 3 + 908 is input to the memory 1503. As a result, memory 1
Reference numeral 503 outputs 3-bit data (0, 1, 0) corresponding to the address 910 × 3 + 908 as a memory control signal.

[0017]

By using the timing control circuit having the above configuration, a memory control signal having an arbitrary waveform can be generated. However, the timing control circuit has the following problems.

The first problem is that a large amount of memory is required, resulting in an increase in cost.

The second problem is that a counter and a comparator are required to generate the field identification signal, which increases the cost.

A third problem is that since the phases of the horizontal synchronizing signal and the vertical synchronizing signal cannot be changed, the timing at which the field discrimination signal changes and the timing at which the counter is initialized are restricted by the synchronizing signal.

An object of the present invention is to provide a timing control circuit which does not use a large-capacity memory, thereby reducing costs.

It is another object of the present invention to provide a timing control circuit with reduced cost by not using a counter and a comparator having a large number of bits for field identification.

Another object of the present invention is to provide a timing control circuit capable of changing the phases of the horizontal synchronizing signal and the vertical synchronizing signal and enabling a flexible operation.

[0024]

A timing control circuit according to the present invention has a first counter which is initialized by a first synchronization signal and counts a second synchronization signal, and wherein the count value of the first counter is a predetermined first value. A first comparator that outputs a signal that is at a first level when it is within the range and a second level otherwise, and a second comparator that is initialized by the second synchronization signal and counts a first clock signal A counter,
A second comparator for outputting a signal having a first level when the count value of the second counter is within a predetermined second range, and a second level otherwise; and an output of the first comparator. A first synthesizing circuit that generates a first timing control signal by synthesizing the output of the second comparator with the output of the second comparator, thereby achieving the above object.

The first synchronization signal is a vertical synchronization signal,
The second synchronization signal may be a horizontal synchronization signal.

The timing control circuit is initialized by a third synchronizing signal, and counts a fourth synchronizing signal.
A counter, a third comparator for outputting a signal having a first level when the count value of the third counter is within a predetermined third range, and a second level otherwise; A fourth counter which is initialized by a signal and counts a second clock signal; and a first level when the count value of the fourth counter is within a predetermined fourth range, and a second level otherwise. A fourth comparator for outputting a second timing control signal by combining the output of the third comparator and the output of the fourth comparator. Is also good.

[0027] The timing control circuit is configured to select one of a plurality of first synchronization signals in response to a selection signal.
A selection circuit, a second selection circuit that selects one of a plurality of second synchronization signals in response to the selection signal, and one of a plurality of first clock signals in response to the selection signal. A third selection circuit for selecting, an output of the first selection circuit is input to the first counter as the first synchronization signal, and an output of the second selection circuit is output as the second synchronization signal. The output of the third selection circuit, which is input to a first counter and the second counter, may be input to the second counter as the first clock signal.

Another timing control circuit of the present invention is a first counter which is initialized by a synchronizing signal and counts a clock signal, and has a first level when the count value of the first counter is within a predetermined range. A comparator that outputs a signal that is otherwise at a second level; and a signal that is output from the comparator is
A second counter that is initialized in response to the change to a level and counts the clock signal, an arithmetic circuit that calculates the count value of the second counter, an output of the comparator, and an output of the arithmetic circuit. And a synthesizing circuit that generates a timing control signal by synthesizing
Thereby, the above object is achieved.

Another timing control circuit according to the present invention is a first memory which is initialized by a vertical synchronizing signal and alternately outputs a first value and a second value in response to a horizontal synchronizing signal;
And a second memory for storing an output of the first memory in response to the vertical synchronization signal. The output of the second memory determines whether the number of lines in one vertical scanning period is odd or even. Determine. Thereby, the above object is achieved.

Another timing control circuit according to the present invention comprises:
A counter which is initialized by a synchronization signal and counts a clock signal; and a comparator which outputs a signal which becomes a first level when the count value of the counter is equal to a predetermined value, and which becomes a second level otherwise. And outputs the output of the comparator as a second synchronization signal. Thereby, the above object is achieved.

[0031] The first synchronization signal may be a horizontal synchronization signal.

The predetermined value is a predetermined first phase + n ×
Represented by a predetermined second phase, n may be an integer greater than or equal to zero.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a configuration of a timing control circuit according to Embodiment 1 of the present invention. The timing control circuit generates a timing control signal in synchronization with the vertical synchronization signal, the horizontal synchronization signal, and the video clock.

As shown in FIG. 1, the timing control circuit includes a 10-bit counter 101, an 11-bit counter 102, a comparator 103, phases 104 and 105,
Comparator 106, phases 107 and 108, and gate circuit 1
09.

The 10-bit counter 101 is initialized by a vertical synchronization signal and counts a horizontal synchronization signal. That is, the 10-bit counter 101 counts the number of one horizontal period included in one vertical period. One vertical period is
This is a period from one rising of the vertical synchronization signal to the next rising. One horizontal period is a period from one rising of the horizontal synchronizing signal to the next rising.

The 11-bit counter 102 is initialized by a horizontal synchronization signal and counts a video clock. That is, the 11-bit counter 102 counts the number of video clock periods included in one horizontal period. The cycle of the video clock is a period from one rising of the video clock to the next rising.

The comparator 103 compares the count value of the counter 101 with the phases 104 and 105. The phase 104 is a predetermined lower limit, and the phase 105 is a predetermined upper limit. The comparator 103 outputs a high-level signal when the count value of the counter 101 is equal to or more than the phase 104 and equal to or less than the phase 105, and outputs a low-level signal otherwise. The signal output from the comparator 103 is input to the gate circuit 109.

The comparator 106 compares the count value of the counter 102 with the phases 107 and 108. Phase 107 is a predetermined lower limit, and phase 108 is a predetermined upper limit. Comparator 106 outputs a high-level signal when the count value of counter 102 is greater than or equal to phase 107 and less than or equal to phase 108, and outputs a low-level signal otherwise. The signal output from the comparator 106 is input to the gate circuit 109.

Gate circuit 109 performs an AND operation on the signal output from comparator 103 and the signal output from comparator 106, and outputs the result as a timing control signal. Note that the operation performed on the signal output from the comparator 103 and the signal output from the comparator 106 is not limited to the logical product operation. It is also within the scope of the present invention to perform an arbitrary combining operation including a logical operation other than an AND operation on the signal output from the comparator 103 and the signal output from the comparator 106.

As described above, the comparator 103 generates a signal which is at a high level only during a predetermined first period of one vertical period. During the predetermined first period, the phase 104 and the phase 105
Defined by The comparator 106 generates a signal that becomes high level only during a predetermined second period in one horizontal period. The predetermined second period is defined by the phase 107 and the phase 108. By combining the signal output from the comparator 103 and the signal output from the comparator 106 by an arbitrary method, a timing control signal is obtained. Thus, the timing control signal can be generated without using a large-capacity memory. As a result, the cost of the timing control circuit is reduced.

FIGS. 2A to 2H show waveforms of signals of various parts of the timing control circuit of FIG. In FIG. 2, the vertical axis indicates the logic of the signal (on / off) or the count value of the counter, and the horizontal axis indicates the time. Here, phase 10
Assume that 4 is set to 64 and phase 105 is set to 159. It is also assumed that phase 107 is set to 576 and phase 108 is set to 703. Note that the phases 104, 105, 107 and 1
The value of 08 shows an example, and is not limited to these values.

FIG. 2A shows the waveform of the vertical synchronizing signal. FIG. 2B shows the waveform of the horizontal synchronization signal. FIG.
(C) shows the waveform of the video clock. The vertical control signal, the horizontal control signal, and the video clock are input to the timing control circuit.

FIG. 2D shows the count value of the counter 101. The count value of the counter 101 is initialized in response to a vertical synchronization signal, and is incremented by one in response to a horizontal synchronization signal. The count value of the counter 101 is output to the comparator 103.

FIG. 2E shows the count value of the counter 102. The count value of the counter 102 is initialized in response to a horizontal synchronization signal, and is incremented by one in response to a video clock. The count value of the counter 102 is output to the comparator 106.

FIG. 2F shows a waveform of a signal output from the comparator 103. The signal output from the comparator 103 is at a high level when the count value of the counter 101 is between 64 and 159, and is at a low level during other periods.

FIG. 2G shows a waveform of a signal output from the comparator 106. The signal output from the comparator 106 is at a high level when the count value of the counter 102 is between 576 and 703 and at a low level during other periods.

FIG. 2H shows a waveform of a signal output from the gate circuit 109.

The waveforms of the vertical synchronizing signal, the horizontal synchronizing signal and the video clock are shown in FIGS. 2 (a), (b) and (c).
However, the present invention is not limited to the above. As long as the number of one horizontal period included in one vertical period and the number of periods of the video clock included in one horizontal period are counted, the vertical synchronization signal, the horizontal synchronization signal, and the video clock can have any waveforms. .

The number of bits of the counter 101 is not limited to 10. The number of bits of the counter 102 is not limited to eleven.

FIG. 3 shows an example of a circuit utilizing a timing control signal generated by the timing control circuit of FIG. The circuit shown in FIG. 3 is a part of a circuit for synthesizing a small screen of a progressive scanning NTSC signal. Here, the NTSC signal of the progressive scanning is a video signal of about 60 frames per second, with one horizontal period (one line) consisting of 910 pixels and one vertical period (one frame) consisting of 525 lines.

In FIG. 3, a selector 201 responds to a selection signal S204 by selecting a first NTSC input video signal S201 (see FIG. 4A) as a main screen and a second NTSC input video signal as a sub-screen. S202 (see FIG. 4B)
By selecting one of the above, a third NTSC video signal S203 (see FIG. 4C) is generated. For example, the timing control circuit of FIG.
4 is used to generate

(Embodiment 2) FIG. 5 shows a configuration of a timing control circuit according to Embodiment 2 of the present invention. The timing control circuit generates a timing control signal in synchronization with the horizontal synchronization signal and the video clock.

As shown in FIG. 5, the timing control circuit includes an 11-bit counter 102, a comparator 106,
It includes phases 107 and 108, a 4-bit counter 301, and gate circuits 302 and 303. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will not be repeated.

The 4-bit counter 301 is provided for the comparator 106
Are initialized in response to the change of the signal output from the high level to the low level, and the video clock is counted.

Gate circuit 302 performs a predetermined logical operation on the count value of counter 301, and outputs the result to gate circuit 303. In the present embodiment, the gate circuit 3
02 outputs to the gate circuit 303 a signal that goes high only when the least significant bit of the count value of the counter 301 is low. However, the operation performed by the gate circuit 302 is not limited to such an operation.

Gate circuit 303 performs an AND operation on the signal output from comparator 106 and the signal output from gate circuit 302, and outputs the result as a timing control signal. Note that the operation performed on the signal output from the comparator 106 and the signal output from the gate circuit 302 is not limited to the logical product operation. It is also within the scope of the present invention to perform an arbitrary combining operation including a logical operation other than an AND operation on the signal output from the comparator 106 and the signal output from the gate circuit 302.

As described above, the timing control signal can be generated without using a large-capacity memory. As a result, the cost of the timing control circuit is reduced.

FIGS. 6A to 6G show waveforms of signals of respective parts of the timing control circuit of FIG. In FIG. 6, the vertical axis indicates the signal logic (on / off) or the count value of the counter, and the horizontal axis indicates time. Here, it is assumed that one horizontal period is 910 video clocks, the phase 107 is set to 4, and the phase 108 is set to 903. Note that the values of the phases 107 and 108 are merely examples, and the present invention is not limited to these values.

FIG. 6A shows the waveform of the horizontal synchronizing signal. FIG. 6B shows the waveform of the video clock. A horizontal synchronization signal and a video clock are input to the timing control circuit.

FIG. 6C shows the count value of the counter 102. The count value of the counter 102 is initialized in response to a horizontal synchronization signal, and is incremented by one in response to a video clock. The count value of the counter 102 is output to the comparator 106.

FIG. 6D shows the count value of the counter 301. The count value of the counter 301 is
6 is initialized in response to the change of the signal output from 6 from a high level to a low level, and is initialized in response to a video clock.
It is incremented by one. The count value of the counter 301 is output to the gate circuit 302. In this example, at the point where the count value of the counter 102 changes from 903 to 904, the signal output from the comparator 106 changes from high level to low level. Therefore, when the count value of the counter 102 changes from 903 to 904,
The count value of 01 is initialized to 0.

FIG. 6E shows the waveform of the signal output from the comparator 106. The signal output from the comparator 106 is at a high level when the count value of the counter 102 is between 4 and 903 and at a low level during other periods.

FIG. 6F shows a waveform of a signal output from the gate circuit 302. The gate circuit 302 operates when the least significant bit of the count value of the counter 301 is low (that is, when the count value of the counter 102 is 904, 9).
06, 908, 0, 2,...), And outputs a low-level signal otherwise.

FIG. 6G shows a waveform of a signal output from the gate circuit 303.

The waveforms of the horizontal synchronizing signal and the video clock are not limited to those shown in FIGS. 6 (a) and 6 (b). As long as the number of periods of the video clock included in one horizontal period is counted, the horizontal synchronization signal and the video clock may have any waveform.

The number of bits of the counter 102 is not limited to eleven. The number of bits of the counter 301 is not limited to four.

(Embodiment 3) FIG. 7 shows a configuration of a timing control circuit according to Embodiment 3 of the present invention. The timing control circuit generates a timing control signal 1 in synchronization with the vertical synchronization signal 1, the horizontal synchronization signal 1, and the video clock 1, and generates the vertical synchronization signal 2, the horizontal synchronization signal 2, and the video clock 2
The timing control signal 2 is generated in synchronization with

The timing control circuit shown in FIG. 7 includes a circuit for generating timing control signal 1 and a circuit for generating timing control signal 2. The configuration of each circuit is the same as the configuration of the timing control circuit of FIG. Therefore, a detailed description is omitted here.

FIGS. 8A to 8P show waveforms of signals of respective parts of the timing control circuit of FIG. In FIG. 8, the vertical axis indicates the logic of the signal (on / off) or the count value of the counter, and the horizontal axis indicates the time. Here, phase 10
4, 105, 107 and 108 are 64,
Assume that they are set to 159, 576 and 703. Also, phases 504, 505, 507 and 508
Are set to 0, 95, 0, 127, respectively. The values of the phases 104, 105, 107 and 108 and the phases 504, 505, 507 and 508
Are merely examples, and the present invention is not limited to these values.

FIG. 8A shows the waveform of the vertical synchronizing signal 1. FIG. 8B shows the waveform of the horizontal synchronization signal 1. FIG.
(C) shows the waveform of the video clock 1. The vertical control signal 1, the horizontal control signal 1, and the video clock 1 are input to the timing control circuit.

FIG. 8D shows the count value of the counter 101. The count value of the counter 101 is initialized in response to the vertical synchronization signal 1, and is incremented by one in response to the horizontal synchronization signal 1. The count value of the counter 101 is output to the comparator 103.

FIG. 8E shows the count value of the counter 102. The count value of the counter 102 is initialized in response to the horizontal synchronization signal 1, and is incremented by one in response to the video clock 1. The count value of the counter 102 is output to the comparator 106.

FIG. 8F shows a waveform of a signal output from the comparator 103. The signal output from the comparator 103 is at a high level when the count value of the counter 101 is between 64 and 159, and is at a low level during other periods.

FIG. 8G shows a waveform of a signal output from the comparator 106. The signal output from the comparator 106 is at a high level when the count value of the counter 102 is between 576 and 703 and at a low level during other periods.

FIG. 8H shows the waveform of the signal output from the gate circuit 109. The signal output from the gate circuit 109 is output from the timing control circuit as the timing control signal 1.

FIG. 8 (i) shows the waveform of the vertical synchronizing signal 2. FIG. 8J shows the waveform of the horizontal synchronization signal 2. FIG.
(K) shows the waveform of the video clock 2. The vertical control signal 2, the horizontal control signal 2, and the video clock 2 are input to the timing control circuit.

FIG. 8 (l) shows the count value of the counter 501. The count value of the counter 501 is initialized in response to the vertical synchronization signal 2, and is incremented by one in response to the horizontal synchronization signal 2. The count value of the counter 501 is output to the comparator 503.

FIG. 8 (m) shows the count value of the counter 502. The count value of the counter 502 is initialized in response to the horizontal synchronization signal 2, and is incremented by one in response to the video clock 2. The count value of the counter 502 is output to the comparator 506.

FIG. 8 (n) shows the waveform of the signal output from the comparator 503. The signal output from the comparator 503 is at a high level when the count value of the counter 501 is between 0 and 95, and is at a low level during other periods.

FIG. 8 (o) shows the waveform of the signal output from the comparator 506. The signal output from the comparator 506 is at a high level when the count value of the counter 502 is 0 or more and 127 or less, and is at a low level during other periods.

FIG. 8 (p) shows the waveform of the signal output from the gate circuit 509. The signal output from the gate circuit 509 is output as the timing control signal 2 from the timing control circuit.

The waveforms of the vertical synchronizing signal 1, the horizontal synchronizing signal 1 and the video clock 1 are not limited to those shown in FIGS. 8 (a), 8 (b) and 8 (c). As long as the number of one horizontal period included in one vertical period and the number of periods of the video clock included in one horizontal period are counted, the vertical synchronization signal 1, the horizontal synchronization signal 1, and the video clock 1 have arbitrary waveforms. Can have. The same applies to the vertical synchronization signal 2, the horizontal synchronization signal 2, and the video clock 2.

The counter 101 and the counter 50
The number of bits of 1 is not limited to 10. The bit numbers of the counter 102 and the counter 502 are not limited to eleven.

FIG. 9 shows an example of a circuit using the timing control signal 1 and the timing control signal 2 generated by the timing control circuit of FIG. The circuit of FIG.
This is a part of a circuit for synthesizing a small screen of an asynchronous signal of a progressive scanning NTSC signal. Here, the NTSC signal of the progressive scanning is a video signal of about 60 frames per second, with one horizontal period (one line) consisting of 910 pixels and one vertical period (one frame) consisting of 525 lines.

In FIG. 9, in response to a selection signal S604, a selector 601 selects a first NTSC input video signal S601 (see FIG. 10A) as a main screen and a second NTSC video signal S606 as a sub-screen. (See FIG. 10B)
By selecting one of the above, a third NTSC video signal S603 (see FIG. 10C) is generated.

The frame memory 602 stores the second NTSC
The input video signal S602 is stored, and the stored signal is output to the selector 601 as a second NTSC video signal S606. The timing of writing the second NTSC input video signal S602 to the frame memory 602 is defined by the write signal S605. Frame memory 602
The timing at which the second NTSC video signal S606 is read from is determined by the read signal. The write signal S605 and the read signal are asynchronous with each other. The read signal is also used as the selection signal S604.

The timing control signal 1 generated by the timing control circuit shown in FIG.
Also, it can be used as the selection signal S604. FIG.
The timing control signal 2 generated by the timing control circuit of (1) can be used, for example, as the write signal S605.

In this way, it is possible to generate a timing control signal for synthesizing the two input signals S601 and S602, which are asynchronous with each other, in synchronism with the signal S601. Further, a timing control signal can be generated without using a large-capacity memory. As a result, the cost of the timing control circuit is reduced.

(Embodiment 4) FIG. 11 shows a configuration of a timing control circuit according to Embodiment 4 of the present invention. The timing control circuit of FIG. 11 includes a selection circuit 701, a selection circuit 702, and a selection circuit 703 in addition to the configuration of the timing control circuit of FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will not be repeated.

The selection circuit 701 selects the vertical synchronization signal 2 when the synchronization selection signal is at a high level, and selects the vertical synchronization signal 1 when the synchronization selection signal is at a low level. The vertical synchronization signal selected by the selection circuit 701 is input to the counter 101.

The selection circuit 702 selects the horizontal synchronization signal 2 when the synchronization selection signal is at a high level, and selects the horizontal synchronization signal 1 when the synchronization selection signal is at a low level. The horizontal synchronization signal selected by the selection circuit 702 is input to the counter 101 and the counter 102.

The selection circuit 703 selects the video clock 2 when the synchronization selection signal is at a high level, and selects the video clock 1 when the synchronization selection signal is at a low level. The video clock selected by the selection circuit 703 is input to the counter 102.

FIGS. 12 (a) to 12 (p) show signal waveforms at various parts of the timing control circuit of FIG. In FIG. 12, the vertical axis indicates the logic of the signal (on / off) or the count value of the counter, and the horizontal axis indicates the time. In FIG. 12, with respect to the vertical synchronization signal 1, the horizontal synchronization signal 1, and the video clock 1, one vertical period is 262 lines,
The horizontal period is 910 video clocks. Further, regarding the vertical synchronizing signal 2, the horizontal synchronizing signal 2, and the video clock 2, one vertical period is 260 lines, and one horizontal period is 9 lines.
14 video clocks. Here, the phases 104, 10
5, 107 and 108 are 2, 259,
Assume that it is set to 2,908. Note that phase 1
The values of 04, 105, 107 and 108 are merely examples, and the present invention is not limited to these values.

When the synchronization selection signal is at the low level, the output of the comparator 103 is, as shown in FIG.
It goes high during the following periods, and goes low during other periods. The output of the comparator 106 is shown in FIG.
As shown in FIG. 2 (g), when the count value of the counter 102 is equal to or more than 2 and equal to or less than 908, it is at the high level, and at other times, it is at the low level. The gate circuit 109 performs an AND operation on the output of the comparator 103 and the output of the comparator 106. As a result, the signal shown in FIG. However,
The logic of the gate circuit 109 is not limited to only the logical product.

When the synchronization selection signal is at a high level, the output of the comparator 103 is, as shown in FIG.
It goes high during the following periods, and goes low during other periods. The output of the comparator 106 is shown in FIG.
As shown in FIG. 2 (o), when the count value of the counter 102 is equal to or more than 2 and equal to or less than 908, it is at a high level, and at other times it is at a low level. The gate circuit 109 performs an AND operation on the output of the comparator 103 and the output of the comparator 106. As a result, the signal shown in FIG. However,
The logic of the gate circuit 109 is not limited to only the logical product.

The signal output from the gate circuit 109 regardless of whether the synchronization selection signal is at a high level or a low level,
It can be used as a timing control signal.

As described above, by adding the selection circuits 701, 702 and 703 to the timing control circuit,
It is possible to generate a timing control signal corresponding to each of two synchronization signals. Thus, the timing control circuit can be shared for two systems of synchronization signals only by adding a selection circuit. This means
Reduce the cost of the timing control circuit.

The waveforms of the vertical synchronizing signal 1, the horizontal synchronizing signal 1 and the video clock 1 are not limited to those shown in FIGS. 12 (a), 12 (b) and 12 (c). As long as the number of one horizontal synchronization period included in one vertical period and the number of video clock periods included in one horizontal period are counted, the vertical synchronization signal 1, the horizontal synchronization signal 1, and the video clock 1 have arbitrary waveforms. May be provided. Vertical sync signal 2, horizontal sync signal 2
The same applies to the video clock 2.

The number of bits of the counter 101 is not limited to 10. The number of bits of the counter 102 is not limited to eleven. Further, the selection circuits 701, 702 and 70
In each of the three, one of the three or more synchronization signals may be selected.

(Embodiment 5) FIG. 13 shows a configuration of a timing control circuit according to Embodiment 5 of the present invention. The timing control circuit generates a field identification signal in synchronization with the vertical synchronization signal and the horizontal synchronization signal.

As shown in FIG. 13, the timing control circuit includes a 1-bit counter 901 and a 1-bit memory 9.
02.

The 1-bit counter 901 outputs a signal which is initialized by a vertical synchronizing signal and alternately repeats a high level and a low level in response to a horizontal synchronizing signal.

The 1-bit memory 902 responds to the change of the vertical synchronization signal from the low level to the high level.
The output of the counter 901 is stored, and the output is stored and continuously output until the vertical synchronization signal next changes from the low level to the high level. The output of the one-bit memory 902 is used as a field identification signal.

FIGS. 14A to 14D show waveforms of signals of various parts of the timing control circuit of FIG. In FIG. 14, the vertical axis indicates signal logic (on / off) or the count value of the counter, and the horizontal axis indicates time. In FIG. 14, with respect to the vertical synchronization signal and the horizontal synchronization signal, 262 lines and 263 lines are alternately repeated during one vertical period. 1
The bit counter 901 is initialized by a vertical synchronization signal, and its output is inverted by a horizontal synchronization signal. Therefore, when the number of lines in one vertical period is odd, the 1-bit memory 902 stores a low level during the next successive vertical period, and the output thereof also becomes low level (FIG. 1).
4 (d)). Similarly, when the number of lines in one vertical period is an even number, the 1-bit memory 902 stores a high level during the next successive one vertical period, and its output also becomes high level (FIG. 14 ( d)).

As described above, a counter and a comparator having a large number of bits are not required to generate the field identification signal. Thereby, the cost of the timing control circuit can be eliminated.

The vertical synchronizing signal shown in FIG.
The waveform of the horizontal synchronization signal shown in FIG. 14B is an example.

(Embodiment 6) FIG. 15 shows a configuration of a timing control circuit according to Embodiment 6 of the present invention. The timing control circuit generates a horizontal synchronization signal 2 in synchronization with the horizontal synchronization signal 1 and the video clock.

As shown in FIG. 15, the timing control circuit includes an 11-bit counter 1101 and a comparator 110.
2 and phase 1103.

The 11-bit counter 1101 is initialized by the horizontal synchronizing signal 1 and counts a video clock.

The comparator 1102 compares the count value of the counter 1101 with the phase 1103, and
When the count value is equal to the phase 1103, a high level signal is output. Otherwise, a low level signal is output.

FIGS. 16 (a) to 16 (d) show signal waveforms at various parts of the timing control circuit of FIG. In FIG. 16, the vertical axis indicates the logic of the signal (on / off) or the count value of the counter, and the horizontal axis indicates the time. In FIG. 16, with respect to the horizontal synchronization signal 1 and the video clock, one horizontal period is 910 video clocks. Assume that phase 1103 is set to eight. Note that the value of the phase 1103 is an example, and is not limited to this value.

The counter 1101 is initialized by the horizontal synchronization signal 1 shown in FIG. 16A, and counts the video clock shown in FIG. 16B. When the count value of the counter 1101 becomes 8, the count value of the counter 1101 becomes equal to the phase 1103, so that the output of the comparator 1102 becomes high level. The output of the comparator 1102 is output as the horizontal synchronization signal 2 (FIG. 16D).

As described above, according to the timing control circuit of FIG. 15, the phase of the horizontal synchronizing signal can be arbitrarily changed. As a result, it is possible to flexibly set the timing at which the field identification signal changes and the timing at which the counter is initialized.

The horizontal synchronizing signal 1 shown in FIG. 16A and the waveform of the video clock shown in FIG. 16B are examples. Further, the number of bits of the counter 1101 is not limited to eleven.

(Seventh Embodiment) FIG. 17 shows a configuration of a timing control circuit according to a seventh embodiment of the present invention. The timing control circuit generates a horizontal synchronization signal 2 in synchronization with the horizontal synchronization signal 1 and the video clock.

As shown in FIG. 17, the timing control circuit includes an 11-bit counter 1101 and a comparator 130.
1 and phases 1302, 1303.

The 11-bit counter 1101 is initialized by the horizontal synchronizing signal 1 and counts a video clock.

In the comparator 1301, the count value of the counter 1101 is (phase 1302 + n × phase 1303) (n =
0, 1, 2, 3,. . . . ), A high-level signal is output; otherwise, a low-level signal is output.

FIGS. 18A to 18D show waveforms of signals of respective parts of the timing control circuit of FIG. In FIG. 18, the vertical axis indicates signal logic (on / off) or the count value of the counter, and the horizontal axis indicates time. In FIG. 18, regarding the horizontal synchronization signal 1 and the video clock, one horizontal period is 910 video clocks. Assume that phase 1302 is set to 8 and phase 1303 is set to 455. It should be noted that the values of the phases 1103 and 1303 are merely examples, and the counter 1101 is not limited to these values. The counter 1101 is initialized by the horizontal synchronization signal 1 in FIG. Count the video clock. When the count value of the counter 1101 reaches 8, the count value of the counter 1101 and (phase 1
302 + 0 × phase 1303), the output of the comparator 1301 becomes high level. Further, when the count value of the counter 1101 becomes 463, the count value of the counter 1101 becomes equal to (phase 1302 + 1 × phase 1303), so that the output of the comparator 1301 becomes high level. The output of the comparator 1301 is output as the horizontal synchronization signal 2 (FIG. 18D).

As described above, according to the timing control circuit of FIG. 17, the phase of the horizontal synchronizing signal can be arbitrarily changed, and the horizontal synchronizing signal 2 having twice the frequency of the horizontal synchronizing signal 1 is obtained. It becomes possible. As a result, it is possible to flexibly set the timing for initializing the counter, and further to set the horizontal timing having a frequency n times (n = 1, 2, 3,...) Of the input horizontal synchronization signal. A synchronization signal can be obtained.

The horizontal synchronizing signal 1 shown in FIG. 18A and the waveform of the video clock shown in FIG. 18B are examples. Further, the number of bits of the counter 1101 is not limited to eleven.

[0123]

According to the first aspect of the present invention, it is possible to provide a timing control circuit for generating a timing control signal without using a large-capacity memory by combining a counter and a comparator. . Thus, the cost of the timing control circuit can be reduced.

According to the third aspect of the present invention, the first timing control signal and the second timing control signal can be generated independently. Thereby, it is possible to generate the asynchronous first timing control signal and the second timing control signal. As a result, it is possible to control the writing and reading of the asynchronous signal to and from the memory, which has the effect of enabling more flexible timing control.

According to the fourth aspect of the present invention, by providing the first to third selection circuits, a single timing control circuit can be commonly used for a plurality of systems of synchronization signals. To Thus, the cost of the timing control circuit can be reduced.

According to the fifth aspect of the present invention, it is possible to provide a timing control circuit for generating a timing control signal without using a large-capacity memory by combining a counter and a comparator. This allows
The cost of the timing control circuit can be reduced.

According to the sixth aspect of the present invention, it is possible to perform field identification using the first memory and the second memory having a simple configuration without using a counter and a comparator having a large number of bits. It is. Thus, the cost of the timing control circuit can be reduced.

According to the invention described in claim 7, it is possible to arbitrarily change the phase of the first synchronization signal. The second synchronization signal is a synchronization signal after the phase has been changed. This makes it possible to flexibly set the timing at which the field identification signal changes and the timing at which the counter is initialized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a timing control circuit according to a first embodiment of the present invention;

FIGS. 2A to 2H are diagrams showing waveforms of signals of respective parts of a timing control circuit.

FIG. 3 is a diagram illustrating an example of a circuit that uses a timing control signal.

FIGS. 4A to 4C are diagrams for explaining synthesis of video signals.

FIG. 5 is a diagram showing a configuration of a timing control circuit according to a second embodiment of the present invention.

FIGS. 6A to 6G are diagrams showing signal waveforms of respective parts of the timing control circuit.

FIG. 7 is a diagram illustrating a configuration of a timing control circuit according to a third embodiment of the present invention;

FIGS. 8A to 8P are diagrams showing waveforms of signals of respective parts of the timing control circuit.

FIG. 9 is a diagram illustrating an example of a circuit that uses a timing control signal 1 and a timing control signal 2.

FIGS. 10A to 10C are diagrams for explaining synthesis of video signals.

FIG. 11 is a diagram showing a configuration of a timing control circuit according to a fourth embodiment of the present invention.

FIGS. 12A to 12P are diagrams showing waveforms of signals of respective parts of the timing control circuit.

FIG. 13 is a diagram showing a configuration of a timing control circuit according to a fifth embodiment of the present invention.

FIGS. 14A to 14D are diagrams illustrating waveforms of signals of respective parts of the timing control circuit.

FIG. 15 is a diagram illustrating a configuration of a timing control circuit according to a sixth embodiment of the present invention.

FIGS. 16A to 16D are diagrams showing waveforms of signals of respective parts of the timing control circuit.

FIG. 17 is a diagram illustrating a configuration of a timing control circuit according to a seventh embodiment of the present invention.

FIGS. 18A to 18D are diagrams showing waveforms of signals of respective parts of the timing control circuit.

FIG. 19 is a diagram showing a configuration of a conventional timing control circuit of a video signal processor.

FIGS. 20A to 20H are diagrams showing waveforms of signals of respective parts of the timing control circuit.

FIG. 21 is a diagram illustrating a relationship between an address of a memory 1503 and data stored at the address.

[Explanation of symbols]

 101 10-bit counter 102 11-bit counter 103 Comparator 104, 105 Phase 106 Comparator 107, 108 Phase 109 Gate circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoichiro Miki 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. 72) Inventor Masahiro Tani 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Kenta Sakawa 1006, Kadoma Kadoma, Kadoma, Osaka Pref. 3-6-12 Kitaaoyama, Minato-ku Fuji Aoyama Building Texas Instruments Japan Co., Ltd.

Claims (9)

[Claims] A first synchronization signal which is initialized by a first synchronization signal;
A first counter that counts a synchronization signal; and a first comparison that outputs a signal that has a first level when the count value of the first counter is within a predetermined first range, and has a second level otherwise. A second counter initialized by the second synchronization signal and counting a first clock signal; and a first level when a count value of the second counter is within a predetermined second range, A first comparator that generates a first timing control signal by synthesizing an output of the first comparator and an output of the second comparator, the second comparator outputting a signal having a second level in the case of A timing control circuit comprising a synthesis circuit. 2. The first synchronization signal is a vertical synchronization signal, and the second synchronization signal is a horizontal synchronization signal.
4. The timing control circuit according to 1. 3. Initialized by a third synchronization signal, the fourth synchronization signal
A third counter for counting a synchronization signal; and a third comparison for outputting a signal having a first level when the count value of the third counter is within a third predetermined range, and a second level otherwise. A fourth counter initialized by the fourth synchronization signal and counting a second clock signal; and a first level when a count value of the fourth counter is within a predetermined fourth range, And a fourth comparator for generating a second timing control signal by combining the output of the third comparator and the output of the fourth comparator. The timing control circuit according to claim 1, further comprising a synthesis circuit. 4. A first selection circuit for selecting one of a plurality of first synchronization signals in response to a selection signal, and a first selection circuit for selecting one of a plurality of second synchronization signals in response to the selection signal.
A second selection circuit for selecting one of the plurality of first clock signals in response to the selection signal, and an output of the first selection circuit, The first synchronization signal is input to the first counter, the output of the second selection circuit is input to the first counter and the second counter as the second synchronization signal, and the output of the third selection circuit is ,
The timing control circuit according to claim 1, wherein the first clock signal is input to the second counter as the first clock signal. 5. A first counter which is initialized by a synchronization signal and counts a clock signal; and a first level when a count value of the first counter is within a predetermined range, and a second level otherwise. A comparator that outputs a signal of a level; a second counter that is initialized in response to the signal output from the comparator changing from the first level to the second level and counts the clock signal A timing control circuit comprising: an arithmetic circuit that calculates a count value of the second counter; and a synthesizing circuit that generates a timing control signal by synthesizing an output of the comparator and an output of the arithmetic circuit. 6. A first memory, which is initialized by a vertical synchronizing signal and outputs a first value and a second value alternately in response to a horizontal synchronizing signal, and in response to the vertical synchronizing signal, And a second memory for storing an output of the first memory, wherein the timing control circuit determines whether the number of lines in one vertical scanning period is an odd number or an even number based on an output of the second memory. 7. A counter which is initialized by a first synchronization signal and counts a clock signal; and a first level when the count value of the counter is equal to a predetermined value, and a second level otherwise. And a comparator that outputs a signal, and outputs an output of the comparator as a second synchronization signal. 8. The timing control circuit according to claim 7, wherein said first synchronization signal is a horizontal synchronization signal. 9. The method according to claim 6, wherein the predetermined value is a predetermined first phase + n
The timing control circuit according to claim 7, wherein x is represented by a predetermined second phase, and n is an integer equal to or greater than 0.