JPH11112328A - Low-consumption logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a subthreshold current which flows when a transistor is off by connecting a transistor which turns on and off according to a control signal controlling the on/off state of a transmission gate between one end of an inverter whose another end is connected to a power source and the ground. SOLUTION: A transistor M3 which inputs a control signal CNT at its gate is connected to the source terminal of a transistor M4 as a driver constituting the inverter 10 inverting and outputting a clock CLK. The subthreshold current which flows when the transistor M4 turns off is reducible by turning off the transistor M3, so that the power consumption can be reduced. Further, the clock CLK having passed through the transmission gate M1 which turns on when the control signal CNT is 'H' only passes through one gate stage of the transistor M4 or M5 and then a signal CLKA as its inverted signal can be outputted fast.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS (Complete) that outputs a clock only when a control signal is valid.
mentary Metal Oxide Semiic
The present invention relates to a low-consumption logic circuit based on a gated clock circuit constituted by transistors, and particularly relates to a low-consumption logic circuit suitable for use in a semiconductor integrated circuit at high speed and low power consumption.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration of a conventional low-consumption logic circuit. In FIG. 5, reference numeral 1 denotes a control signal CNT and a clock CLK which are input, and performs a logical product operation of the control signal CNT and the clock CLK. The NAND circuit 2 inverts the result of the operation and outputs the inverted signal, the inverter 2 inverts the output signal of the NAND circuit 1 and outputs the inverted signal, and the inverter 3 inverts the output signal of the inverter 2 and outputs the inverted signal CLKA. It is an inverter.

Next, the operation will be described. Here, FIG.
Is a time chart for explaining the operation of the conventional low-consumption logic circuit.

[0004] This low-consumption logic circuit operates, for example, from time t1 to time t1.
As shown during t2, the inverter 3 outputs the inverted signal CLKA of the clock CLK only when the control signal CNT is at "H" level. Therefore, before the time t1 and after the time t2, since the control signal CNT is at the “L” level, the signal CLKA is in the “H” state.

Another conventional example of this kind is disclosed in, for example,
There is a semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 2-154915. That is, a transistor is added to the source side of the CMOS input / output circuit, and the signal output is controlled by a control signal.
By not setting the output to the intermediate potential, the through current of the transistor on the input side is eliminated.

[0006]

Since the conventional low-consumption logic circuit is configured as described above, the period in which the signal CLKA which is the inverted signal of the clock CLK is not output, that is, the control signal CNT is "L". During the period of N
Although the channel transistor is turned off, it is not completely turned off because a subthreshold current (leakage current) flows at the time of turning off. When this is compared with the NAND circuit 1 and the inverter 2, Although the leak current also flows through the transistor of the inverter 2, since the transistor of the inverter 3 on the most output side is large as a general configuration, the amount of current flowing when the inverter 3 is turned off is larger. However, there is a problem that power consumption during operation is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and reduces a subthreshold current flowing when a transistor constituting a signal input / output inverter is off, thereby reducing power consumption of the transistor. It is an object of the present invention to obtain a low power consumption logic circuit.

[0008]

SUMMARY OF THE INVENTION A low consumption logic circuit according to the present invention inverts an input signal passed through a transmission gate and outputs the inverted signal, and connects between the other end of the inverter, one end of which is connected to a power supply, and ground. And a first transistor that is turned on / off in response to a first control signal that controls on / off of the transmission gate.

The low power consumption logic circuit according to the present invention has a second transistor connected between the other end of the inverter and the ground, which is turned on / off in response to an input signal passing through the transmission gate.

A low-consumption logic circuit according to the present invention has a third transistor connected between an inverter and a ground, which is turned off by a second control signal when an input signal is cut off by a transmission gate. It is.

The low power consumption logic circuit according to the present invention is characterized in that the first control signal has a level that turns off the transmission gate, an input signal that has passed through the transmission gate turns off the second transistor, and a second control signal. Indicates that the level at which the third transistor is turned off is 0V.

In the low power consumption logic circuit according to the present invention, the level of the second control signal for turning off the third transistor is a negative voltage.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a low-consumption logic circuit according to Embodiment 1 of the present invention. In FIG. 1, M1 is supplied with a control signal (first control signal) CNT supplied to a gate terminal G1 of an N-type transistor and supplied to a gate terminal G2 of a P-type transistor via an inverter 5 and supplied thereto. When the control signal CNT is at “H” level, the clock (input signal) CLK is passed,
A transmission gate M2 which cuts off the clock CLK when the signal is at the "L" level. The control signal CNT is supplied to the gate terminal of the transmission gate M1 via the inverter 5, and the drain terminal is connected to the output terminal of the transmission gate M1, the N-type transistor M4 and the P-type An N-type transistor connected to the gate terminal of the transistor M5 and having the source terminal grounded.

M3 is an N-type transistor (first transistor) in which the control signal CNT is supplied to the gate terminal, the drain terminal is connected to the source terminal of the transistor M4, and the source terminal is grounded. Gate terminal of M5, transmission gate M
1, an N-type transistor whose drain terminal is connected to the drain terminal of the transistor M5, M5 is a P-type transistor whose source terminal is connected to a power supply, and 10 is a transistor M4, M5 and the transistor M
4 and M5 are inverters that invert the signal supplied to the mutually connected gate terminals and output the inverted signal as a signal CLKA from the mutually connected drain terminals.

That is, the feature of the first embodiment is that the control signal CNT of the transmission gate M1 is supplied to the source terminal of the transistor M4 of the driver constituting the inverter 10 for inverting and outputting the clock CLK passed through the transmission gate M1. The point is that the transistor M3 serving as a gate input is connected to be configured. However, the clock CLK does not need to change at a constant cycle as long as the input signal changes between “L” and “H” alternately. The above “L” is 0 V, and “H” is the transmission gate M
1 and the potential for operating the transistors M2 to M5.

Next, the operation will be described. However, since the circuit of the first embodiment shown in FIG. 1 performs the same operation as the circuit of the conventional example shown in FIG. 5, the operation will be described with reference to the time chart of FIG. 6 used in the conventional example.

As shown before time t1 or after time t2,
When the control signal CNT is "L", the transmission gate M1 is turned off, the transistor M2 is turned on, and the node indicated by S becomes "L", so that the transistor M5 is turned on and the transistor M4 is turned off. Accordingly, the output signal CLKA becomes “H”. Further, the transistor M3 is in an off state because the control signal CNT is “L”.

At this time, the source voltage at the node indicated by T of the transistor M4 increases due to the drain-source leakage current of the transistor M3 flowing in the direction of arrow A. Assuming that the increased voltage is + V1 “V”, at this time, the gate voltage of the transistor M4 is 0 “V”.
The voltage between the gate and the source is reverse-biased at -V1 "V". This reverse bias raises the threshold voltage of transistor M4 to
4 when the source terminal is directly grounded, the threshold voltage is lower than the threshold voltage when the voltage between the gate and the source is 0 “V”.
Rise. In other words, the state in which the threshold voltage has increased is a state in which the depletion layer of the transistor M4 has expanded and the current path has narrowed.

Therefore, when the threshold voltage rises in this manner, the sub-threshold current I flowing in the direction of arrow A is
Means that the above-described conventional gate-source voltage is 0 V
In this case, the sub-threshold current I flowing is reduced. From this, when the transistor M3 is connected,
It can be seen that the amount of current flowing when the transistor M4 is off is smaller than in the conventional case.

On the other hand, as shown between times t1 and t2 in FIG. 6, when the control signal CNT is "H", the transmission gate M1 is turned on and the transistor M2 is turned off, so that the clock CLK is transmitted to the node S. Since the transistor M3 is turned on, the clock CLK is inverted by the transistors M4 and M5, and is output as the signal CLKA.

That is, when the control signal CNT is "H", the transmission gate M1 is on, and the clock CL passing through the transmission gate M1 is turned on.
Only when K passes through one gate of the transistor M4 or M5, the inverted signal CLKA can be output, and the inverted signal CLKA can be output at a high speed.

As described above, according to the first embodiment, the inverter 1 for inverting and outputting the clock CLK is output.
Since the transistor M3 having the control signal CNT as a gate input is connected to the source terminal of the transistor M4 serving as a driver constituting the driver 0, the transistor M3 is turned off without using a special circuit. The sub-threshold current flowing when the switch is off can be reduced, thereby obtaining an effect of reducing power consumption.

When the control signal CNT is "H", the clock CLK passing through the transmission gate M1 which is turned on only passes through one gate of the transistor M4 or M5, and the inverted signal CLK is obtained.
Since the configuration is such that A can be output, it is possible to obtain an effect that a signal CLKA obtained by inverting the clock CLK can be output at high speed.

Embodiment 2 FIG. FIG. 2 is a circuit diagram showing a configuration of a low power consumption logic circuit according to a second embodiment of the present invention.
However, in FIG. 2, portions corresponding to the respective portions of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 2, M6 is a transistor (second transistor) whose gate terminal is connected to the output terminal of the transmission gate M1, whose drain terminal is connected to the source terminal of the transistor M4, and whose source terminal is grounded.

Next, the operation will be described. However, since the circuit of the second embodiment shown in FIG. 2 performs the same operation as the circuit of the conventional example shown in FIG. 5, the operation will be described with reference to the time chart of FIG. 6 used in the conventional example.

As shown before time t1 or after time t2,
When the control signal CNT is “L”, the transmission gate M1 is turned off, the transistor M2 is turned on, and the node indicated by S becomes “L”, so that the transistor M5 is turned on, and the transistors M4 and M6 are turned off. ,
As a result, the output signal CLKA becomes “H”.

At this time, the source voltage of the transistor M4 at the node indicated by T rises due to the drain-source leakage current of the transistor M6 flowing in the direction of arrow A. Assuming that the increased voltage is + V2 “V”, at this time, the gate voltage of the transistor M4 is 0 “V”.
The voltage between the gate and the source will be reverse-biased at -V2 "V". This reverse bias increases the threshold voltage of the transistor M4.

As described above, when the threshold voltage increases, the subthreshold current I flowing in the direction of arrow A is reduced when the conventional gate-source voltage is 0 V, as described in the first embodiment. Sub-threshold current I flowing
Less than. This indicates that when the transistor M6 is connected, the amount of current flowing when the transistor M4 is turned off is smaller than that in the related art.

On the other hand, as shown between time t1 and time t2 in FIG. 6, when the control signal CNT is "H", the transmission gate M1 is turned on and the transistor M2 is turned off, so that the clock CLK is transmitted to the node S. Further, since the transistor M6 performs the same on / off operation as the transistor M4, the clock CLK is inverted by the transistors M4 and M5, and this is output as the signal CLKA.

That is, when the control signal CNT is "H", the transmission gate M1 is on, and the clock CL passing through the transmission gate M1 is turned on.
Only when K passes through one gate of the transistor M4 or M5, the inverted signal CLKA can be output, and the inverted signal CLKA can be output at a high speed.

As described above, according to the second embodiment, the inverter 1 for inverting and outputting the clock CLK is output.
Since the transistor M6 having the same gate input signal as the gate input signal of the transistor M4 is connected to the source terminal of the transistor M4 serving as the driver constituting the driver 0, the transistor M6 is turned off without using a special circuit. By doing so, the sub-threshold current flowing when the transistor M4 is off can be reduced, whereby an effect of reducing power consumption can be obtained.

When the control signal CNT is "H", the clock CLK that has passed through the transmission gate M1 that is turned on only passes through one gate of the transistor M4 or M5, and the inverted signal CLK is the signal CLK.
Since the configuration is such that A can be output, it is possible to obtain an effect that a signal CLKA obtained by inverting the clock CLK can be output at high speed.

Embodiment 3 FIG. 3 is a circuit diagram showing a configuration of a low-consumption logic circuit according to a third embodiment of the present invention.
However, in FIG. 3, the portions corresponding to the respective portions of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 3, a transistor M7 has a gate terminal to which a control signal (second control signal) CNT1 different from the control signal CNT is input, a drain terminal connected to the source terminal of the transistor M4, and a source terminal grounded. Third transistor).

Next, the operation will be described. However, since the circuit of the third embodiment shown in FIG. 3 performs the same operation as the circuit of the conventional example shown in FIG. 5, the operation will be described with reference to the time chart of FIG. 6 used in the conventional example.

As shown before time t1 or after time t2,
When the control signal CNT is “L”, the control signal CNT2 is also set to “L”. As a result, the transmission gate M1 is turned off, the transistor M2 is turned on, and the node indicated by S becomes "L", so that the transistor M5 is turned on, and the transistors M4 and M7 are turned off, whereby the output signal CLKA becomes "H". ".

At this time, the source voltage of the transistor M4 at the node indicated by T rises due to the drain-source leakage current of the transistor M7 flowing in the direction of arrow A. Assuming that the increased voltage is + V2 “V”, at this time, the gate voltage of the transistor M4 is 0 “V”.
The voltage between the gate and the source will be reverse-biased at -V2 "V". This reverse bias increases the threshold voltage of the transistor M4.

As described above, when the threshold voltage rises, the subthreshold current I flowing in the direction of arrow A is reduced when the conventional gate-source voltage is 0 V, as described in the first embodiment. Sub-threshold current I flowing
Less than. This indicates that, when the transistor M7 is connected, the amount of current flowing when the transistor M4 is off is smaller than in the conventional case.

At this time, if the source voltage of the node indicated by T of the transistor M4 is set to V3 "V" due to the leakage current between the drain and source of the transistor M7, the gate voltage becomes 0 "V" and the gate-source Voltage is -V
Since the voltage is 3 V and reverse-biased, the threshold voltage increases, and the sub-threshold current of the transistor M4 becomes, for example, I2.

Here, when the transistor M7 is not connected, the voltage between the gate and the source of the transistor M4 becomes 0 "V", and the sub-threshold current in the case of 0 "V" is set to, for example, I1. Compared with I2, I2 <I1. This shows that when the transistor M7 is connected, the amount of current flowing when the transistor M4 is off is reduced.

On the other hand, as shown between times t1 and t2 in FIG. 6, when control signal CNT is "H", control signal C
NT1 is similarly set to “H”. As a result, the transmission gate M1 is turned on and the transistor M2 is turned off, so that the clock CLK is transmitted to the node S. Further, since the transistor M7 is on, the clock CLK is inverted by the transistors M4 and M5,
This is output as signal CLKA.

That is, when the control signal CNT is "H", the transmission gate M1 is on, and the clock CL passing through the transmission gate M1 is turned on.
Only when K passes through one gate of the transistor M4 or M5, the inverted signal CLKA can be output, and the inverted signal CLKA can be output at a high speed.

The "L" level of the control signal CNT1 may be set to a negative voltage by the circuit shown in FIG. That is,
When the control signal CNT2 input to the switch 8 is, for example, "L", the switch 8 selects the negative voltage VB output from the negative potential generating circuit 7, and sets this to the "L" control signal CNT1. When CNT2 is “H”, the switch 8 may select the power supply voltage Vcc and use this as the “H” control signal CNT1.

If the "L" of the control signal CNT1 is set to a negative voltage as described above, the threshold voltage of the transistor M4 can be further increased as compared with the case of 0 "V". Leak current can be further reduced.

A DRAM (Dynamic Ran)
A semiconductor integrated circuit in which a dom access memory and a logic circuit coexist can be realized without an additional circuit by using a substrate voltage generating circuit of a DRAM as a method of generating a negative voltage.

Further, the generation of the negative voltage is not limited to the substrate voltage generation circuit of the DRAM, but may be inputted from outside.

As described above, according to the third embodiment, the inverter 1 for inverting and outputting the clock CLK is output.
0, the control signal CN for controlling the transmission of the clock CLK is supplied to the source terminal of the transistor M4 serving as the driver constituting the driver.
Since the drain terminal of the transistor M7 having T and another control signal CNT1 as a gate input is connected, the transistor M7 is turned off without using a special circuit, and thus flows when the transistor M4 is off. The sub-threshold current can be reduced, and the effect of reducing power consumption can be obtained.

Since "L" of the control signal CNT1 is set to a negative voltage, the transistor M is further increased than in the case of 0 "V".
4 can be increased, whereby the effect of further reducing the off-state leakage current of the transistor M4 can be obtained.

Further, the clock CLK which has passed through the transmission gate M1 which is turned on when the control signal CNT is at "H" only passes through one gate of the transistor M4 or M5, and the signal CL which is an inverted signal thereof.
Since the configuration is such that the KA can be output, an effect that the signal CLKA obtained by inverting the clock CLK can be output at a high speed can be obtained.

Further, the control signal CNT1 input to the gate terminal of the transistor M7 is separated from the control signal CNT for controlling the transmission of the clock CLK.
By using NT1, the circuit operation can be stopped quickly, and unnecessary operation can be avoided, and power consumption can be reduced accordingly.

[0050]

As described above, according to the present invention, the input signal passing through the transmission gate is inverted and output, and the transmission is connected between the other end of the inverter, one end of which is connected to the power supply, and the ground. First on / off in response to a first control signal for controlling on / off of the gate
Since the transistor is connected, the first transistor is turned off by the first control signal, so that the subthreshold current flowing when the transistor forming the inverter is turned off can be reduced, thereby reducing power consumption. There is an effect that can be.

According to the present invention, since the second transistor which is turned on / off in accordance with the input signal passing through the transmission gate is connected between the inverter and the ground, the second transistor is turned on by the gate passing input signal. Is turned off, it is possible to reduce a subthreshold current flowing when a transistor included in the inverter is turned off, thereby reducing power consumption.

According to the present invention, the third transistor which is turned off by the second control signal when the input signal is cut off by the transmission gate is connected between the inverter and the ground. By turning off the third transistor by the second control signal, a subthreshold current flowing when a transistor included in the inverter is turned off can be reduced, and thus there is an effect that power consumption can be reduced.

According to the present invention, the first control signal sets the level for turning off the transmission gate, the input signal passing through the transmission gate sets the level for turning off the second transistor, and the second control signal sets the level for turning off the third transistor. Is turned off at 0 V, and a leakage current flows when the first transistor is off, so that the drain voltage of the first transistor is 0 V.
As a result, a reverse bias can be applied between the gate and source of the transistor of the inverter, and the subthreshold current can be reduced.
Even when the other second and third transistors are off, there is an effect that the sub-threshold current can be reduced by applying a reverse bias.

According to the present invention, since the level of the second control signal for turning off the third transistor is configured as a negative voltage, a reverse bias can be applied by further increasing the threshold voltage as compared with the case of 0V. Thus, there is an effect that the subthreshold current can be further reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a low-consumption logic circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a low-consumption logic circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a low power consumption logic circuit according to a third embodiment of the present invention;

FIG. 4 is a diagram illustrating a configuration of a circuit that generates a level of a control signal for controlling on / off of a third transistor illustrated in FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of a conventional low-consumption logic circuit.

FIG. 6 is a time chart for explaining the operation of the low-consumption logic circuit according to the conventional example and the first to third embodiments of the present invention.

[Explanation of symbols]

10 inverter, M1 transmission gate,
M3 transistor (first transistor), M6 transistor (second transistor), M7 transistor (third transistor), CLK clock (input signal), CNT control signal (first control signal), CNT1
Control signal (second control signal).

Claims (5)

[Claims] An input signal is passed / responsive to a first control signal.
A transmission gate to cut off, one end connected to a power supply, an inverter for inverting and outputting an input signal passed through the transmission gate, one end connected to the other end of the inverter, and the other end connected to ground, A first transistor which is turned on / off in response to the first control signal. 2. Passing an input signal according to a first control signal
A transmission gate to cut off, one end connected to a power supply, an inverter for inverting and outputting an input signal passed through the transmission gate, one end connected to the other end of the inverter, and the other end connected to ground, A second transistor which is turned on / off in response to an input signal passed through the transmission gate. 3. Passing an input signal according to a first control signal
A transmission gate to cut off, one end connected to a power supply, an inverter for inverting and outputting an input signal passed through the transmission gate, one end connected to the other end of the inverter, and the other end connected to ground, And a third transistor that is turned off by a second control signal when the input signal is cut off by the transmission gate. 4. A level in which a first control signal turns off a transmission gate, a level in which an input signal passing through the transmission gate turns off a second transistor, and a second control signal turns off a third transistor. 4. The low consumption logic circuit according to claim 1, wherein the level is 0V. 5. The level of a second control signal for turning off the third transistor is a negative voltage.
Low consumption logic circuit as described.