JPH11112037A - Thermionic element and method for forming electrode of the same - Google Patents

Thermionic element and method for forming electrode of the same

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Publication number
JPH11112037A
JPH11112037A JP9265519A JP26551997A JPH11112037A JP H11112037 A JPH11112037 A JP H11112037A JP 9265519 A JP9265519 A JP 9265519A JP 26551997 A JP26551997 A JP 26551997A JP H11112037 A JPH11112037 A JP H11112037A
Authority
JP
Japan
Prior art keywords
semiconductor
electrode
fesi
type
thermoelectric element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9265519A
Other languages
Japanese (ja)
Inventor
Kiyoshi Noshiro
清 野城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosokawa Micron Corp
Original Assignee
Hosokawa Micron Corp
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Filing date
Publication date
Application filed by Hosokawa Micron Corp filed Critical Hosokawa Micron Corp
Priority to JP9265519A priority Critical patent/JPH11112037A/en
Publication of JPH11112037A publication Critical patent/JPH11112037A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce the effective ratio resistance of a thermoelectric element and to improve ability as the thermionic element by forming the electrodes of low contact resistance on FeSi2 semiconductors. SOLUTION: In the thermionic element where one end 1a and 2a-side in the P-type FeSi2 semiconductor 1 and the N-type FeSi2 semiconductor 2 are directly connected or through a conductor, the electrodes 3 which contain the doping materials of Fe, Ni, Co or Mn and Co and which is constituted of Fe are directly formed on the other end 1b and 2b-side of the P-type FeSi2 semiconductor 1 and the N-type FeSi2 semiconductor 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、FeSi2 半導体
からなる熱電素子に関し、更に詳しくは、熱電素子の低
抵抗化を図るための電極形成技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermoelectric element made of a FeSi 2 semiconductor, and more particularly, to an electrode forming technique for lowering the resistance of a thermoelectric element.

【0002】[0002]

【従来の技術】近年、熱エネルギの有効利用や熱源の多
様化等に伴い、高効率熱電材料に対する期待が高まって
おり、種々の材料が研究開発されている。なかでもFe
Si2半導体は、比較的高温度での使用が可能であり、
耐酸化性にも優れているため大気中での使用が可能であ
り、添加する不純物元素を適宜選択することで半導体と
してのP型或いはN型の導電型制御が可能であり、且
つ、原料となる鉄やシリコンが豊富で原料費が安価であ
るという多くの利点から注目されている。しかし、かか
るFeSi2 半導体も、他の熱電材料に比べて後述する
熱電素子の性能が低く、熱電素子として実用に供するに
は、この性能の改善が望まれていた。一般的に、熱電素
子の性能は、性能指数z(z=α2 /ρκ)を指標とし
て評価される。ここで、αは熱電能、ρは比抵抗、κは
熱伝導率で、性能指数zは温度に依存する物質固有の値
である。かかる観点から、熱電能αは大きく、比抵抗ρ
と熱伝導率κの小さい物質が望ましい。
2. Description of the Related Art In recent years, with the effective use of heat energy and diversification of heat sources, expectations for high-efficiency thermoelectric materials have been increasing, and various materials have been researched and developed. Above all, Fe
Si 2 semiconductors can be used at relatively high temperatures,
Since it has excellent oxidation resistance, it can be used in the air. By appropriately selecting an impurity element to be added, it is possible to control the P-type or N-type conductivity type as a semiconductor, and It is attracting attention because of its many advantages that it is rich in iron and silicon and its raw material cost is low. However, such a FeSi 2 semiconductor also has a lower performance of a thermoelectric element described later than other thermoelectric materials, and improvement of this performance has been desired for practical use as a thermoelectric element. Generally, the performance of a thermoelectric element is evaluated using a figure of merit z (z = α 2 / ρκ) as an index. Here, α is the thermoelectric power, ρ is the specific resistance, κ is the thermal conductivity, and the figure of merit z is a value specific to a substance that depends on temperature. From this viewpoint, the thermoelectric power α is large and the specific resistance ρ
And a substance having a small thermal conductivity κ is desirable.

【0003】ここで、FeSi2 半導体とは、β−Fe
Si2 相を主たる成分とする鉄珪化物であり、かかる組
成を持つ合金は、化学量論組成の非常に狭い単相領域を
持つβ−FeSi2 相が安定な相として存在し、所定温
度の熱処理によって半導体特性を有するβ相を得たもの
である。また、β−FeSi2 の溶製材は多孔質で亀裂
が多く脆いため、その作製には一般には粉末冶金法が用
いられ、その粉末冶金法における焼結法としては、代表
的なものとして、無加圧焼結法(PLS)、ホットプレ
ス焼結法(HP)、熱間等方圧力焼結法(HIP)等が
使用されている。
Here, the FeSi 2 semiconductor is β-Fe
An iron silicide having a Si 2 phase as a main component.In an alloy having such a composition, a β-FeSi 2 phase having a very narrow single-phase region of a stoichiometric composition exists as a stable phase, and at a predetermined temperature. A β phase having semiconductor characteristics was obtained by heat treatment. In addition, since the ingot of β-FeSi 2 is porous and has many cracks and is brittle, powder metallurgy is generally used for its production, and a typical sintering method in the powder metallurgy is as follows. Pressure sintering (PLS), hot press sintering (HP), hot isostatic sintering (HIP) and the like are used.

【0004】このβ−FeSi2 は、MnやAl等のP
型不純物をドーピングするとP型の導電型を呈するP型
FeSi2 半導体に、一方、Co等のN型不純物をドー
ピングするとN型の導電型を呈するN型FeSi2 半導
体にすることができる。
[0004] This β-FeSi 2 is composed of P such as Mn or Al.
Doping with a type impurity can provide a P-type FeSi 2 semiconductor having a P-type conductivity, while doping with an N-type impurity such as Co can provide an N-type FeSi 2 semiconductor having an N-type conductivity.

【0005】ところで、FeSi2 半導体を用いて熱電
素子を具体的に構成する場合、P型不純物をドーピング
したP型FeSi2 半導体とN型不純物をドーピングし
たN型FeSi2 半導体の一端同士を接合し、P型及び
N型FeSi2 半導体の他端側に電極部を形成する構成
が一般的である。ここで、各半導体の両端に温度差を与
えて両電極間に熱起電力を発生させる熱電発電素子とし
て使用する場合は、前記P型及びN型半導体の接合部を
高温側に配置する。前記P型及びN型半導体の接合部
は、FeSi2 半導体の融点が高いため銀ロウ等の高温
ロウ材を使用したり、種々の方法で直接接合させるほ
か、同種の方法で導電体を介して接合され形成されてい
た。一方、低温側に形成される電極部は、特別な導電性
の電極材料で特別に電極を形成するのではなく、前記各
半導体表面の電極部に銅線等の電気配線を超音波ハンダ
付け等で接続することで、一般的には外部回路との電気
的接続を形成していた。
Meanwhile, by using FeSi 2 semiconductor if specifically configure the thermoelectric element, joining the N-type FeSi 2 semiconductor one ends doped with P-type FeSi 2 semiconductor and N-type impurity doped with P-type impurities , P-type and N-type FeSi 2 semiconductors are generally provided with an electrode portion on the other end side. Here, when the semiconductor is used as a thermoelectric generator for generating a thermoelectromotive force between both electrodes by giving a temperature difference to both ends of the semiconductor, the junction between the P-type and N-type semiconductors is arranged on the high temperature side. The junction of the P-type and N-type semiconductors uses a high-temperature brazing material such as silver brazing because the melting point of the FeSi 2 semiconductor is high, or is directly joined by various methods, and via a conductor in the same manner. It was joined and formed. On the other hand, the electrode portion formed on the low-temperature side does not form a special electrode with a special conductive electrode material. In general, an electrical connection with an external circuit has been formed by the connection.

【0006】[0006]

【発明が解決しようとする課題】熱電素子の性能は、上
記のように性能指数zを指標として評価されるが、熱電
材料自体の性能指数zが高くても、前記P型及びN型半
導体の接合部及び前記電極部での接触抵抗が高ければ、
熱電素子全体としての実効的な比抵抗ρが見かけ上大き
くなり、実質的な性能を低下させる結果となる。つま
り、熱電発電素子として機能させた場合、前記各接触抵
抗が熱電発電素子の内部抵抗として作用し、前記各接触
抵抗において出力電流に応じた電圧降下が発生するた
め、前記P型及びN型半導体が前記接合部と前記各電極
部間の温度差で発生する熱起電力の電圧値が実効的に低
下する結果となるのである。さて、上記のFeSi2
導体を用いた熱電素子の電極部形成に使用される超音波
ハンダ付け等では、半田等の合金または金属とFeSi
2 半導体との接触面にエネルギ障壁(ショットキー障
壁)が生じ、その両端にかかるエネルギ障壁を超える電
圧が印加されなければ電気的な導通が得られず、良好な
オーミック接触とはならずに実質的に接触抵抗を増大さ
せる結果となり、特に低温時に顕著であるため、熱電素
子性能向上の一阻害要因となっていた。
The performance of the thermoelectric element is evaluated using the performance index z as an index as described above. Even if the performance index z of the thermoelectric material itself is high, the performance of the P-type and N-type semiconductors can be improved. If the contact resistance at the joint and the electrode is high,
The effective specific resistance ρ of the thermoelectric element as a whole becomes apparently large, resulting in a substantial decrease in performance. That is, when functioning as a thermoelectric generator, each of the contact resistances acts as an internal resistance of the thermoelectric generator, and a voltage drop occurs in each of the contact resistances according to an output current. As a result, the voltage value of the thermoelectromotive force generated due to the temperature difference between the bonding portion and each of the electrode portions is effectively reduced. In the above-described ultrasonic soldering or the like used for forming the electrode portion of the thermoelectric element using the FeSi 2 semiconductor, an alloy or metal such as solder and FeSi are used.
(2 ) An energy barrier (Schottky barrier) is generated at the contact surface with the semiconductor, and unless a voltage exceeding the energy barrier applied to both ends is applied, electrical conduction cannot be obtained, and good ohmic contact is not achieved without substantial ohmic contact. As a result, the contact resistance is remarkably increased, and particularly at a low temperature, which is one of the hindrance factors for improving the performance of the thermoelectric element.

【0007】ところで、一般に金属と半導体を接触させ
たとき、界面でのキャリヤの再結合速度が非常に速い場
合とか、上記ショットキー障壁が十分低い場合とか、ま
たは、キャリヤがトンネルできるほど障壁が十分に薄い
場合にオーミック接触となることから、高温時ほど良好
なオーミック接触が得られ、前記接合部及び前記電極部
での接触抵抗は低くなる。よって、低温側に設けられる
前記電極部の接触抵抗の低抵抗化が、熱電材料自体の高
性能化と合わせて、熱電素子としての高性能化に寄与す
るのである。
In general, when a metal and a semiconductor are brought into contact with each other, the carrier recombination speed at the interface is very fast, the Schottky barrier is sufficiently low, or the barrier is sufficiently large so that the carrier can tunnel. Since the ohmic contact is obtained when the thickness is too small, a good ohmic contact can be obtained at a higher temperature, and the contact resistance at the junction and the electrode decreases. Therefore, the reduction in the contact resistance of the electrode portion provided on the low-temperature side contributes to the high performance of the thermoelectric element together with the high performance of the thermoelectric material itself.

【0008】更に、熱電発電素子として使用する場合、
高温側の前記P型及びN型半導体の接合部と低温側の電
極部との温度差を大きくすれば、それだけ大きい起電力
が得られ、発電能力が高くなるが、前記電極部の接触抵
抗を低くするために電極部の温度を上げると、却って発
生起電力が低下し、発電能力が阻害される。このため、
低温側に設けられる前記電極部は通常水冷等で冷却され
る。従って、前記電極部における接触抵抗は別手段によ
って低抵抗化を図る必要がある。
Further, when used as a thermoelectric generator,
If the temperature difference between the junction of the P-type and N-type semiconductors on the high-temperature side and the electrode on the low-temperature side is increased, a larger electromotive force is obtained and the power generation capacity is increased, but the contact resistance of the electrode is reduced. If the temperature of the electrode part is raised to lower the temperature, the generated electromotive force is rather lowered, and the power generation capacity is hindered. For this reason,
The electrode portion provided on the low temperature side is usually cooled by water cooling or the like. Therefore, it is necessary to reduce the contact resistance of the electrode section by another means.

【0009】また、前記電極部の形成を、超音波ハンダ
付け等によらずに、FeSi2 半導体とオーミック接触
可能な導電性の電極材料を前記各半導体表面に直接形成
すれば、一見上記問題の解決が図れるように思われる
が、別材料で形成された電極とFeSi2 半導体の熱膨
張率及び焼成時の収縮率の違いから、電極形成を含む工
程での大きな温度差で、電極部にクラックが発生する虞
があった。更に、かかる問題点を解消し、且つ、FeS
2 半導体と良好なオーミック接触が可能な適切な電極
材料が知られていなかった。
In addition, if the electrode portion is formed directly on the surface of each semiconductor by using a conductive electrode material capable of ohmic contact with the FeSi 2 semiconductor without using ultrasonic soldering or the like, the above problem may be apparently caused. Although it seems to be able to solve the problem, the difference in the thermal expansion coefficient and the shrinkage rate during firing between the electrode formed of a different material and the FeSi 2 semiconductor causes a large temperature difference in the process including the electrode formation. May occur. Further, such a problem is solved and FeS
No suitable electrode material capable of making good ohmic contact with the i 2 semiconductor has been known.

【0010】本発明は、上記実情に鑑みてなされたもの
で、その目的は、低接触抵抗の電極を形成することで実
効的な比抵抗ρを低くし、熱電素子としての性能の向上
を図り、FeSi2 半導体が本来有する上記利点を有効
に活用し、高温使用に適した高性能の熱電素子を提供す
る点にある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to form an electrode having a low contact resistance to lower the effective specific resistance ρ and improve the performance as a thermoelectric element. Another object of the present invention is to provide a high-performance thermoelectric element suitable for high-temperature use by effectively utilizing the advantages inherent in FeSi 2 semiconductors.

【0011】[0011]

【課題を解決するための手段】この目的を達成するため
の本発明による熱電素子の第一の特徴構成は、特許請求
の範囲の欄の請求項1に記載した通り、FeSi2 半導
体に、Fe、Ni、Co、または、Mn、Co等のドー
ピング材を含むFeを成分とする電極が直接形成されて
ある点にある。
A first feature of a thermoelectric element according to the present invention for achieving this object is that a FeSi 2 semiconductor has a FeSi 2 semiconductor as described in claim 1 of the claims. , Ni, Co, or an electrode containing Fe as a component containing a doping material such as Mn or Co is directly formed.

【0012】同第二の特徴構成は、特許請求の範囲の欄
の請求項2に記載した通り、P型FeSi2 半導体とN
型FeSi2 半導体の一端同士を直接または導電体を介
して接続してなり、前記P型FeSi2 半導体及び前記
N型FeSi2 半導体の各他端側に、Fe、Ni、C
o、または、Mn、Co等のドーピング材を含むFeを
成分とする電極が直接形成されてある点にある。ここ
で、電極が直接形成されてあるとは、FeSi2 半導体
と電極材料とが、半田や銀ロウ等のFeSi2 半導体と
前記電極材料とは別組成の媒体を介して電気的且つ物理
的に接続されているのではなく、かかる媒体を介さずに
直接接続されている状態を指す。例えば、既に作製され
たFeSi2 半導体の所定箇所に、真空蒸着、溶射、塗
布等により前記電極材料の被膜を形成し、焼成すること
で、或いは、焼結法により前記FeSi2 半導体と前記
電極を同時に一体成形することで、FeSi2 半導体に
対して電極を直接形成することができる。
[0012] The second characteristic configuration is that, as described in claim 2 of the claims, a P-type FeSi 2 semiconductor and an N-type
The other ends of the P-type FeSi 2 semiconductor and the N-type FeSi 2 semiconductor are connected to one end of the type FeSi 2 semiconductor directly or via a conductor.
The point is that an electrode containing o or Fe containing a doping material such as Mn or Co as a component is directly formed. Here, the expression that the electrode is directly formed means that the FeSi 2 semiconductor and the electrode material are electrically and physically connected via a medium having a composition different from that of the FeSi 2 semiconductor such as solder or silver brazing and the electrode material. It refers to a state in which they are not connected but are directly connected without passing through such a medium. For example, a coating of the electrode material is formed by vacuum deposition, thermal spraying, coating, or the like on a predetermined portion of an already manufactured FeSi 2 semiconductor, and the film is fired, or the FeSi 2 semiconductor and the electrode are sintered by a sintering method. At the same time, by integrally molding, an electrode can be directly formed on the FeSi 2 semiconductor.

【0013】この目的を達成するための本発明による熱
電素子の電極形成方法の第一の特徴構成は、特許請求の
範囲の欄の請求項3に記載した通り、特許請求の範囲の
欄の請求項1または2に記載の熱電素子の電極形成方法
であって、電極形成箇所に前記電極材料の粉末を配置
し、半導体形成箇所に前記FeSi2 半導体の所定の導
電型の半導体材料の粉末を配置し、前記電極形成箇所と
前記半導体形成箇所の中間に前記電極材料と前記半導体
材料の混合粉末を配置し、前記FeSi2 半導体と前記
電極とを焼結法によって同時に焼成し一体成形する点に
ある。
A first feature of the method for forming an electrode of a thermoelectric element according to the present invention for achieving this object is as described in claim 3 of the claims. Item 3. The method for forming an electrode of a thermoelectric element according to Item 1 or 2, wherein the powder of the electrode material is disposed at a position where the electrode is formed, and the powder of the semiconductor material of a predetermined conductivity type of the FeSi 2 semiconductor is disposed at a position where the semiconductor is formed. Then, a mixed powder of the electrode material and the semiconductor material is disposed between the electrode formation location and the semiconductor formation location, and the FeSi 2 semiconductor and the electrode are simultaneously fired by a sintering method to be integrally molded. .

【0014】同第二の特徴構成は、特許請求の範囲の欄
の請求項4に記載した通り、前記熱電素子の電極形成方
法の第一の特徴構成に加えて、前記混合粉末の混合比
が、前記半導体形成箇所との境界から前記電極形成箇所
との境界にかけて、段階的または連続的に、前記電極材
料の粉末の配合が増えるように変化する点にある。
According to a second feature of the present invention, in addition to the first feature of the method for forming an electrode of a thermoelectric element, a mixing ratio of the mixed powder is set as described in claim 4 of the claims. From the boundary with the semiconductor formation location to the boundary with the electrode formation location, the mixing ratio of the electrode material powder changes stepwise or continuously.

【0015】以下に作用並びに効果を説明する。本発明
による上記した熱電素子の第一または第二の特徴構成に
よれば、低温時においても、電極材料とFeSi2 半導
体とが良好なオーミック接触を形成し、接触抵抗の低減
を図ることができ、結果として、熱電素子全体の実効的
な比抵抗を低下させることができ、熱電素子の高性能化
を図ることができるのである。特に、第二の特徴構成に
よれば、P型FeSi2 半導体とN型FeSi2 半導体
の熱電効果の電気的特性の極性が反転するため熱電素子
を直列接続しても発生起電力や温度差が相殺されず、高
性能化が図れるのである。更に、同構成を直列或いは並
列に接続して増設が可能である。
The operation and effect will be described below. According to the first or second characteristic configuration of the thermoelectric element according to the present invention, even at a low temperature, the electrode material and the FeSi 2 semiconductor form a good ohmic contact, and the contact resistance can be reduced. As a result, the effective specific resistance of the entire thermoelectric element can be reduced, and the performance of the thermoelectric element can be improved. In particular, according to the second characteristic configuration, since the polarity of the electrical characteristics of the thermoelectric effect of the P-type FeSi 2 semiconductor and the N-type FeSi 2 semiconductor is inverted, even if the thermoelectric elements are connected in series, the generated electromotive force and the temperature difference are reduced. It is not canceled out and high performance can be achieved. Further, the same configuration can be connected in series or in parallel to expand the configuration.

【0016】ところで、Fe、Ni、Co、または、M
n、Co等のドーピング材を含むFeは、従来、FeS
2 半導体との接触では良好なオーミック接触が困難と
思われていた材料であるが、本発明者が実験により、良
好なオーミック接触が可能であることを新たに確認し、
かかる新知見を得るに至ったものである。例えば、電極
材料がFe、または、Mn、Co等のドーピング材を含
むFeの場合は、FeSi2 半導体と電極界面にFeS
iの薄膜層が形成され、このFeSiを介して良好なオ
ーミック接触が形成されているものと推察される。ここ
に、FeSi層が実際にFeSi2 半導体と電極界面に
形成されているとしても、かかる中間層は電極形成工程
の結果としてFeSi2 半導体材料と電極材料から直接
生成されるもので、これらの材料とは別組成の接続媒体
とは言えず、かかる中間層の存在をもって電極がFeS
2 半導体に直接形成されている状態が否定されるもの
ではない。
By the way, Fe, Ni, Co, or M
Conventionally, Fe containing a doping material such as n or Co has conventionally been FeS
Although it was considered that good ohmic contact was difficult in contact with i 2 semiconductor, the present inventor newly confirmed by experiments that good ohmic contact is possible,
Such new findings have been obtained. For example, when the electrode material is Fe or Fe containing a doping material such as Mn or Co, FeS 2 semiconductor and FeS
It is presumed that a thin film layer of i was formed and a good ohmic contact was formed via this FeSi. Here, even if the FeSi layer is actually formed at the interface between the FeSi 2 semiconductor and the electrode, such an intermediate layer is formed directly from the FeSi 2 semiconductor material and the electrode material as a result of the electrode forming step. It cannot be said that the connection medium has a different composition from that of the connection medium.
This does not deny the state of being directly formed on the i 2 semiconductor.

【0017】本発明による上記した熱電素子の電極形成
方法の第一の特徴構成によれば、電極とFeSi2 半導
体が同時に作製されるため、電極形成工程を独立して別
途設ける必要がなく、工程の簡略化が図れるとともに、
電極形成を含む焼結工程での大きな温度差に対して、前
記電極材料と前記当該半導体材料の混合粉末が焼結して
中間層を形成するに、熱膨張率及び焼成時の収縮率が平
均的には電極とFeSi2 半導体の中間の値となり、か
かる熱膨張率及び収縮率の差が電極とFeSi 2 半導体
間で急激に変化しないため、クラックの発生を防止する
ことができるのである。尚、かかる混合粉末を設けずと
も一定の歩留りでクラックを発生させずに電極を形成す
ることも、工程条件を適切に調整することで可能である
が、その適正値を予備実験等により抽出するのが比較的
困難であり、高歩留りで量産するには問題となるが、本
特徴構成によれば、安定した高歩留りが期待でき、量産
適応性が高いのである。
Electrode formation of the above-mentioned thermoelectric element according to the present invention
According to a first feature of the method, the electrode and the FeSiTwoSemiconduct
Since the body is manufactured at the same time, the electrode formation process is
There is no need to provide a way, and the process can be simplified,
Due to the large temperature difference in the sintering process including electrode formation,
The mixed powder of the electrode material and the semiconductor material is sintered.
In forming the intermediate layer, the coefficient of thermal expansion and the rate of shrinkage during firing are flat.
The electrode and FeSiTwoIt is an intermediate value between semiconductors.
The difference between the thermal expansion coefficient and the contraction rate Twosemiconductor
Crack does not occur because it does not change rapidly between
You can do it. In addition, without providing such mixed powder
Electrode without cracking at a constant yield
It is also possible to adjust the process conditions appropriately
However, it is relatively difficult to extract the appropriate value by preliminary experiments, etc.
It is difficult and it is a problem for mass production at high yield.
According to the feature configuration, stable high yield can be expected and mass production
It is highly adaptable.

【0018】同第二の特徴構成によれば、電極とFeS
2 半導体間で熱膨張率及び収縮率を段階的または連続
的に変化させることができるので、前記クラックの発生
をより確実に防止できるのである。また、クラックの発
生し易い特定の焼結法の適用を容易化し、焼結法の選択
自由度が増すのである。
According to the second characteristic configuration, the electrode and the FeS
Since the coefficient of thermal expansion and the coefficient of contraction can be changed stepwise or continuously between the i 2 semiconductors, the occurrence of the crack can be more reliably prevented. In addition, the application of a specific sintering method in which cracks easily occur is facilitated, and the degree of freedom in selecting the sintering method is increased.

【0019】[0019]

【発明の実施の形態】以下に、本発明に係る熱電素子及
びその電極形成方法の実施の形態を図面に基づいて説明
する。図1に示すように、本発明に係る熱電素子は、棒
状のP型FeSi2 半導体1と棒状のN型FeSi2
導体2が夫々の一端同士1a、2aにおいて平面視V字
形状に直接接続し、更に、前記P型FeSi2 半導体1
と前記N型FeSi2半導体2の各他端1b、2b側の
上面に、Feを成分とする電極3が直接形成された構成
となっている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a thermoelectric element and an electrode forming method according to the present invention will be described with reference to the drawings. As shown in FIG. 1, in the thermoelectric element according to the present invention, a rod-shaped P-type FeSi 2 semiconductor 1 and a rod-shaped N-type FeSi 2 semiconductor 2 are directly connected to each other at one end 1a, 2a in a V-shape in plan view. And the P-type FeSi 2 semiconductor 1
An electrode 3 containing Fe as a component is formed directly on the upper surface of each of the other ends 1b and 2b of the N-type FeSi 2 semiconductor 2.

【0020】図2に示すように、前記P型FeSi2
導体1、前記N型FeSi2 半導体2、及び、前記電極
3の各部を含む、直径40mm、厚さ7mmの円盤体4
を無加圧焼結法で同時に一体で作製した後に、マイクロ
カッターで図中破線部分に沿ってV字形状に切削加工し
て前記熱電素子が作製される。また、前記電極3の厚さ
は、全体の厚み7mm中の2mmで上面側に位置してい
る。何れも焼成後の寸法である。ここで、前記電極3の
厚みを2mmとしたのは、2mmより厚くすると、Fe
とFeSi2 を比較した場合の焼成時の収縮率がFeの
方が大きいため、前記電極3にクラックが発生し易くな
るためである。
As shown in FIG. 2, a disc 4 having a diameter of 40 mm and a thickness of 7 mm including the P-type FeSi 2 semiconductor 1, the N-type FeSi 2 semiconductor 2, and the electrodes 3.
Are simultaneously and integrally formed by a pressureless sintering method, and then cut into a V-shape along a broken line portion in the figure by a micro cutter to manufacture the thermoelectric element. The thickness of the electrode 3 is 2 mm of the total thickness of 7 mm and is located on the upper surface side. All are dimensions after firing. Here, the reason why the thickness of the electrode 3 is 2 mm is that if the thickness is larger than 2 mm,
This is because, when Fe is compared with FeSi 2 , the shrinkage ratio during firing is larger in Fe, so that cracks easily occur in the electrode 3.

【0021】以下、前記円盤体4の作製について説明す
る。前記P型FeSi2 半導体1の原料粉末は、Fe
(純度99.9%以上)、Si(純度99.9%以
上)、Mn(純度99.99%以上)を原料としてFe
(1 -X) Mnx Si2 (X=0.05〜0.13)の組成
になるように秤量して真空溶解炉で溶解したものの粗粉
末を、ボールミルでメカニカルグライディングして平均
粒径5〜8mmの微粉末としたものを使用する。一方、
前記N型FeSi2 半導体2の原料粉末は、Fe(純度
99.9%以上)、Si(純度99.9%以上)、Co
(純度99.9%以上)を原料としてFe(1-Y) CoY
Si2 (Y=0.03〜0.12)の組成になるように
秤量して真空溶解炉で溶解したものの粗粉末を、上記同
様に平均粒径5〜8mmの微粉末としたものを使用す
る。前記電極3の原料粉末は、Fe(純度99.9%以
上)の粗粉末を、上記と同様の工程を経て、平均粒径1
〜10μmの微粉末としたものを使用する。
Hereinafter, the production of the disk 4 will be described. The raw material powder of the P-type FeSi 2 semiconductor 1 is Fe powder
(Purity 99.9% or more), Si (purity 99.9% or more), Mn (purity 99.99% or more)
(1 -X) Mn x Si 2 (X = 0.05 to 0.13) The composition was weighed to have a composition of 0.5 to 0.13 and melted in a vacuum melting furnace. 〜8 mm fine powder is used. on the other hand,
The raw material powder of the N-type FeSi 2 semiconductor 2 includes Fe (purity of 99.9% or more), Si (purity of 99.9% or more), Co
(Purity 99.9% or more) as raw material and Fe (1-Y) Co Y
A coarse powder obtained by weighing so as to have a composition of Si 2 (Y = 0.03 to 0.12) and melting in a vacuum melting furnace is used as a fine powder having an average particle diameter of 5 to 8 mm in the same manner as described above. I do. The raw material powder of the electrode 3 is obtained by subjecting a coarse powder of Fe (purity of 99.9% or more) to a process similar to that described above to obtain an average particle diameter of 1: 1.
A fine powder of 10 to 10 μm is used.

【0022】前記P型FeSi2 半導体1及び前記N型
FeSi2 半導体2の原料粉末を所定円筒容器内に夫々
半円柱分づつ充填し、更に、図2に示す電極形成部分に
前記電極3の原料粉末を充填して、円盤状に予備成形し
たものを、焼結温度1050℃、昇温時間30分で、無
加圧焼結を施した。尚、焼結温度1050℃は、前記P
型FeSi2 半導体1及び前記N型FeSi2 半導体2
の原料粉末が焼結して、しかもβ相化する温度1124
°K以上に設定してある。尚、無加圧焼結法では、焼成
後の緻密度が92%〜93%であるため、耐久性を向上
させるためには、ホットプレス焼結法や熱間等方圧力焼
結法等の使用が好ましい。しかしながら、焼結法とし
て、ホットプレス焼結法や熱間等方圧力焼結法等の加圧
焼結法を用いる場合は、加圧用の黒鉛製のパンチの炭素
と前記電極3のFeが反応し、前記電極3が剥がれる虞
があるため、前記パンチを例えばアルミナ製等に変更す
る必要がある。
Raw material powders for the P-type FeSi 2 semiconductor 1 and the N-type FeSi 2 semiconductor 2 are filled into predetermined cylindrical containers by half cylinders, respectively. The powder was filled and preliminarily formed into a disk shape, and pressureless sintering was performed at a sintering temperature of 1050 ° C. and a heating time of 30 minutes. The sintering temperature of 1050 ° C.
-Type FeSi 2 semiconductor 1 and N-type FeSi 2 semiconductor 2
Temperature at which the raw material powder sinters and becomes β-phase
° K or higher. In the pressureless sintering method, since the compactness after firing is 92% to 93%, in order to improve the durability, hot press sintering method, hot isostatic pressure sintering method, or the like is used. Use is preferred. However, when a pressure sintering method such as a hot press sintering method or a hot isostatic pressure sintering method is used as the sintering method, carbon of the graphite punch for pressurization and Fe of the electrode 3 react. However, since the electrode 3 may be peeled off, it is necessary to change the punch to, for example, alumina.

【0023】上記製法で作製された熱電素子の内部抵抗
を、同形状で同じ作製方法で前記電極3を設けず超音波
ハンダ付けで電極部を設けた従来の熱電素子の内部抵抗
と比較した結果、従来6Ωであったものが、0.1Ω以
下に低減されていることが確認できた。
The result of comparing the internal resistance of the thermoelectric element manufactured by the above-described method with the internal resistance of the conventional thermoelectric element having the same shape and the same manufacturing method but not provided with the electrode 3 but provided with an electrode portion by ultrasonic soldering. It was confirmed that what was conventionally 6Ω was reduced to 0.1Ω or less.

【0024】以下に別実施形態を説明する。 〈1〉上記の実施形態における前記円盤体4の作製工程
において、図2に示す電極形成部分に前記電極3の原料
粉末を充填する前に、前記電極3の原料粉末の充填箇所
と、前記P型FeSi2 半導体1及び前記N型FeSi
2 半導体2の原料粉末の各充填箇所の間に、当該導電型
のFeSi2 半導体原料粉末と前記電極3の原料粉末の
混合粉末を充填させるのも好ましい実施の形態である。
尚、この混合粉末の混合比としては、FeSi2 半導体
原料粉末の重量%が10%〜90%のものが好ましい。
このように、前記P型FeSi2 半導体1及び前記N型
FeSi2 半導体2と前記電極3の間に、積極的に同種
の成分からなる中間層を形成することで、前記電極3の
焼成時の収縮による衝撃を吸収緩和し、クラックの発生
を抑制することができるのである。
Another embodiment will be described below. <1> In the manufacturing process of the disk body 4 in the above embodiment, before the raw material powder for the electrode 3 is filled in the electrode forming portion shown in FIG. -Type FeSi 2 semiconductor 1 and the N-type FeSi
It is also a preferred embodiment to fill a mixed powder of the conductive type FeSi 2 semiconductor raw material powder and the raw material powder for the electrode 3 between the filling locations of the two semiconductor 2 raw material powders.
The mixing ratio of the mixed powder is preferably such that the weight% of the FeSi 2 semiconductor raw material powder is 10% to 90%.
As described above, an intermediate layer made of the same kind of component is positively formed between the P-type FeSi 2 semiconductor 1 and the N-type FeSi 2 semiconductor 2 and the electrode 3, so that the The shock due to shrinkage can be absorbed and alleviated, and the occurrence of cracks can be suppressed.

【0025】更に、前記混合比を、前記混合粉末の充填
箇所の前記各FeSi2 半導体1、2側から前記電極3
側にかけて、連続的または断続的に傾斜組成化させても
構わない。この場合、前記電極3の焼成時の収縮による
衝撃を連続的または断続的に吸収緩和できるため、上記
のクラック発生抑制効果がより顕著となり、より好まし
いのである。
Further, the mixing ratio is determined from the side of each of the FeSi 2 semiconductors 1 and 2 at the filling position of the mixed powder.
The composition may be continuously or intermittently graded toward the side. In this case, since the impact due to the shrinkage of the electrode 3 during firing can be absorbed continuously and intermittently, the above-described effect of suppressing the occurrence of cracks becomes more remarkable, which is more preferable.

【0026】〈2〉前記電極3の電極材料としては、F
e以外に、Ni、Co、または、Mn、Co等のドーピ
ング材を含むFeであっても構わない。これらの電極材
料においても、Feの場合と同様に、FeSi2 半導体
2との間で良好なオーミック接触が可能であることが確
認できている。
<2> The electrode material of the electrode 3 is F
In addition to e, Ni, Co, or Fe containing a doping material such as Mn or Co may be used. Also in these electrode materials, it has been confirmed that good ohmic contact with the FeSi 2 semiconductor 2 is possible as in the case of Fe.

【0027】〈3〉本実施形態において、前記P型Fe
Si2 半導体1と前記N型FeSi2半導体2は、各別
に作製されたものを、前記電極3とは反対側の端部同士
を銀ロウ付け等の既存の接続方法で接続しても構わな
い。また、前記P型FeSi2 半導体1及び前記N型F
eSi2 半導体2の両端に前記電極3を設け、一方端の
電極同士を共通としたり、或いは、別途導電体を介して
接続しても構わない。
<3> In this embodiment, the P-type Fe
The Si 2 semiconductor 1 and the N-type FeSi 2 semiconductor 2 may be manufactured separately and their ends opposite to the electrode 3 may be connected by an existing connection method such as silver brazing. . Further, the P-type FeSi 2 semiconductor 1 and the N-type F
The electrodes 3 may be provided at both ends of the eSi 2 semiconductor 2, and the electrodes at one end may be made common or may be connected separately via a conductor.

【0028】〈4〉前記電極3は、必ずしも、前記P型
FeSi2 半導体1及び前記N型FeSi2 半導体2は
焼結法で同時に作製されなくても構わない。例えば、既
製のP型FeSi2 半導体及びN型FeSi2 半導体の
夫々の一端側に、真空蒸着、溶射、塗布等により前記電
極材料の被膜を形成し、焼成して形成しても構わない。
また、既製の前記P型FeSi2 半導体及び前記N型F
eSi2 半導体のβ相化は前記電極材料の被膜の焼成時
に同時に行っても構わない。また、既製の前記P型Fe
Si2 半導体及び前記N型FeSi2 半導体の作製方法
は無加圧焼結法以外の焼結法であってもよく、また、真
性FeSi2 半導体を作製した後に所定の導電型の不純
物をスパッタリング等して作製しても構わない。
<4> In the electrode 3, the P-type FeSi 2 semiconductor 1 and the N-type FeSi 2 semiconductor 2 do not necessarily have to be manufactured simultaneously by the sintering method. For example, a film of the electrode material may be formed by vacuum deposition, thermal spraying, coating, or the like on one end of each of the ready-made P-type FeSi 2 semiconductor and N-type FeSi 2 semiconductor, and may be formed by firing.
The P-type FeSi 2 semiconductor and the N-type F
The β-phase conversion of the eSi 2 semiconductor may be performed simultaneously with the baking of the film of the electrode material. In addition, the ready-made P-type Fe
Si 2 semiconductor and a manufacturing method of the N-type FeSi 2 semiconductor may be a sintering method other than pressureless sintering method, also, sputtering a predetermined conductivity type impurity after forming an intrinsic FeSi 2 semiconductor such It may be made by making.

【0029】[0029]

【発明の効果】以上説明したように、本発明によれば、
低接触抵抗の電極をFeSi2 半導体上に形成すること
で実効的な熱電素子の比抵抗を低くし、熱電素子として
の性能の向上を図ることができ、結果として、FeSi
2 半導体が本来的に有する高温度使用、耐酸化性、導電
型制御容易性、低原料コスト等の多くの利点を有効に活
用した、高温使用に適した高性能の熱電素子を提供する
ことができた。
As described above, according to the present invention,
By forming the electrode with low contact resistance on the FeSi 2 semiconductor, the specific resistance of the effective thermoelectric element can be reduced, and the performance as the thermoelectric element can be improved.
(2) To provide a high-performance thermoelectric element suitable for high-temperature use, making effective use of many advantages inherent in semiconductors such as high temperature use, oxidation resistance, easy control of conductivity type, low raw material cost, etc. did it.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る熱電素子の一実施形態を示す斜視
FIG. 1 is a perspective view showing one embodiment of a thermoelectric element according to the present invention.

【図2】本発明に係る熱電素子の一実施形態の製造工程
を説明する平面図
FIG. 2 is a plan view illustrating a manufacturing process of one embodiment of the thermoelectric element according to the present invention.

【符号の説明】[Explanation of symbols]

1 P型FeSi2 半導体 1a P型FeSi2 半導体の一端 1b P型FeSi2 半導体の他端 2 N型FeSi2 半導体 2a N型FeSi2 半導体の一端 2b N型FeSi2 半導体の他端 3 電極 4 円盤体1 P-type FeSi 2 semiconductor 1a P-type FeSi 2 semiconductor end 1b P-type FeSi 2 semiconductor of the other end 2 N type FeSi 2 semiconductor 2a N-type FeSi 2 semiconductor end 2b N-type FeSi 2 semiconductor of the other end 3 electrode 4 disc body

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 FeSi2 半導体に、Fe、Ni、C
o、または、Mn、Co等のドーピング材を含むFeを
成分とする電極が直接形成されてある熱電素子。
1. An FeSi 2 semiconductor comprising Fe, Ni, C
A thermoelectric element in which an electrode composed of o or Fe containing a doping material such as Mn or Co is directly formed.
【請求項2】 P型FeSi2 半導体とN型FeSi2
半導体の一端同士を直接または導電体を介して接続して
なる熱電素子であって、 前記P型FeSi2 半導体及び前記N型FeSi2 半導
体の各他端側に、Fe、Ni、Co、または、Mn、C
o等のドーピング材を含むFeを成分とする電極が直接
形成されてある熱電素子。
2. A P-type FeSi 2 semiconductor and an N-type FeSi 2.
A thermoelectric element in which one end of a semiconductor is connected directly or via a conductor, and the other end of the P-type FeSi 2 semiconductor and the N-type FeSi 2 semiconductor is Fe, Ni, Co, or Mn, C
A thermoelectric element in which an electrode containing Fe as a component containing a doping material such as o is directly formed.
【請求項3】 請求項1または2に記載の熱電素子の電
極形成方法であって、 電極形成箇所に前記電極材料の粉末を配置し、半導体形
成箇所に前記FeSi 2 半導体の所定の導電型の半導体
材料の粉末を配置し、前記電極形成箇所と前記半導体形
成箇所の中間に前記電極材料と前記半導体材料の混合粉
末を配置し、前記FeSi2 半導体と前記電極とを焼結
法によって同時に焼成し一体成形することを特徴とする
熱電素子の電極形成方法。
3. The power supply of the thermoelectric element according to claim 1 or 2.
A method of forming a pole, comprising: placing a powder of the electrode material at an electrode formation location;
The above-mentioned FeSi TwoSemiconductor of a given conductivity type of semiconductor
A material powder is placed, and the electrode forming portion and the semiconductor
A mixed powder of the electrode material and the semiconductor material in the middle of the formation location
And the FeSiTwoSintering the semiconductor and the electrode
Characterized by simultaneous firing and integral molding by the method
Method for forming electrodes of thermoelectric element.
【請求項4】 前記混合粉末の混合比が、前記半導体形
成箇所との境界から前記電極形成箇所との境界にかけ
て、段階的または連続的に、前記電極材料の粉末の配合
が増えるように変化する請求項3記載の熱電素子の電極
形成方法。
4. The mixing ratio of the powder mixture changes stepwise or continuously from the boundary with the semiconductor formation location to the boundary with the electrode formation location so as to increase the blending of the powder of the electrode material. The method for forming an electrode of a thermoelectric element according to claim 3.
JP9265519A 1997-09-30 1997-09-30 Thermionic element and method for forming electrode of the same Pending JPH11112037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9265519A JPH11112037A (en) 1997-09-30 1997-09-30 Thermionic element and method for forming electrode of the same

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010093009A (en) * 2008-10-07 2010-04-22 Sumitomo Chemical Co Ltd Thermoelectric transduction module and thermoelectric transducer
JP2017204501A (en) * 2016-05-09 2017-11-16 日本ドライケミカル株式会社 Thermoelectric conversion element, distributed temperature sensor and manufacturing method of thermoelectric conversion element
JP2021073685A (en) * 2020-12-25 2021-05-13 日本ドライケミカル株式会社 Thermoelectric transducer, distribution type temperature sensor, and manufacturing method of thermoelectric transducer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010093009A (en) * 2008-10-07 2010-04-22 Sumitomo Chemical Co Ltd Thermoelectric transduction module and thermoelectric transducer
JP2017204501A (en) * 2016-05-09 2017-11-16 日本ドライケミカル株式会社 Thermoelectric conversion element, distributed temperature sensor and manufacturing method of thermoelectric conversion element
JP2021073685A (en) * 2020-12-25 2021-05-13 日本ドライケミカル株式会社 Thermoelectric transducer, distribution type temperature sensor, and manufacturing method of thermoelectric transducer

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