JPH11111937A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of contriving high integration while preventing latch ups. SOLUTION: Two sets of cells adjoining each other in the direction of wells 3 and 11 are arranged, so that the disposition of n well and p well are mutually each other, and also isolation layers 12 and 13 are arranged to separate the whole two p wells 11 and 11 en block from the substrate 1, forming them astride the two cells where the p wells 1 separated from a substrate 1 are adjoined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a dynamic random access memory (DRA).
The present invention relates to a preferable improvement when a memory device such as M) and a logic circuit are formed on the same substrate to form a semiconductor device.

[0002]

2. Description of the Related Art FIG. 7 is a front view showing a cell structure of a conventional semiconductor device. In FIG. 7, reference numeral 1 denotes a P-type doped substrate, and 2 denotes a drain formed on one side of the substrate 1. Reference numeral 3 denotes an N well formed in the substrate 1 adjacent to the drain N + diffusion region 2;
Is a source P + diffusion region formed in the N well 3, and 5 is a source N + formed in the N well 3 between the source P + diffusion region 4 and the drain N + diffusion region 2.
It is a diffusion area. Reference numeral 6 denotes a high-voltage power supply line which is laminated on the substrate 1 via an insulating layer or the like and is connected to the P + diffusion region 4 for source and the N + diffusion region 5 for source. A low-voltage side power supply line is stacked via layers and connected to the N + diffusion region 2 for the drain, and 8 is a signal line for output connected to the P + diffusion region 4 for the source and the N + diffusion region 2 for the drain. 9 is laminated on the source P + diffusion region 4 between the high-voltage side power supply line 6 and the output signal line 8, and is connected to the drain between the low-voltage side power supply line 7 and the output signal line 8. This is an input signal line stacked on the N + diffusion region 2. Note that the substrate 1 is supplied with a VBB potential lower than the GND potential.

FIG. 8 is a front view showing a layout of a semiconductor device having a plurality of the cells. In the figure, reference numeral 10 denotes each of the above cells, and reference numeral 16 denotes a signal line for transmitting and receiving a signal to and from each cell. Further, as can be seen from the fact that the N-wells 3 are arranged on the same side, the cells are arranged in the same direction in consideration of design efficiency by an auto router or the like.

Next, the operation will be described. The high-voltage power line 6 is connected to the Vcc potential, and the low-voltage power line 7 is connected to GND. For example, when a Vcc level signal is input from the input signal line 9, the drain N + diffusion region 2 is controlled to the cutoff operation state, while the source P + diffusion region 4 is controlled to the linear operation state. You. As a result, a signal of Vcc level is output from output signal line 8.

Conversely, when a GND level signal is input from the input signal line 9, the source P + diffusion region 4 is controlled to the cutoff operation state, while the drain N + diffusion region 2 is set to the linear operation state. Is controlled. As a result, a signal at the GND level is output from the output signal line 8. Therefore, the cell of the example shown in the above figure operates as an inverter.

[0006]

Since the conventional semiconductor device is configured as described above, there is a problem that a thyristor structure is formed in each cell, and as a result, latch-up occurs. . Hereinafter, the problem will be described in detail.

FIG. 9A is a sectional view showing a section taken along line EE 'of the cell of the semiconductor device shown in FIG.
r1 is a first transistor formed between the N well 3 and the substrate 1 using the source P + diffusion region 4 as an emitter, R1 is a first resistor formed by the N well 3,
Tr2 is a second transistor formed between the substrate 1 and the N well 3 using the N + diffusion region 2 for drain as an emitter, and R2 is a second resistor formed on the substrate 1.
FIG. 9B is a diagram illustrating a circuit structure of the transistor illustrated in FIG.

Next, the operation will be described. For example, if a current flows through the first resistor R1 for some reason, the first resistor R1
1 turns on the first transistor Tr1. When the first transistor Tr1 is turned on, a voltage is generated in the second resistor R2 by the current flowing between the emitter and the collector of the first transistor Tr1. As a result, the voltage generated in the second resistor R2 causes the second transistor Tr2
And the current flowing through the first resistor R1 increases. Therefore, the first transistor Tr
When the product of the amplification factor of 1 and the amplification factor of the second transistor Tr2 is 1 or more, if such an operation is started once, the current flowing through each of the transistors Tr1 and Tr2 continues to be amplified, and in an extreme case, The substrate is destroyed. The above operation is a latch-up operation.

Note that, in the semiconductor device shown in FIG. 9, in order to suppress such a latch-up operation, the source P
A source N + diffusion region 5 is provided in an N well 3 between the + diffusion region 4 and the drain N + diffusion region 2. Thereby, the resistance value of the first resistor R1 by the N well 3 can be reduced, so that the first transistor Tr1 is hardly turned on.

However, even with such a configuration, when the base potential of the second transistor Tr2 fluctuates and turns on when the second resistor R2 is generated by the substrate 1, for example, it is still necessary. This causes a problem of latch-up. In particular, when a memory circuit such as a dynamic random access memory (DRAM) and a logic circuit are formed on the same substrate to form a semiconductor device, the logic circuit is not connected to the substrate 1.
The substrate potential VBB fluctuates due to the current flowing into
There is a problem that the latch-up occurs frequently.

In the semiconductor device shown in FIG. 9, to suppress the ON operation of the second transistor Tr2,
Since it is extremely difficult to reduce the second resistor R2, the distance (A) between the N well 3 and the N + diffusion region 2 for drain is increased to increase the VBE voltage when the second transistor Tr2 is turned on. However, in such a configuration, the width W1 of the cell increases, which makes it difficult to form a semiconductor device with a high degree of integration.

Therefore, Japanese Patent Application Laid-Open Nos. 61-147564, 3-239359 and 8-460 are disclosed.
It is conceivable to take measures against latch-up by using techniques disclosed in Japanese Patent Application Laid-Open No. 54-54, Japanese Patent Application Laid-Open No. 6-97374, and the like. FIG. 10 is a cross-sectional view showing a structure of a semiconductor device when such a conventional latch-up countermeasure is taken.
In the figure, reference numeral 13 denotes an N-type buried diffusion layer provided below the drain N + diffusion region 2, and 12 denotes a drain N + diffusion region 2 between the upper surface of the substrate 1 and the N-type buried diffusion layer 13. Reference numeral 11 denotes an N-type diffusion region for isolation provided so as to surround it, and 11 denotes a P-well separated from the substrate 1 by the N + diffusion region 2 for drain and the N-type diffusion region 12 for isolation. Other configurations are the same as those of the conventional semiconductor device shown in FIG. In the following, the N-type buried diffusion layer 13 and the isolation N-type diffusion region 12 are also collectively called an isolation layer.

When the semiconductor device is configured in this manner, as shown in the figure, the connection between the collector terminal of the second transistor Tr2 and the base terminal of the first transistor Tr1 is cut off, and the base of the second transistor Tr2 is disconnected. Since the connection between the terminal and the collector terminal of the first transistor Tr1 is disconnected, a thyristor structure as shown in FIG. 9B is not formed in each cell. As a result, the latch-up problem is fundamentally solved.

However, when each cell of the semiconductor device is configured as described above, it is necessary to provide the isolation layers 12 and 13 for each cell, which causes the width W2 of each cell to be large, and high integration is required. You can't do what you want.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of achieving high integration while preventing latch-up.

[0016]

In a semiconductor device according to the present invention, when a pair of one N well and one P well arranged adjacent to each other is a set of cells, the semiconductor device is arranged in the well arrangement direction. Two sets of adjacent cells are arranged so that the arrangement of the N-well and the P-well are opposite to each other, and the isolation layer is connected to the two cells adjacent to the well separated from the substrate. The two wells are formed so as to be separated from the substrate.

In the semiconductor device according to the present invention, the substrate is doped to be P-type and set at a potential equal to or lower than the ground potential.

In the semiconductor device according to the present invention, the substrate is doped with N-type, and is set to a potential equal to or higher than the high-side potential of the power supply voltage.

In a semiconductor device according to the present invention, the potential of the substrate is set to a potential equal to or lower than the ground potential, and the semiconductor device includes a plurality of memory cells and a plurality of logic cells. The cell is arranged so that the arrangement of the N well and the P well is opposite to that of another cell adjacent in the arrangement direction of the wells, and the isolation layer is formed of a well separated from the substrate. The two wells are formed so as to span the two adjacent cells, and are disposed so as to separate the entire two wells from the substrate.

In a semiconductor device according to the present invention, the potential of the substrate is set to a potential equal to or higher than the high potential of the power supply voltage, and the semiconductor device includes a plurality of memory cells and a plurality of logic cells. The logic cell is disposed so that the arrangement of the N well and the P well is opposite to other cells adjacent in the arrangement direction of the well, and the isolation layer is separated from the substrate. A well to be formed is formed so as to extend between two adjacent cells, and is disposed so as to separate the entire two wells from the substrate.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a front view (a) and a sectional view (b) showing a layout of a semiconductor device according to a first embodiment of the present invention. In the semiconductor device, a DRAM and a logic circuit are provided on the same substrate, and FIG. 1 shows a cell for the logic circuit. In the figure, 10
Numerals are cells arranged in a matrix on one side surface of the semiconductor device, and 16 is a signal line arranged between the cells on the above-mentioned side surface for transmitting and receiving signals to and from each cell. Also,
Numeral 3 denotes an N well formed in each cell 10, and 11 denotes a P well formed in each cell 10 adjacent to the N well 3. As is clear from these, each cell 10 has a vertical Are arranged in different directions for each row.

FIG. 2 is a front view showing one cell 10 and its related parts. FIG. 3A shows cell 1
FIG. 3 is a sectional view taken along the line AA ′ of FIG. In these figures, 1 is a P-doped substrate, 11 is a P well formed in one side of the substrate 1, and 3 is formed in the substrate 1 adjacent to the P well 11. Reference numeral 9 denotes an N well, an input signal line for inputting a signal to the cell 10 from a position adjacent to the N well 3, and an output signal from the cell 10 from a position adjacent to the P well 11. An output signal line 4 is a source P + diffusion region (P-type diffusion region) formed at a position near the P well 11 in the N well 3, and 5 is a source P
A source N + diffusion region formed in N well 3 between + diffusion region 4 and input signal line 9, and a drain N + formed in P well 11 at a position near N well 3. A diffusion region (N-type diffusion region) 14 is a P well 1 between the drain N + diffusion region 2 and the output signal line 8.
1 is a drain P + diffusion region formed in
Is an N-type buried diffusion layer disposed below two N + diffusion regions 2 for drain over two adjacent cells 10, and 12 is an upper surface of the substrate 1 and an N-type buried diffusion layer 13
And an isolation N-type diffusion region 15 arranged so as to surround each drain N + diffusion region 2. Reference numeral 6 denotes a P-type diffusion region for separation, and a reference numeral 6 denotes a main power supply line 6 arranged perpendicularly to the signal line 16 in FIG.
a, and a cell supply line 6b disposed so as to pass over the N + diffusion region 5 for the source.
A high-voltage side power supply line connected to the diffusion region 4 and the source N + diffusion region 5 is indicated by a signal line 16 in FIG.
And a main power supply line 7a vertically arranged, and a cell supply line 7b arranged to pass through the P + diffusion region 14 for the drain, and the N + diffusion region 2 for the drain.
And a low-voltage side power supply line connected to the drain P + diffusion region 14. The main power supply line 6a is connected to the N-type diffusion region 12 for isolation, and the N-type diffusion region 1 for isolation.
A high voltage is supplied to an isolation layer composed of the N-type buried diffusion layer 13 and the N-type buried diffusion layer 13.

With such a configuration, FIG.
A transistor structure is formed as shown in FIG. In the figure, the Vcc potential (> GND potential) is applied to the high-voltage power supply line 6, the GND potential is applied to the low-voltage power supply line 7, the VBB potential (<GND potential) is applied to the P-type substrate 1, and
It is assumed that the Vcc potential is supplied to the buried diffusion layer 13. In the figure, Tr1 is a first transistor formed between the N well 3 and the P-type substrate 1 using the source P + diffusion region 4 as an emitter, and R1 is a first resistor formed by the N well 3. , Tr2 are second transistors formed between the P-type substrate 1 and the N well 3 using the drain N + diffusion region 2 as an emitter.
Is a second resistor formed on the P-type substrate 1, and R3 is N
This is a third resistor formed by the mold embedded diffusion layer 13.

FIG. 3B is a diagram showing a transistor structure including the transistor shown in FIG. 3A, and thus each cell 10 of the semiconductor device according to the first embodiment is shown.
Then, the connection between the collector terminal of the second transistor Tr2 and the base terminal of the first transistor Tr1 is cut off, and the connection between the base terminal of the second transistor Tr2 and the collector terminal of the first transistor Tr1 is cut off. No thyristor structure is formed. Therefore, the problem of latch-up has been fundamentally solved.

Next, the operation will be described. First, for example, when a Vcc level signal is input from the input signal line 9, the drain N + diffusion region 2 is controlled to the cutoff operation state, while the source P + diffusion region 4 is controlled to the linear operation state. You. As a result, V is output from the output signal line 8.
A cc level signal is output.

Conversely, when a GND level signal is input from the input signal line 9, the source P + diffusion region 4 is controlled to the cutoff operation state, while the drain N + diffusion region 2 is set to the linear operation state. Is controlled. As a result, a signal at the GND level is output from the output signal line 8.

Therefore, the cell of the example shown in the above figure operates as an inverter. Various logic circuits can be realized by combining a plurality of the cells 10.

As described above, according to the first embodiment, two sets of cells 10 adjacent to each other in the arrangement direction of P well 11 and N well 3 are connected to each other by the arrangement of N well 3 and P well 11. While being arranged in the opposite direction,
The isolation layers 12 and 13 are formed so as to extend between two cells 10 and 10 where the P well 11 separated from the substrate 1 is adjacent, and the entire two P wells 11 and 11 are collectively formed from the substrate 1. N
The connection between the first transistor Tr1 formed in the well 3 and the second transistor Tr2 formed in the P well 11 can be cut off, and no thyristor structure is formed.

Therefore, although the DRAM and the logic circuit are arranged on the same substrate 1 and the power supply for the substrate 1 is generated in a semiconductor device having a small current capacity, the logic circuit and the like are not used. An effect is obtained that a latch-up can be prevented without a large amount of current flowing into one.

In other words, in a semiconductor device in which a DRAM and a logic circuit are mixedly mounted, the logic cell is configured as described above even if the potential of the substrate 1 is set to a potential equal to or lower than the ground potential. It can be said that no latch-up problem occurs.

In this configuration, the two cells 10, 1
Since one isolation layer 12, 13 is formed for each 0, increase in cell width W3 due to the isolation layers 12, 13 can be suppressed, and high integration can be achieved while preventing latch-up. Can be.

Embodiment 2 FIG. FIG. 4 is a front view (a) showing a layout of a semiconductor device according to a second embodiment of the present invention.
And a sectional view (b), wherein the semiconductor device is a DRA.
M and a logic circuit are arranged on the same substrate, and FIG. 1 shows a cell for the logic circuit. In the figure, reference numeral 10 denotes cells arranged in a matrix on one side surface of the semiconductor device, and reference numeral 16 denotes a signal line disposed on the side surface between the cells and for transmitting and receiving signals to and from each cell. . 3 is an N well formed in each cell 10, and 11 is a P well formed in each cell 10 adjacent to the N well 3. As is clear from these, each cell 10 is Are arranged in different directions for each vertical arrangement.

FIG. 5 is a front view showing the one cell 10 and its related parts. FIG. 6A shows cell 1
FIG. 6 is a cross-sectional view taken along the line CC ′ of FIG. In these figures, 1 'is an N-type doped substrate, 11 is a P-well formed in one side of the N-type substrate 1', and 3 is an N-type substrate adjacent to the P-well 11. N well formed in 1 ', 9 is P well 11
, An input signal line for inputting a signal to the cell 10 from a position adjacent to the N well 3, an output signal line 8 for outputting an output signal from the cell 10 from a position adjacent to the N well 3, and 4 an N signal line. A source P + diffusion region formed at a position near the P well 11 in the well 3 and 5 is a source P +
A source N + diffusion region formed in the N well 3 between the diffusion region 4 and the output signal line 8, and 2 is a P well 1
1. N for drain formed near N well 3 in 1
A diffusion region 14; a drain P + diffusion region formed in the P well 11 between the drain N + diffusion region 2 and the input signal line 9; and 18 extending over two adjacent cells 10. P-type buried diffusion layers are disposed below the two N-wells 3, respectively. Reference numeral 17 denotes each N-well 3 between the upper surface of the N-type substrate 1 ′ and the P-type buried diffusion layer 18.
Is a P-type diffusion region for isolation provided so as to surround
Reference numeral 1 denotes an N-type diffusion region for separation for separating the P-wells 11 and the P-well 11 from the P-type diffusion region 17 for separation.
6 has a main power supply line 6a disposed perpendicular to the signal line 16 in FIG. 4, and a cell supply line 6b disposed so as to pass over the source N + diffusion region 5, and has a source P + diffusion region. 4 and a high-voltage-side power supply line connected to the source N + diffusion region 5. Reference numeral 7 denotes a main power supply line 7a arranged perpendicular to the signal line 16 in FIG.
And a cell supply line 7b arranged so as to pass through the P + diffusion region 14 for drain.
This is a low voltage side power supply line connected to the diffusion region 2 and the drain P + diffusion region 14. The main power supply line 7a is connected to the isolation P-type diffusion region 17, and supplies a high voltage to an isolation layer composed of the isolation P-type diffusion region 17 and the P-type buried diffusion layer 18. .

With such a configuration, FIG.
A transistor structure is formed as shown in FIG. In the figure, the Vcc potential (> GND potential) is applied to the high-voltage power supply line 6, the GND potential is applied to the low-voltage power supply line 7, the Vcc potential (> GND potential) is applied to the N-type substrate 1 ', and P It is assumed that the GND potential is supplied to the mold buried diffusion layer 18. In the figure, Tr1 is a first transistor formed between the N well 3 and the P-type isolation layers 17 and 18 using the source P + diffusion region 4 as an emitter, and R1 is constituted by the N well 3. Tr2 is a second transistor formed between the N-type substrate 1 and the P well 11 using the N + diffusion region 2 for drain as an emitter, and R2 is a second transistor formed by the P well 11. R3 is a third resistor formed on the N-type substrate 1.

FIG. 6B is a diagram showing a transistor structure including the transistor shown in FIG. 6A. Thus, in each cell 10 of the semiconductor device according to the second embodiment, the second transistor Tr2 The connection between the collector terminal and the base terminal of the first transistor Tr1 is cut off, and the connection between the base terminal of the second transistor Tr2 and the collector terminal of the first transistor Tr1 is cut off, so that no thyristor structure is formed. Therefore, the problem of latch-up has been fundamentally solved.

Next, the operation will be described. First, for example, when a Vcc level signal is input from the input signal line 9, the drain N + diffusion region 2 is controlled to the cutoff operation state, while the source P + diffusion region 4 is controlled to the linear operation state. You. As a result, a signal at the Vcc level is output from the output signal line 8.

Conversely, when a GND level signal is input from the input signal line 9, the source P + diffusion region 4 is controlled to the cutoff operation state, while the drain N + diffusion region 2 is set to the linear operation state. Is controlled. As a result, a signal at the GND level is output from the output signal line 8.

Therefore, the cell of the example shown in the above figure operates as an inverter. Various logic circuits can be realized by combining a plurality of the cells 10.

As described above, according to the second embodiment, two sets of cells 10 adjacent to each other in the arrangement direction of P well 11 and N well 3 are connected to each other by the arrangement of N well 3 and P well 11. While being arranged in the opposite direction,
The isolation layers 17 and 18 are separated from the N-type substrate 1 'by two cells 10 and 10 adjacent to each other with an N well 3 adjacent thereto.
And the two P-wells 11 and 11 are disposed so as to be separated from the N-type substrate 1 ′ at a time, so that the first transistor Tr formed in the N-well 3 is formed.
1 and a second transistor Tr2 formed in the P well 11
Can be disconnected, and a thyristor structure is not formed.

Therefore, although the DRAM and the logic circuit are arranged on the same substrate 1 and the power supply for the N-type substrate 1 'is generated in the semiconductor device having a small current capacity, the N-type substrate 1' There is no need to flow a large amount of current from 1 'to the logic circuit or the like, and the effect of preventing latch-up can be obtained.

In other words, in a semiconductor device in which a DRAM and a logic circuit are mixedly mounted, the logic cell is configured as described above even if the potential of the N-type substrate 1 'is set to a high voltage potential or higher. Therefore, it can be said that there is no problem of latch-up.

In this configuration, the two cells 10, 1
Since one isolation layer 17, 18 is formed for each 0, an increase in the cell width W3 due to the isolation layers 17, 18 can be suppressed, and high integration can be achieved while preventing latch-up. Can be.

[0043]

As described above, according to the present invention, when a pair of one N well and one P well disposed adjacent to each other is a set of cells, adjacent cells are arranged in the arrangement direction of the wells. Are arranged so that the arrangement of the N-well and the P-well is opposite to each other, and the isolation layer is connected to the two cells adjacent to the well separated from the substrate. And the two wells are disposed so as to be separated from the substrate. Therefore, the connection between the transistor formed in the N well and the transistor formed in the P well can be cut off, and the thyristor structure can be formed. Is not formed. Therefore, there is an effect that latch-up can be prevented.

Further, in this configuration, since one isolation layer is formed for every two cells, an increase in the cell width due to the isolation layer can be suppressed, and the latch-up can be prevented. There is an effect that integration can be achieved.

The configuration of such a semiconductor device is as follows.
For example, as in the case where the DRAM and the logic circuit are provided on the same substrate, the P-type substrate is set to a potential lower than the ground potential, or the N-type substrate is set to a higher potential than the power supply voltage. It is particularly suitable in some cases. This is because, in the case where the substrate potential is set to a potential other than the high-side potential of the power supply voltage or the ground potential, the potential is generally generated by a semiconductor device. In the power supply device on the device, there is a problem that potential fluctuation is likely to occur due to a large amount of current flowing from the above logic circuit and the like. By configuring the cell as in the present invention, it is possible to suppress a large amount of current flowing into the substrate. Because it is possible. That is, by employing the present invention, the DRAM and the logic circuit can be easily provided on the same substrate.

From a different point of view, such a semiconductor device has a structure in which the substrate potential is set to a potential equal to or lower than the ground potential, and a plurality of memory cells and a plurality of logic cells are used. In a semiconductor device having a plurality of memory cells and a plurality of logic cells, wherein the potential of the substrate is set to a potential equal to or higher than the high-side potential of the power supply voltage, It can be said that it is preferable to form the cell with the above cell structure.

[Brief description of the drawings]

FIGS. 1A and 1B are a front view and a sectional view showing a layout of a semiconductor device according to a first embodiment of the present invention; FIGS.

FIG. 2 is a front view showing one cell of the semiconductor device according to the first embodiment of the present invention and its related parts.

FIGS. 3A and 3B are a cross-sectional view illustrating one cell of the semiconductor device according to the first embodiment of the present invention and a view illustrating a transistor structure, respectively; FIGS.

FIGS. 4A and 4B are a front view and a sectional view showing a layout of a semiconductor device according to a second embodiment of the present invention; FIGS.

FIG. 5 is a front view showing one cell of a semiconductor device according to a second embodiment of the present invention and a related portion thereof.

6A is a sectional view showing one cell of a semiconductor device according to a second embodiment of the present invention, and FIG. 6B is a view showing a transistor structure;

FIG. 7 is a front view showing one cell of a conventional semiconductor device and its related parts.

FIG. 8 is a front view showing a layout of a conventional semiconductor device.

9A is a cross-sectional view illustrating one cell of a conventional semiconductor device, and FIG. 9B is a view illustrating a transistor structure.

FIG. 10 is a cross-sectional view showing one cell of another conventional semiconductor device.

[Explanation of symbols]

1 P-type substrate (substrate), 1 'N-type substrate (substrate), 2
N + diffusion region for drain (N-type diffusion region), 3 N well, P + diffusion region for source (P-type diffusion region), 11
P well, 12 N-type diffusion region for isolation (isolation layer), 13 N-type buried diffusion layer (isolation layer), 17 P-type diffusion region for isolation (isolation layer), 18 P-type buried diffusion layer (isolation layer) ).

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Hatanaka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Toru Kitaguchi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Ryo Denki Co., Ltd. (72) Inventor Kiyoyuki Shiroshima 3-1-1, Chuo, Itami-shi, Hyogo Mitsubishi Electric Corporation Semiconductor Software Co., Ltd. In Isahaya Electronics Co., Ltd. (72) Inventor Masaaki Matsuo 1830-25, Kaizu-cho, Isahaya-shi, Nagasaki Prefecture Isahaya Electronics Co., Ltd.

Claims (5)

[Claims] 1. A P-type or N-type doped substrate, an N-well and a P-well formed on the substrate,
A P-type diffusion region formed in the N-well, an N-type diffusion region formed in the P-well, and a substrate around the well of the same type as the substrate so as to separate the substrate and the well. In a semiconductor device having an isolation layer provided, when one set of one N well and one P well arranged adjacent to each other is a set of cells, two sets of cells adjacent to each other in the arrangement direction of the wells are provided. Are arranged such that the arrangement of the N-well and the P-well are opposite to each other, and the isolation layer is connected to two cells adjacent to the well separated from the substrate. A semiconductor device, wherein the two wells are formed so as to be separated from the substrate. 2. The semiconductor device according to claim 1, wherein the substrate is P-doped and set at a potential equal to or lower than a ground potential. 3. The semiconductor device according to claim 1, wherein the substrate is N-doped and is set to a potential equal to or higher than the high-side potential of the power supply voltage. 4. A semiconductor device having a potential of a substrate set to a potential equal to or lower than a ground potential and having a plurality of memory cells and a plurality of logic cells, wherein the logic cells are P-type or An N-type doped substrate, an N-well and a P-well formed in the substrate, a P-type diffusion region formed in the N-well,
An N-type diffusion region formed in the P-well, and an isolation layer disposed around the well of the same type as the substrate so as to separate the substrate from the well;
The other cells adjacent in the arrangement direction of the wells are N
The arrangement of the wells and the P-wells is disposed so that they are opposite to each other, and the isolation layer is formed so as to span two cells adjacent to the well separated from the substrate. A semiconductor device, wherein one whole well is provided so as to be separated from a substrate. 5. The semiconductor device according to claim 1, wherein the potential of the substrate is set to a potential equal to or higher than a high-potential of the power supply voltage, and the semiconductor device has a plurality of memory cells and a plurality of logic cells. A P-type or N-type doped substrate, an N-well and a P-well formed in the substrate, a P-type diffusion region formed in the N-well, and an N-type diffusion formed in the P-well. A region and an isolation layer disposed around a well of the same type as the substrate so as to separate the substrate and the well, and another cell adjacent in the arrangement direction of the well is N The arrangement of the wells and the P-wells is disposed so that they are opposite to each other, and the isolation layer is formed so as to span two cells adjacent to the well separated from the substrate. Horn Wherein a that is disposed so as to separate the whole E Le from the substrate.