KR20090038062A - Electrostacticdischarge protection structure - Google Patents

Electrostacticdischarge protection structure Download PDF

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Publication number
KR20090038062A
KR20090038062A KR1020070103340A KR20070103340A KR20090038062A KR 20090038062 A KR20090038062 A KR 20090038062A KR 1020070103340 A KR1020070103340 A KR 1020070103340A KR 20070103340 A KR20070103340 A KR 20070103340A KR 20090038062 A KR20090038062 A KR 20090038062A
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KR
South Korea
Prior art keywords
well
type impurity
electrostatic discharge
discharge protection
impurity region
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Application number
KR1020070103340A
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Korean (ko)
Inventor
김종수
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070103340A priority Critical patent/KR20090038062A/en
Publication of KR20090038062A publication Critical patent/KR20090038062A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Disclosed is an electrostatic discharge preventing structure that can reduce the occupied area. The disclosed electrostatic discharge protection structure includes a semiconductor substrate, an n well formed in the semiconductor substrate, a p well formed in the n well, a pnpn junction formed in the n well, an npnp junction formed in the p well, and A pad disposed to overlap the n well region and electrically connected to at least one of the npnp junction and the pnpn junction.

Description

Electrostatic Discharge Protection Structure {ElectroStacticDischarge Protection Structure}

The present invention relates to a semiconductor device, and more particularly, to an electrostatic discharge protection structure for protecting internal elements of a semiconductor integrated circuit from static electricity input to an external pad.

The semiconductor device receives an external signal through an input / output pad and a power pin. At this time, the static electricity may flow into the input / output pad and the power pin together with the external signal, and the static electricity may flow into the internal circuit of the semiconductor device through the pad or the pin to discharge. Such static discharge causes damage to the internal circuit of the semiconductor device, such as the junction region and dielectric of the MOS transistor.

Currently, in order to discharge static electricity flowing from the outside into the low resistance path without entering the internal circuit, an electrostatic discharge protection structure is connected between the input / output pad (power pin) and the internal circuit.

The electrostatic discharge protection structure is typically a silicon controlled rectifier (SCR). The silicon rectifier controlled rectifier consists of a parasitic pnpn bipolar transistor, which instantaneously discharges the current generated by electrostatic discharge to a ground supply line or a supply voltage line.

As shown in FIG. 1, the static discharge protection structure 10 having the SCR structure is connected between the input / output pad 20 and the internal circuit 30.

The electrostatic discharge protection structure 10 is composed of a first electrostatic discharge circuit portion 10a and a second electrostatic discharge circuit portion 10b for discharging high pressure static electricity and low pressure static electricity, respectively. The first electrostatic discharge circuit unit 10a includes the first and second bipolar transistors T1 connected in an SCR form between the conductive line L connecting the input / output pad 20 and the internal circuit 30 and the ground line Vss. T2). At this time, R1 represents a parasitic resistance of the first electrostatic discharge circuit portion 10a.

The second electrostatic discharge circuit portion 10b includes third and fourth bipolar transistors T3 and T4 connected in an SCR form between the conductive line L and the power supply voltage line Vdd, and the second electrostatic discharge circuit portion 10b ) R2 also represents the parasitic resistance of the second electrostatic discharge circuit portion 10b.

2 is a cross-sectional view illustrating a state in which the electrostatic discharge protection structure 10 of FIG. 1 is integrated in the semiconductor substrate 50.

Referring to FIG. 2, the n well 52 is formed in a region where the electrostatic discharge protection structure 10 of the semiconductor substrate 50 is to be formed. A device isolation layer 54 is formed in a predetermined portion of the n well 52 to define a p well predetermined region in which npn type second and third bipolar transistors T2 and T3 are to be formed. First to third p wells 56a, 56b, and 56c are formed in a predetermined portion of the n well 52 region defined by the device isolation layer 54. P-type impurity regions 58a and 58b and n-type impurity regions 59a and 59b are formed in the first and third p wells 56a and 56c, respectively, and p-type impurity regions ( Only 58c) is formed. Here, the p-type impurity regions 58a, 58b and 58c formed in the first to third p wells 56a, 56b and 56c are bodies for providing conductivity to the first to third p wells 56a and 56c. Body contacts. In addition, in order to provide conductivity to the n well 52, an n-type impurity region 59c is formed in the n well 52. Here, the p-type and n-type impurity regions 58a, 58b, 59a, and 59c of the first and third p wells 56a and 56c are electrically connected to ground voltage lines, and the p of the second p well 56b is electrically connected. The type impurity region 58c is electrically connected to the pad. In addition, the n-type impurity region 59c formed in the n well 52 is electrically connected to the power supply voltage line.

Such an electrostatic discharge protection structure requires a pair of SCR elements to effectively discharge high pressure static electricity and low pressure static electricity.

However, as one SCR element is composed of a pair of bipolar transistors, and a pair of SCR elements, that is, four bipolar transistors are required to constitute one electrostatic discharge protection element, the area occupied by the electrostatic discharge protection element is considerable. . Therefore, in the case of highly integrated semiconductor devices, the area of such an electrostatic discharge protection device must also be taken into account.

In addition, in order to form a pair of SCR devices, a plurality of p wells must be formed in an area defined by n wells. To this end, device separation membranes for separation between wells are required. However, since the device isolation layer has to occupy a certain area to perform its function, it is a limiting factor in reducing the area of the electrostatic discharge protection device itself.

It is therefore an object of the present invention to provide an electrostatic discharge protection structure that can reduce the footprint.

In order to achieve the above object of the present invention, an electrostatic discharge protection structure according to an embodiment of the present invention, a semiconductor substrate, n well formed on the semiconductor substrate, p well formed in the n well, within the n well A pnpn junction formed, an npnp junction formed in the p well, and a pad disposed to overlap the n well region and electrically connected to at least one of the npnp junction and the pnpn junction.

In addition, the electrostatic discharge protection structure according to another embodiment of the present invention, the semiconductor substrate, the n well formed in the semiconductor substrate, the p well formed in the n well, the first spaced apart at a predetermined interval in the n well To third p-type impurity regions, first to third n-type impurity regions spaced apart from each other at predetermined intervals in the p well, a fourth n-type impurity region formed in the n well and supplied with a power supply voltage, a fourth p-type impurity region formed in the p-well and receiving a ground voltage, and a pad formed to overlap the n-well while being in electrical contact with the third p-type impurity region.

By placing the electrostatic discharge protection circuit under the pad, the area of the electrostatic discharge protection circuit can be reduced. In addition, when the electrostatic discharge protection circuit is integrated, the pnpn junction may be formed in the well without the device isolation layer, thereby reducing the area of the electrostatic discharge protection circuit itself.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 3, an electrostatic discharge protection structure 110 is positioned between the pad 120 and the semiconductor substrate. That is, in the present exemplary embodiment, the electrostatic discharge protection structure 110 may be overlapped with the pad 120, thereby reducing the area occupied by the electrostatic discharge protection structure 110 in the semiconductor device.

The electrostatic discharge protection structure 110 may include a first electrostatic discharge circuit unit 110a driven when low voltage static electricity is input and a second electrostatic discharge circuit unit 110b driven when high voltage static electricity is input.

The first electrostatic discharge circuit unit 110a is composed of first and second bipolar transistors T11 and T12. The first bipolar transistor T11 may be a pnp transistor, for example, and the second bipolar transistor T12 may be an npn transistor. The first and second bipolar transformers T1 and T2 may be connected in an SCR form. That is, the base of the first bipolar transistor T11 is connected with the collector of the second bipolar transistor T12, and its collector is connected with the base of the second bipolar transistor T12, and its emitter is connected to the pad 120. Is electrically connected to the In addition, the emitter of the second bipolar transistor T12 is connected to the ground voltage line.

The second electrostatic discharge circuit unit 110b is composed of third and fourth bipolar transistors T13 and T14. The third bipolar transistor T13 may be an npn transistor, for example, and the fourth bipolar transistor T14 may be a pnp transistor. The third and fourth bipolar transformers T13 and T14 may be connected in an SCR form similarly to the first and second bipolar transistors T11 and T12. That is, the base of the third bipolar transistor T13 is connected with the collector of the fourth bipolar transistor T14, and its collector is electrically connected with the base of the fourth bipolar transistor T14, and its emitter is padded. Is electrically connected to 120. In addition, the emitter of the fourth bipolar transistor T14 is connected to a power supply voltage line.

Here, R11 and R12 are parasitic resistances formed in each electrostatic discharge circuit portion, that is, well resistances.

When a low voltage static electricity flows into the pad 120, the base potential of the first bipolar transistor T11 is lowered to drive the first bipolar transistor T11. Accordingly, the collector potential of the first bipolar transistor T11 is raised. As a result, the second bipolar transistor T12 is driven to discharge the low voltage static electricity to the ground voltage line through the second bipolar transistor T12.

On the other hand, when a high voltage static electricity flows into the pad 120, the base potential of the third bipolar transistor T13 is increased to drive the third bipolar transistor T13. As a result, the collector potential of the third bipolar transistor T13 is lowered. As a result, the fourth bipolar transistor T14 is driven to discharge the high voltage static electricity to the power supply voltage line through the fourth bipolar transistor T14.

The electrostatic discharge protection circuit having such a configuration is integrated on the semiconductor substrate as shown in FIGS. 4 and 5 on the semiconductor substrate. 4 is a plan view of the electrostatic discharge protection circuit of the present embodiment, and FIG. 5 is a cross-sectional view taken along the line VV ′ of FIG. 4. At this time, in FIG. 4, the arrangement of the metal wires is omitted for convenience of description.

First, as shown in FIGS. 4 and 5, a semiconductor substrate 200 is prepared. The n well 205 is formed in a predetermined region of the electrostatic discharge protection circuit of the semiconductor substrate 200. The p well 210 is formed to occupy a portion of the n well 205. In this case, no device isolation layer is provided between the n well 205 and the p well 210.

In order to form a bipolar transistor for forming an SCR, first to third p-type impurity regions 215a, 215b and 215c are formed in the n well 205 and the first to third n in the p well 210. Type impurity regions 218a, 218b, and 218c are formed. In addition, in order to impart conductivity to the n well 205 and the p well 210, a fourth n-type impurity region 218d is formed in the n well 205 and a fourth p-type impurity in the p well 210. Region 215d is formed.

In the electrostatic discharge protection circuit configured as described above, a pnpn type and an npnp type junction are respectively formed in the n well 205 and the p well 210 to form a bipolar transistor of an SCR type.

For example, a first bipolar transistor T11 is formed between the third p-type impurity region 215c, the n well 205, and the p well 210, and the first n-type impurity region 218a and the p well The second bipolar transistor T12 may be formed between the 210 and the second n-type impurity regions 218b.

In addition, a third bipolar transistor T13 is formed between the n well 205, the p well 210, and the first n-type impurity region 218a, and the second p-type impurity region 215b and the n well ( A fourth bipolar transistor T14 may be formed between the 205 and the third p-type impurity region 215c.

The fourth p-type impurity region 215d is electrically connected to the ground voltage line Vss, and the fourth n-type impurity region 218d is electrically connected to the power supply voltage line Vdd. Here, the electrical connection between the impurity region and the voltage line can be achieved through metal wiring.

The pad 250 is disposed to be in electrical contact with the third p-type impurity region 215c. The pad 250 is disposed over the n well 205 where the electrostatic discharge protection circuit is formed. Here, reference numeral 240 denotes an interlayer insulating film for electrically insulating the semiconductor substrate from the pad 250.

According to the present embodiment, an n well and a p well may be divided to form an electrostatic discharge protection circuit, and a pnpn junction (npnp junction) may be formed in the n well and p well, thereby forming an SCR structure without an element isolation layer. As a result, since the area of the electrostatic discharge protection circuit is substantially reduced by the area of the device isolation layer, the area of the entire electrostatic discharge protection circuit can be reduced.

In addition, as the electrostatic discharge protection circuit of the present embodiment is disposed between the substrate and the pad, the semiconductor device can secure as much as the area of the electrostatic discharge protection circuit, thereby improving the layout efficiency of the semiconductor device.

In addition, as described above, the electrostatic discharge protection circuit of this embodiment can distinguish n well and p well, and form a pnpn junction (npnp junction) in the n well and p well, thereby forming an SCR structure without an element isolation film. . As a result, the area of the electrostatic discharge protection circuit itself can be reduced by the area of the device isolation film. Therefore, as shown in FIG. 6, even if the electrostatic discharge protection circuit is not implemented under the pad, since the area of the electrostatic discharge protection circuit itself is reduced, the area of the peripheral area of the semiconductor device can be further reduced.

Although the present invention has been described in detail with reference to the above-described preferred embodiment, the present invention is not limited to the above embodiment, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.

1 is a circuit diagram schematically showing a typical electrostatic discharge protection structure,

2 is a cross-sectional view of a general electrostatic discharge protection structure,

3 is a circuit diagram showing an electrostatic discharge protection structure according to an embodiment of the present invention;

4 is a plan view of an electrostatic discharge protection structure according to an embodiment of the present invention;

FIG. 5 is a cross-sectional view of the electrostatic discharge protection structure taken along the line VV ′ of FIG. 4.

Claims (7)

Semiconductor substrates; An n well formed on the semiconductor substrate; A p well formed in said n well; A pnpn junction formed in said n well; An npnp junction formed in the p well; And And a pad disposed to overlap the n well region and electrically connected to at least one of the npnp junction and the pnpn junction. The method of claim 1, The npnp junction, Electrostatic discharge protection structure consisting of the first to third p-type impurity regions spaced apart at regular intervals in the n well. The method of claim 1, The pnpn junction, Electrostatic discharge protection structure consisting of the first to third n-type impurity regions spaced apart at regular intervals in the p well. The method of claim 1, And the n well further includes an n-type impurity region provided with a power supply voltage. The method of claim 1, And the p well further includes a p-type impurity region provided with a ground voltage. Semiconductor substrates; An n well formed on the semiconductor substrate; A p well formed in said n well; First to third p-type impurity regions spaced apart from each other at predetermined intervals in the n well; First to third n-type impurity regions spaced apart from each other at predetermined intervals in the p well; A fourth n-type impurity region formed in the n well and receiving a power supply voltage; A fourth p-type impurity region formed in the p well and supplied with a ground voltage; And And a pad formed in electrical contact with the third p-type impurity region and overlapping the n well. Semiconductor substrates; An n well formed on the semiconductor substrate; A p well formed in said n well; First to third p-type impurity regions spaced apart from each other at predetermined intervals in the n well; First to third n-type impurity regions spaced apart from each other at predetermined intervals in the p well; A fourth n-type impurity region formed in the n well and receiving a power supply voltage; A fourth p-type impurity region formed in the p well and supplied with a ground voltage; And And a pad in electrical contact with the third p-type impurity region.
KR1020070103340A 2007-10-15 2007-10-15 Electrostacticdischarge protection structure KR20090038062A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010126314A2 (en) 2009-04-30 2010-11-04 한양대학교 산학협력단 Silicon solar cell comprising a carbon nanotube layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010126314A2 (en) 2009-04-30 2010-11-04 한양대학교 산학협력단 Silicon solar cell comprising a carbon nanotube layer

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