JPH09298277A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress generation of a latch-up phenomenon, even when it has a substrate potential generation circuit. SOLUTION: Provided on a P type substrate 10 are a substrate potential generation circuit 80 for applying a potential, a CMOS internal circuit 12, an output circuit 82 and a latch-up preventing element 84. The preventing element 84 and output circuit 82 are connected in parallel to a power voltage line to which a power voltage Vcc is applied and also to a grounding voltage line to which a grounding voltage Vss is applied. The preventing element 84 has an N type first diffusion region 96 in the P type substrate 10, the first diffusion region 96 has an N type second diffusion region (n<+> ) 98 and a P type third diffusion region (p<+> ) 100, an N type fourth diffusion region 102 is provided around the first diffusion region 96 so as to substantially surround the first diffusion region 96 as viewed from a planar pattern.

Description

Detailed Description of the Invention

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a latch-up prevention protection element.

[0002]

2. Description of the Related Art In a semiconductor device having a COMS internal circuit and an output circuit for outputting a signal from the inside of the COMS, when a surge current flows from the output line into the COMS internal circuit through the output circuit, the surge current is generated. May trigger to cause latch-up. Therefore,
In order to suppress the occurrence of latch-up, as a latch-up prevention circuit, an impurity diffusion region (hereinafter, also referred to as a peripheral diffusion region) is formed around the output circuit so as to surround the output circuit. By forming this latch-up prevention circuit, as will be described in Comparative Example 1 to be described later, among the surge currents flowing from the output line, the
The ratio of the current flowing through the internal circuit can be reduced. As a result, the occurrence of latch-up can be suppressed.

[0003]

By the way, in a semiconductor device, a substrate voltage is generally applied to a substrate in order to ensure optimum operation of an internal circuit. In order to obtain this substrate potential, a substrate potential generation circuit is usually provided for each semiconductor device. Then, the potential generated by the substrate potential generation circuit is applied to the substrate via the peripheral diffusion region of the latch-up prevention circuit.

However, the substrate potential generating circuit generally has a small current supply amount and a large internal impedance as a power source. Therefore, when the surge current flows into the substrate potential generation circuit through the peripheral diffusion region, the potential applied to the substrate from the substrate potential generation circuit easily changes. As a result of the change in the substrate potential due to this surge, latch-up occurs in the internal circuit. Therefore, if the semiconductor device having the substrate potential generation circuit is provided with the conventional latch-up prevention / protection circuit, it is difficult to reduce the occurrence of latch-up.

Therefore, it has been desired to realize a semiconductor device capable of reducing the occurrence of latch-up even if it has a substrate potential generating circuit.

[0006]

According to the semiconductor device of the invention of this application, a substrate potential generating circuit for applying a potential to the first conductivity type substrate, an internal circuit, and a signal from this internal circuit. Is a semiconductor device including an output circuit for outputting a signal to an output line, and a latch-up prevention protection element for preventing latch-up of the internal circuit. The first power supply line and the second power supply line that are connected in parallel with the output circuit, and are provided in the first diffusion region of the second conductivity type provided on the substrate, and provided in the first diffusion region. Further, a second conductivity type second diffusion region having an impurity concentration higher than that of the first diffusion region, and a first conductivity type provided in the first diffusion region and separated from the second diffusion region. The third diffusion region of the mold and this first expansion region A fourth diffusion region of the second conductivity type provided on the substrate around the region so as to be separated from the first diffusion region and substantially surround the first diffusion region when viewed in a plan pattern. The third diffusion region is connected to the output line, the second diffusion region is connected to the first power supply line, the fourth diffusion region is connected to the second power supply line, and the substrate potential is The internal potential generation line to which the potential generated in the generation circuit is applied is connected to the substrate outside the latch-up prevention protection element.

According to the present invention, the latch-up prevention protection element provided in parallel with the output circuit is provided, and the surge is first transmitted through the SCR (Semiconductor Controlled Rectifier) formed of the parasitic bipolar transistor formed in the latch-up protection element. Alternatively, it can be supplied to the second power supply line. As a result, the surge flowing from the output circuit to the internal circuit can be reduced and the occurrence of latch-up can be suppressed.

Further, it is preferable that the gate electrode of the MOS transistor is provided on the portion of the first diffusion region between the second diffusion region and the third diffusion region. Second
If the diffusion region and the third diffusion region are separated by the gate electrode,
The distance between both diffusion regions can be made shorter than in the case where they are separated by a field oxide film. As a result, the area occupied by the latch-up prevention protection element can be reduced.

Further, preferably, the second circuit is provided around the output circuit so as to substantially surround the output circuit when viewed in a plane pattern, and is connected to the second power supply line through a pure resistance.
It is desirable to have a conductivity type fifth diffusion region. If a part of the surge flowing from the output circuit to the internal circuit is extracted from the fifth diffusion region, the surge flowing to the internal circuit can be further reduced. As a result, the occurrence of latch-up can be further suppressed.

Preferably, the output circuit has an electrical resistance higher than that of the latch-up prevention protection element as viewed from the external connection bonding pad connected to the output line, and the output circuit is made of an insulating film. It is desirable to be connected to the output line via a pure resistance element separated from the substrate. If the output circuit is on the high resistance side, it is possible to reduce the ratio of the surge that flows into the output circuit from the output terminal to the output circuit and the latch-up prevention protection device. Therefore, the surge flowing from the output circuit to the internal circuit can be reduced. As a result, the occurrence of latch-up can be further suppressed.

Further, preferably, the output circuit is constituted by a CMOS transistor including a first conductivity type MOS transistor and a second conductivity type MOS transistor, and the first conductivity type MOS transistor and the second conductivity type. Of the MOS transistors, it is desirable to connect the MOS transistor that is the injection source of the surge that triggers the occurrence of latch-up to the pure resistance element. If both the first and second conductivity type MOS transistors forming the output circuit are connected to the pure resistance element, the drive capability of the output circuit is reduced, but if the pure resistance element is connected to only one of the MOS transistors, It is possible to prevent the latch-up while suppressing the deterioration of the drive capability.

Preferably, the latch-up prevention protection element is provided around the output circuit so as to surround the output circuit when viewed in a plan pattern. If the output circuit is surrounded by the latch-up prevention protection element, the latch-up prevention protection element also has a function of drawing out a surge from the output circuit, like the fifth diffusion region described above. as a result,
Surge from the output circuit to the internal circuit can be effectively extracted from the latch-up prevention protection element. Therefore, the surge flowing from the output circuit to the internal circuit can be reduced. As a result, the occurrence of latch-up can be further suppressed.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. It should be noted that the drawings to be referred to merely schematically show the sizes, shapes, and positional relationships of the respective constituent components to the extent that the present invention can be understood. Therefore, the present invention is not limited to the illustrated example.

Prior to the description of the embodiments of the present invention, in order to facilitate understanding of the present invention, Comparative Example 1 and Comparative Example 2
Will be described briefly.

Comparative Example 1 First, with reference to FIG. 13, an example of a semiconductor device having a conventional latch-up prevention circuit in the case of not having a substrate potential generating circuit will be described as Comparative Example 1. FIG. 13 is a schematic sectional view for explaining the semiconductor device of Comparative Example 1. In FIG. 13, the wiring and the parasitic circuit are shown together with the diffusion region of the semiconductor device.

(Regarding Configuration) In Comparative Example 1, a CMOS (Complementary Metal Oxide Semico) is provided on the P-type substrate 10.
An internal circuit 12 and a CMOS output circuit 14 are provided. The P-type substrate 10 is usually provided with a plurality of CMOS internal circuits other than the illustrated CMOS internal circuit 12.

A P-type MOS transistor (also referred to as a PMOSTr) 16 forming a COMS internal circuit (hereinafter, also simply referred to as an internal circuit) 12 is a P-type substrate 10.
N well (also referred to as Nwell) 18 formed in
Is formed. A power supply voltage V _{CC of} 3.0 V is applied to the source (p +) 20 of the PMOSTr 16 and the N well 18. The power supply voltage V _CC is applied to the N-well 18 through an N-type high-concentration impurity diffusion region (n +) 24 having an impurity concentration higher than that of the N-well 18.

Further, N which constitutes the CMOS internal circuit 12
Type MOS transistor (also referred to as NMOSTr) 2
6 is formed on the P-type substrate 10. And NMO
The drain (n +) 32 of the STr 26 and the P-type substrate 10
Is applied with a ground voltage V _{SS of} 0V. The ground voltage V _SS is applied via a P-type high-concentration impurity diffusion region (p +) 34 whose impurity concentration is higher than that of the P-type substrate 10.

Further, a P-type MOS transistor (PMOSTr) 36 constituting the COMS output circuit (hereinafter, simply referred to as an output circuit) 14 is formed in an N well 38 formed in the P-type substrate 10. And N well 38
And the source (p +) 40 of the PMOSTr 36,
A power supply voltage V _{CC of} 3.0 V is applied. The power supply voltage V _CC is applied to the N well 38 through the high-concentration impurity diffusion region (n +) 114 whose impurity concentration is higher than that of the N well 38.

Further, N constituting the COMS output circuit 14
The type MOS transistor (NMOSTr) 46 is formed on the P-type substrate 10. The ground voltage V _{SS of} 0V is applied to the drain (n +) 52 of the NMOSTr 46. In addition, the PMOST that constitutes the output circuit 14
The drain (p +) 42 of r36 and the NMOSTr46
Source (n +) 50 of the output terminal 54 through the output line
It is connected to the.

In Comparative Example 1, the P-type high-concentration impurity diffusion region (p +) 58 to which the ground voltage V _{SS of} 0V is applied is used as the latch-up prevention / protection circuit. And in Comparative Example 1, it is provided so as to surround the PMOSTr 36), and
The N-type impurity diffusion region 60 to which the power supply voltage V _{CC of} 3.0 V is applied is provided so as to surround the PMOSTr 36 forming the output circuit. The power supply voltage V _CC is
It is applied to the impurity diffusion region 60 through the N-type high-concentration impurity diffusion region (n +) 62 formed in the impurity diffusion region 60 of the type.

(Regarding Parasitic Circuit) Next, a parasitic circuit of the semiconductor circuit of Comparative Example 1 will be described. In the semiconductor device of Comparative Example 1, by combining the P-type substrate, the P-type impurity diffusion region, and the N well and the N-type impurity diffusion region, which form the semiconductor device, a parasitic circuit different from the original element is formed. It

For example, the PMOSTr16 of the internal circuit 12
Source (p +) 20, N well 18, and P-type substrate 1
0 corresponds to the emitter, the base and the collector, respectively, and corresponds to a pnp type first parasitic transistor (first parasitic T
r) 64. The base 64 of the first parasitic Tr is connected to the power supply voltage via an N-type high-concentration impurity diffusion region (n +) 24 in the N well 18 of the internal circuit 12. Further, between the base and the n + 24, the well resistance R ₁ 66 occurs parasitically.

The drain (n +) 32 of the NMOSTr 26 of the internal circuit 12, the P-type substrate 10 and the N well 1 are also included.
Reference numeral 8 denotes an npn-type second parasitic transistor (second parasitic T
r) 68.

The high-concentration impurity diffusion region (p +) 34 provided on the P-type substrate 10 of the internal circuit 12 and the P-type substrate 1 are also included.
Between 0 and 0, a substrate resistance R ₂ 70 is parasitically generated.

The source (p +) 40 of the PMOSTr 36 of the output circuit 14, the N well 38 and the P type substrate 10 are also provided.
Is a pnp-type third parasitic transistor (third parasitic Tr) corresponding to the emitter, the base and the collector, respectively.
72 is configured. The collector of the third parasitic Tr 72 is connected to the P-type high-concentration impurity diffusion region (p +) 58 of the latch-up prevention protection circuit and the P-type high-concentration impurity diffusion region (of the internal circuit 12) via the p-type substrate 10. p +) 3
4 connected to each. Therefore, the third parasitic Tr
72 is a multi-collector type.

The drain (p ⁺ ) 42 of the PMOSTr 26 of the output circuit 14, the N well 38 and the P type substrate 1 are also provided.
0 corresponds to the emitter, the base, and the collector, and corresponds to a pnp-type fourth parasitic transistor (fourth parasitic T
r) 74. The collector of the fourth parasitic Tr 74 is connected to the P-type high-concentration impurity diffusion region (p +) 58 of the latch-up prevention protection circuit and the P-type high-concentration impurity diffusion region (of the internal circuit 12 (via the p-type substrate 10). p
+) 34 connected to each. Therefore, the fourth parasitic Tr 74 also becomes a multi-collector type.

The source (n +) 50 of the NMOSTr 46 of the output circuit 14 and the P-type substrate 10 correspond to the emitter and the base, respectively, and the N-well 38 and the N-type impurity diffusion region 6 of the latch-up prevention / protection circuit 6 are provided.
2 (including N-type high-concentration impurity diffusion region (n +) 60)
Corresponds to the collector and constitutes an npn-type fifth parasitic transistor (fifth parasitic Tr) 76. Therefore, the fifth
The parasitic Tr76 also becomes a multi-collector type.

Further, the drain (n +) 52 of the NMOSTr 46 of the output circuit 14 and the P-type substrate 10 correspond to the emitter and the base, respectively, and the N-well 38 and the N-type impurity diffusion region 62 of the latch-up prevention / protection circuit 62. The (n-type high-concentration impurity diffusion region (n +) 60 is included) corresponds to the collector and constitutes the npn-type sixth parasitic transistor (sixth parasitic Tr) 78. Therefore,
The sixth parasitic Tr 78 also becomes a multi-collector type.

(Regarding Latch-up Phenomenon and Operation of Latch-up Prevention / Protection Circuit) Next, the latch-up phenomenon and the latch-up phenomenon will be described as an example in which a positive surge voltage is applied to the semiconductor device of Comparative Example 1 from the output terminal 54. The operation of the up prevention protection circuit will be described.

The surge current flowing from the output terminal 54 flows into the semiconductor device from the drain 42 which is the emitter of the fourth parasitic Tr 74. This surge current flows as a base current of the fourth parasitic Tr 74 from the N-type high-concentration impurity diffusion region 60 to the power supply voltage source V _CC , and also the fourth parasitic T
The collector current of r74 flows to the P-type substrate 10.
Part of the surge current flowing to the P-type substrate 10 flows from the P-type high-concentration impurity diffusion region 58 of the latch-up prevention / protection circuit to the ground voltage source V _SS , and the remaining part of the surge current flows to the internal circuit 12.
From the P-type high-concentration impurity diffusion region 34 to the ground voltage source.

At this time, the surge current i ₁ flowing to the P type high concentration impurity diffusion region 58 of the latch-up prevention / protection circuit is sufficiently large, and as a result, it flows to the P type high concentration impurity diffusion region 34 of the internal circuit 12. If the surge current i ₂ is sufficiently small, it is possible to prevent latch-up from occurring in the internal circuit.

However, if the surge current i ₂ flowing to the P-type high-concentration impurity diffusion region 34 of the internal circuit 12 increases, this surge current i ₂ triggers and latches in the internal circuit 12 as follows. Up occurs.

The surge current i ₂ increases and the substrate resistance R
_When the potential difference between both ends of 2 reaches the level for forward biasing the base-emitter of the second parasitic Tr68, the base current of the second parasitic Tr68 flows and the second parasitic Tr68
Is turned on. As a result, the second parasitic transistor 6
A collector current of 8 is supplied from the power supply voltage V _CC . At that time, the collector current is supplied from the power supply voltage V _CC through a well resistor R _1. Therefore, due to this collector current, the potential difference across the well resistance R ₁ becomes the first parasitic Tr.
When the level of forward biasing the base-emitter of 64 is reached, the base current of the first parasitic Tr64 flows,
This first parasitic Tr64 is turned on. As a result, the base current and the collector current of the first parasitic Tr 64 and the second parasitic Tr 68 multiply positively with each other, thereby causing latch-up.

On the other hand, in Comparative Example 1, the surge current i ₂ flowing to the internal circuit 12 is reduced by providing the latch-up protection circuit 56 as described above, and the occurrence of latch-up is suppressed. In Comparative Example 1, all the parasitic bipolar transistors formed in the output circuit 14 are of the multi-collector type, and hence this latch-up prevention protection circuit is also referred to as a multi-collector type latch-up prevention protection circuit.

When a negative surge voltage is applied to the output terminal, the surge is the source 5 of the NMOSTr 46.
It flows in from 0 (the direction of the current is opposite). In this case, it is possible to reduce the surge flowing to the internal circuit 12 by flowing a part of the surge to the N-type high-concentration impurity diffusion region 60 of the latch-up prevention / protection circuit. As a result, occurrence of latch-up in the internal circuit 12 can be suppressed.

(Comparative Example 2) Next, with reference to FIG. 14, a case will be described as Comparative Example 2 in which the substrate potential generating circuit is provided in the semiconductor device of Comparative Example 1 described above. FIG.
4 is a schematic sectional view for explaining a semiconductor device of Comparative Example 2. FIG. In FIG. 14, the circuit and the parasitic circuit are shown together with the diffusion region of the circuit. In Comparative Example 2, Comparative Example 1
Constituent components that are the same as the above are given the same reference numerals, and description thereof is omitted.

The semiconductor device of Comparative Example 2 includes a substrate potential generating circuit 80. Then, the potential generated by the substrate potential generation circuit 80 is passed through the internally generated potential line and the P-type high concentration impurity diffusion region (p
+) 34 and a P-type high-concentration impurity diffusion region (p +) 58 of the latch-up prevention / protection circuit. The potential V _BB applied to the P-type substrate 10 from the substrate potential generation circuit 80 is set to a potential V lower than the ground potential V _SS .

By the way, in the comparative example 2 provided with the substrate potential generating circuit 80, unlike the case of the comparative example 1, it is impossible to suppress the occurrence of latch-up by making the parasitic transistor a multi-collector type. Hereinafter, the reason will be described.

In the semiconductor device of Comparative Example 2, 54 from the output terminal
When the positive surge voltage is applied, the surge current flowing from the output terminal 54 flows into the semiconductor device from the drain 42 which is the emitter of the fourth parasitic Tr 74. This surge current serves as the base current of the fourth parasitic Tr 74 and is N
In addition to flowing from the high concentration impurity diffusion region 60 of the type to the power supply voltage source V _CC , P
It flows to the mold substrate 10. Part of the surge current flowing to the P-type substrate 10 flows from the P-type high-concentration impurity diffusion region 58 of the latch-up prevention / protection circuit to the substrate potential generation circuit 80,
The remaining portion flows from the P-type high-concentration impurity diffusion region 34 of the internal circuit 12 to the ground voltage source.

However, the substrate potential generating circuit 80 is
The current supply capability is originally small, and the internal impedance as a power source is large. Therefore, when the surge current flows into the substrate potential generation circuit 80, the substrate potential V _BB itself is easily pulled up to the high potential side. This substrate potential V _BB is raised, and PN is further increased than the ground potential V _SS.
When the junction forward voltage (V _f ) is increased, the drain 32 of the NMOS Tr 26 of the P-type substrate 10 and the internal circuit 12 is increased.
The PN junction formed by and is forward biased.

As a result, as described in Comparative Example 1, the base current of the second parasitic Tr 68 flows, and the second parasitic Tr 68 flows.
The parasitic Tr 68 is turned on. As a result, the collector current of the second parasitic transistor 68 is supplied from the power supply voltage V _CC . At this time, this collector current is generated by the well resistance R _1
Is supplied from the power supply voltage V _CC via. Therefore, when this collector current causes the potential difference across the well resistor R ₁ to reach a level at which the base-emitter of the first parasitic Tr 64 is forward biased, the base current of the first parasitic Tr 64 flows, and the first parasitic Tr 64 flows. Tr64 is turned on.
As a result, the base current and the collector current of the first parasitic Tr 64 and the second parasitic Tr 68 multiply positively with each other, thereby causing latch-up.

As described above, when the substrate potential generating circuit 80 is provided, the substrate potential V _BB easily rises due to the surge current. Therefore, even if the latch-up prevention protection circuit is provided, the occurrence of latch-up is suppressed. Can not do.

Metal wiring (internally generated potential line) for supplying the substrate potential V _BB to the entire chip on which the semiconductor device is formed.
Are also routed to a plurality of other CMOS internal circuits. In any CMOS internal circuit, PMOST
r and NMOSTr are arranged at the minimum distance. Therefore, in these CMOS internal circuits, an npn-type parasitic bipolar transistor (second parasitic T of Comparative Example 2) is used.
The base width (corresponding to r) is also the smallest. For this reason, the current amplification factor (hFE) of the parasitic bipolar transistor becomes larger than that of the peripheral circuit section, so that latch-up is more likely to occur. This means that in the semiconductor device provided with (built-in) the substrate potential generation circuit, once the substrate potential V _BB is raised, latch-up may occur in an unspecified COMS internal circuit. . That is,
Latch-up resistance is reduced.

On the other hand, in a semiconductor device having a built-in substrate potential generating circuit, if no latch-up prevention / protection circuit is provided, a surge current easily flows into the internal COMS circuit, and latch-up occurs. Therefore, in order to prevent latch-up, a CMOS output circuit and C
When the base length of the npn-type transistor of the parasitic bipolar transistor is increased by increasing the distance between the PMOSTr and the NMOSTr of the OMS internal circuit, the base length of the parasitic npn-type transistor of all CMOS internal circuits must be increased. I won't. Of the CMOS internal transistors, this is the PMOSTr and NMOSTr
The reason is that the latch-up resistance of the entire semiconductor device is determined by the minimum distance between and. Therefore, if the latch-up is suppressed by increasing the base length, the chip area increases and the chip cost increases.

(First Embodiment) Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic sectional view for explaining the semiconductor device according to the first embodiment. In FIG. 1, a circuit and a parasitic circuit are shown together with a diffusion region of the circuit. FIG.
3A is a plane pattern used for description of the semiconductor device of the first embodiment. Further, in FIG. 2, illustration of a field oxide film, wiring, and the like on the substrate is omitted in order to show the arrangement relationship of the diffusion regions in a planar pattern. In FIG. 2,
In order to facilitate understanding of the drawings, not a cross-sectional portion but a part is shown with hatching. FIG. 1 corresponds to a cross section taken along the line XX in FIG.

In the first embodiment, the same components as those of Comparative Example 1 or Comparative Example 2 described above are designated by the same reference numerals, and detailed description thereof will be omitted.

(Regarding the Configuration of the First Embodiment) In the semiconductor device of the first embodiment, the P-type substrate 10 is used.
A substrate potential generating circuit 80 for applying a potential to
An OS internal circuit 12, a PMOS output circuit (hereinafter also referred to as an output circuit) 82 for outputting a signal from the CMOS internal circuit 12 to an output line, and a latch for preventing the CMOS internal circuit 12 from latching up. An up prevention protection element (hereinafter, also referred to as a protection element) 84 is provided. Since the structure of the CMOS internal circuit 12 is the same as that of the above-described comparative example 1, its detailed description is omitted.

The PMOS output circuit 82 is formed in the N well 86 formed in the P type substrate 10.
A power supply voltage V _{CC of} 3.0 V is applied to the N well 86 and the source (p +) 88 of the PMOS output circuit 82. The power supply voltage V _CC is applied to the N well 86 via a high concentration impurity diffusion region (n +) 92 having an impurity concentration higher than that of the N well 86. Also, PMOS
The drain (p +) 90 of the output circuit 82 is connected to the output terminal 54 via the output line.

The latch-up prevention protection element 84 is also provided.
Is connected to the power supply voltage line as the first power supply line to which the power supply voltage V _{CC of} 3.0 V is applied and the ground voltage line as the second power supply line to which the ground voltage V _{SS of} 0 V is applied. And are connected in parallel.

The latch-up prevention protection element 8
4 is an N type first diffusion region (N well) on the P type substrate 10.
96, and in the first diffusion region 96, the first
A second diffusion region (n +) 98 of N type having an impurity concentration higher than that of the diffusion region 96;
The diffusion region 96 includes a P-type third diffusion region (p +) 100 provided apart from the second diffusion region 98, and the P-type substrate 10 around the first diffusion region 96 includes: N provided so as to be separated from the first diffusion region 96 and substantially surround the first diffusion region 96 when viewed in a plane pattern.
The mold includes a fourth diffusion region (N well) 102. In the plane pattern of FIG. 2, the fourth diffusion region 102 is formed in a square shape surrounding the first diffusion region (N well) 96.

The third diffusion region 100 is connected to the output line. Further, the second diffusion region (n +) 98 is
It is connected to the first power supply line to which the power supply voltage V _{CC of} 3.0 V is applied. In addition, the fourth diffusion region (N well) 102
Is connected to the second power supply line to which the ground voltage V _{SS of} 0V is applied. The ground voltage V _SS is a high-concentration impurity diffusion region (n +) whose impurity concentration is higher than that of the fourth diffusion region 102.
It is applied to the fourth diffusion region 102 via 104.

Further, in this embodiment, the internal potential generation line to which the substrate potential V _BB generated in the substrate potential generation circuit 80 is applied has the P-type high concentration impurity outside the latch-up prevention protection element 84. It is connected to the P-type substrate 10 via the diffusion region (p +) 94. This P-type substrate 1
The substrate potential V _{BB of} 0 is lowered to a lower potential side than the ground voltage V _SS .

(Regarding Parasitic Circuit of First Embodiment) Next, the parasitic circuit of the semiconductor circuit of the first embodiment will be described. Since the parasitic circuit formed in the internal circuit 12 is the same as that in the case of the comparative example 1, its detailed description is omitted.

In the first embodiment, the internal circuit 1
In addition to the first parasitic Tr64 and the second parasitic Tr68 of 2,
The source (p +) 88, the N well 86 and the P-type substrate 10 of the PMOS output circuit 82 form a pnp-type third parasitic transistor (third parasitic Tr) 106 corresponding to the emitter, the base and the collector, respectively. There is.

The drain (p +) 90, the N well 86 and the P-type substrate 10 of the PMOS output circuit 82 correspond to the emitter, the base and the collector, respectively, and p
np type fourth parasitic transistor (fourth parasitic Tr) 108
Is composed.

Further, in the latch-up prevention protection element, the third diffusion region (p +) 100, the first diffusion region (N well) 96 and the P-type substrate 10 are the emitter,
A pnp type fifth parasitic transistor (fifth parasitic Tr) 110 is formed corresponding to the base and the collector.

The fourth diffusion region (N well) 102,
The P-type substrate 10 and the first diffusion region (N well) 96 are
Corresponding to the emitter, base and collector respectively
npn-type sixth parasitic transistor (sixth parasitic Tr) 11
Make up 2. In FIG. 1, the sixth parasitic Tr112
Are shown in two places.

The fifth parasitic Tr 110 and the sixth parasitic Tr 112 are connected to the parasitic SCR (Semiconductor Cont).
rolled Rectifier).

(Regarding Operation of First Embodiment) Next, the latch-up phenomenon and the latch-up phenomenon will be described by taking the case where a positive surge voltage is applied from the output terminal 54 to the semiconductor device of the first embodiment as an example. The operation of the up prevention protection element will be described.

The positive surge current flowing from the output terminal 54 is shunted and flows into the third diffusion region (p +) 100 of the protection element 84 and the drain (p +) 90 of the output circuit 82.

The third which is the emitter of the fifth parasitic Tr110
The surge current flowing into the diffusion region (p +) 100 is further shunted, and a part thereof flows as the base current i ₁ of the fifth parasitic Tr 110 from the second diffusion region (n +) to the power supply voltage source V _CC , and the remaining part. Flows to the P-type substrate 10 as the collector current i ₂ of the fifth parasitic resistance Tr110. The surge current i _{2 that} has flowed to the P-type substrate 10 that is also the base of the sixth parasitic Tr112 is drawn as a base current of the sixth parasitic Tr112 from the fourth diffusion region 102 that is also the emitter of the sixth parasitic Tr112 to the ground power supply line. .

The fourth diffusion region 102 is the first diffusion region (N well) in which the third diffusion region (p +) 100 is formed.
Since it is provided so as to surround 96, almost all of the surge current i ₂ flowing to the P-type substrate 10 is extracted from the fourth diffusion region 102. As a result, the region where the substrate potential V rises due to the surge current i ₂ flowing in is substantially limited to the region surrounded by the fourth diffusion region 102. Therefore, it is possible to prevent the substrate potential of the P-type high-concentration impurity diffusion region (p +) 94 connected to the substrate potential generation device 80 from increasing outside the latch-up prevention protection element 84.

The surge current that has flown into the drain (p +) 90 of the output circuit 82, which is also the emitter of the fourth parasitic Tr 108, is further shunted and part of it is the fourth parasitic T.
The base current i ₃ of r108 flows from the N-type high-concentration impurity diffusion region (n +) 92 to the power supply voltage source V _CC , and the remaining portion is P as the collector current i ₄ of the fourth parasitic Tr 108.
It flows to the mold substrate 10. The surge current i ₄ flowing into the P-type substrate 10 flows into the internal circuit 12.

The surge current flowing from the output terminal 54 is divided into four currents i _{1 to} i ₄ as described above. As a result, the surge current i ₄ flowing to the internal circuit 12 becomes small. Therefore, the amount of the surge current i ₄ flowing into the internal circuit 12 is smaller than that of, for example, a semiconductor circuit provided with no latch-up prevention protection circuit or a semiconductor circuit provided with the multi-collector type latch-up prevention protection circuit described in Comparative Example 1. Can be reduced. Therefore, it is possible to suppress the substrate potential V _BB in the region where the internal circuit 12 is formed from being raised to the potential at which latch-up occurs.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a schematic sectional view for explaining the semiconductor device according to the second embodiment. In FIG. 3, a circuit and a parasitic circuit are shown together with a diffusion region of the circuit.

In the second embodiment, the same components as those in the first embodiment described above are designated by the same reference numerals, and detailed description thereof will be omitted.

(Regarding the Configuration of the Second Embodiment) In the semiconductor device of the second embodiment, the P type and the N type are replaced with each other in the first embodiment, and the power supply voltage V _CC and ground are used. The connection with the voltage V _SS is exchanged.

In the semiconductor device of the second embodiment, the substrate potential generation circuit 80 for applying a potential to the N-type substrate 120, the CMOS internal circuit (hereinafter also referred to as the internal circuit) 122, and the CMOS internal circuit. An NMOS output circuit (hereinafter, also referred to as an output circuit) 124 for outputting a signal from the circuit 122 to an output line, and a latch-up prevention protection element (hereinafter, protection element) for preventing latch-up of the CMOS internal circuit 122 Also referred to as 126). The N-type substrate 120 is usually provided with a plurality of internal circuits other than the illustrated internal circuit 122.

N constituting the CMOS internal circuit 122
Type MOS transistor (also referred to as NMOSTr) 12
8 is a P well (Pwel) formed on the N-type substrate 120.
l) 130. And NMOSTr1
A ground voltage V _{SS of} 0V is applied to the drain (n +) 132 of 28 and the P well 130. The ground voltage V _SS is applied to the P well 130 via the P-type high-concentration impurity diffusion region (p +) 136 whose impurity concentration is higher than that of the P well 130.

Further, a P-type MOS transistor (also referred to as PMOSTr) 1 forming the COMS internal circuit 122 is provided.
38 is formed on the N-type substrate 120. And P
A power supply voltage V _{CC of} 3.0 V is applied to the source (p +) 144 of the MOSTr 138 and the N-type substrate 120.

Further, the NMOS output circuit 122 has N
It is formed in the P well 148 formed in the mold substrate 120. The ground voltage V _{SS of} 0V is applied to the P well 148 and the drain (n +) 152 of the NMOS output circuit 122. The ground voltage V _SS is applied to the P well 148 via the P-type high-concentration impurity diffusion region (p +) 156 having an impurity concentration higher than that of the P well 148. In addition, the source (n
+) 154 is connected to the output terminal 54 via the output line.

Further, the latch-up prevention protection element 12
Reference numeral 6 denotes an output circuit for the ground voltage line as the first power supply line to which the ground voltage V _{SS of} 0V is applied and the power supply voltage line as the second power supply line to which the power supply voltage V _{CC of} 3.0V is applied. 124
And are connected in parallel.

The latch-up prevention protection element 1
26 includes a P-type first diffusion region (P-well) 158 in the N-type substrate 120, and the first diffusion region 158
The semiconductor device includes a P-type second diffusion region (p +) 160 having an impurity concentration higher than the impurity concentration of the first diffusion region 158.
N-type third diffusion region (n
+) 162, and the N-type substrate 120 around the first diffusion region 158 is spaced apart from the first diffusion region 158 and substantially surrounds the first diffusion region 158 when viewed in a plane pattern. The P-type fourth diffusion region (P well) 164 thus provided is provided.

The third diffusion region 162 is connected to the output line. Further, the second diffusion region (p +) 160
It is connected to the first power supply line to which the ground voltage V _{SS of} 0V is applied. In addition, the fourth diffusion region (P well) 164 is
It is connected to the second power supply line to which the power supply voltage V _{CC of} 3.0 V is applied. The power supply voltage V _CC is applied to the fourth diffusion region 164 through the P-type high-concentration impurity diffusion region (p +) 166 having an impurity concentration higher than that of the fourth diffusion region 164.

In this embodiment, the internal potential generating line to which the substrate potential V _BB generated in the substrate potential generating circuit 80 is applied is the N-type high concentration impurity outside the latch-up prevention protection element 126. Diffusion region (n +) 15
0 is connected to the N-type substrate 120. Substrate potential V _BB of N-type substrate 120 is raised to a higher potential side than power supply voltage V _CC .

(Regarding Parasitic Circuit of Second Embodiment) Next, a parasitic circuit of the semiconductor circuit of the second embodiment will be described. The parasitic circuit formed in the second embodiment has the npn type and the pnp type exchanged with those in the first embodiment.

In the first embodiment, the internal circuit 1
22, the drain (n +) 132 of the NMOS Tr 128,
The P-well 130 and the N-type substrate 120 constitute an npn-type first parasitic transistor (first parasitic Tr) 168 corresponding to the emitter, base and collector, respectively. The base of the first parasitic Tr 168 is the internal circuit 1
Through the P-type high-concentration impurity diffusion region (p +) 136 in the 22 P-well 130, it is connected to the ground voltage.
Then, the base and the P-type high concentration impurity diffusion region (p
+) 136, a well resistance R ₁ 170 is parasitically generated.

In addition, the PMOSTr13 of the internal circuit 122
8, a source (n +) 144, an N-type substrate 120, and a P-well 130 correspond to an emitter, a base, and a collector, respectively.
(Parasitic Tr) 172.

Further, the drain (n +) 152 of the NMOS output circuit 124, the P well 148 and the N type substrate 120.
Is an npn-type third parasitic transistor (third parasitic Tr) corresponding to the emitter, the base and the collector, respectively.
174 are configured.

Further, the source (n +) 154 of the NMOS output circuit 124, the P well 148 and the N type substrate 120.
Is an npn-type fourth parasitic transistor (fourth parasitic Tr) corresponding to the emitter, the base and the collector, respectively.
176 is configured.

In the latch-up prevention protection element, the third diffusion region (n +) 162, the first diffusion region (P well) 158 and the N-type substrate 120 correspond to the emitter, the base and the collector, respectively, and npn. Type 5
A parasitic transistor (fifth parasitic Tr) 178 is configured.

The fourth diffusion region (P well) 164,
N-type substrate 120 and first diffusion region (P well) 158
Is a pnp type sixth parasitic transistor (sixth parasitic Tr) corresponding to the emitter, the base and the collector, respectively.
It constitutes 180. In FIG. 1, the sixth parasitic Tr1
80 is shown in two places.

The fifth parasitic Tr 178 and the sixth parasitic Tr 180 are connected to the parasitic SCR (Semiconductor Cont).
rolled Rectifier).

(Regarding Operation of Second Embodiment) Next, the latch-up phenomenon and the latch-up phenomenon will be described as an example in which a negative surge voltage is applied from the output terminal 54 to the semiconductor device of the second embodiment. The operation of the up prevention protection element will be described. In FIG. 3, since the negative surge voltage is applied, the directions of i _{1 to} i ₄ indicating the surge current are shown in FIG.
The direction is opposite to the inside.

The negative surge flowing from the output terminal 54 is shunted and flows into the third diffusion region (p +) 162 of the protection element 126 and the source 154 of the output circuit 124.

The third which is the emitter of the fifth parasitic Tr178
The surge that has flowed into the diffusion region (n +) 162 is further shunted, and a part thereof flows from the second diffusion region (p +) 160 to the ground voltage source V _SS as the base current i ₁ of the fifth parasitic Tr 178, and the remaining portion. Flows to the N-type substrate 120 as the collector current i ₂ of the fifth parasitic resistance Tr178. Sixth
The surge i _{2 that} has flowed to the N-type substrate 120 that is also the base of the parasitic Tr 180 is extracted as a base current of the sixth parasitic Tr 180 from the fourth diffusion region 164 that is also the emitter of the sixth parasitic Tr 180 to the power supply voltage line.

The fourth diffusion region 164 is the first diffusion region (P well) in which the third diffusion region (n +) 162 is formed.
Since it is provided so as to surround 158, the N-type substrate 12
Almost all of the surge i ₂ flowing to 0 is extracted from the fourth diffusion region 164. As a result, the region where the substrate potential V rises due to the surge i ₂ flowing in is substantially limited to the region surrounded by the fourth diffusion region 164. Therefore, it is possible to prevent the substrate potential of the N-type high-concentration impurity diffusion region (n +) 150 connected to the substrate potential generation device 80 from increasing outside the latch-up prevention protection element 126.

The surge that has flown into the source (n +) 154 of the output circuit 124, which is also the emitter of the fourth parasitic Tr 176, is further shunted, and a part of it is part of the fourth parasitic Tr 176.
The base current i ₃ of 176 flows from the P-type high-concentration impurity diffusion region (p +) 156 to the ground voltage source V _SS , and the remaining part is N as the collector current i ₄ of the fourth parasitic Tr 176.
It flows to the mold substrate 120. The surge i ₄ flowing to the N-type substrate 120 flows to the internal circuit 12.

The surge flowing from the output terminal 54 is shunted into the four currents i _{1 to} i ₄ as described above. As a result, the surge i ₄ flowing to the internal circuit 122 is reduced. Therefore, the amount of surge i ₄ flowing into the internal circuit 122 is smaller than that of a semiconductor circuit having no latch-up prevention protection circuit or a semiconductor circuit having the multi-collector type latch-up prevention protection circuit described in Comparative Example 1, for example. can do. Therefore, it is possible to prevent the substrate potential V _BB in the region where the internal circuit 122 is formed from being lowered to the potential at which latch-up occurs.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic sectional view for explaining the semiconductor device according to the third embodiment. In FIG. 4, a circuit and a parasitic circuit are shown as well as a diffusion region of the circuit.

In the semiconductor device of the third embodiment, the gate oxide film is interposed 184 on the portion of the first diffusion region 96 between the second diffusion region 98 and the third diffusion region 100 of the latch-up prevention protection element. Then, the gate electrode 1 of the MOS transistor
The semiconductor device has the same configuration as the semiconductor device according to the first embodiment except that the semiconductor device according to the first embodiment is provided. For this reason, in the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. Further, the semiconductor device of the third embodiment when a surge voltage is applied is also the same as that of the first embodiment, so its detailed description is omitted.

In the third embodiment, the second diffusion region 98 and the third diffusion region 100 respectively correspond to the source-drain of the MOS transistor. The power supply voltage V _{CC of} 3.0 V is applied to the gate electrode 182, and the channel immediately below the gate electrode is maintained in a closed state. Therefore, the second diffusion region 98 and the third diffusion region 100 are separated by the gate electrode 182.

By providing the gate electrode 182, the distance required for separating the second diffusion region 98 and the third diffusion region 100 is shorter than that in the case where the field oxide film is provided in the first embodiment. You can As a result, the area occupied by the latch-up prevention protection element can be reduced.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a schematic sectional view for explaining the semiconductor device according to the fourth embodiment. In FIG. 5, a circuit and a parasitic circuit are shown together with a diffusion region of the circuit.

In the semiconductor device according to the fourth embodiment, the gate oxide film 184 is provided on the first diffusion region 158 portion between the second diffusion region 160 and the third diffusion region 162 of the latch-up prevention protection element. The semiconductor device has the same structure as the semiconductor device of the second embodiment except that the gate electrode 182 of the MOS transistor is provided. Therefore, in the fourth embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
Further, the semiconductor device of the fourth embodiment when a surge voltage is applied is also the same as that of the second embodiment, and a detailed description thereof will be omitted.

In the fourth embodiment, the second diffusion region 160 and the third diffusion region correspond to the source-drain of the MOS transistor, respectively. The ground voltage V _{SS of} 0 V is applied to the gate electrode 182, and the channel immediately below the gate electrode is maintained in a closed state. Therefore, the second diffusion region 160 and the third diffusion region 162 are separated by the gate electrode 182.

Second diffusion region 160 and third diffusion region 162
By providing the gate electrode 182, the distance required for the separation from and can be shortened as compared with the case where the field oxide film is provided in the first embodiment. As a result, the area occupied by the latch-up prevention protection element can be reduced.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIG. 6A and 6B are schematic circuit diagrams for explaining the semiconductor device according to the fifth embodiment, and FIG. 6A shows a semiconductor device formed on a P-type substrate. FIG. 6B shows a case where the semiconductor device is formed on the N-type substrate.

The structure of the diffusion region of the semiconductor device of the fifth embodiment shown in FIG. 6A is the same as that of the first embodiment except that the output circuit is a CMOS transistor (hereinafter also referred to as CMOSTr) 186. It is the same as the embodiment. Therefore, detailed description of the same components as in the first embodiment will be omitted.

The CMOSTr 186 is a P-type M
OS transistor (hereinafter also referred to as PMOSTr)
188 and an N-type MOS transistor (hereinafter, NMOSTr
190). And PMOST
The source of r is connected to the power supply V _CC through the power supply voltage line. Further, the drain of the NMOSTr is connected to the ground voltage V _SS via the ground voltage line. And PMO
The drain of the STr 188 and the source of the NMOS Tr 190 are connected to the output line via a pure resistance element 192 of about 10Ω. The pure resistance element 192 is separated from the P-type substrate by an insulating film. Therefore, the pure resistance element 192 does not serve as a new injection source of the surge current to the P-type substrate.

Further, the latch-up prevention protection element 84 is
It is directly connected to the output line without going through the pure resistance element 186. Therefore, the output circuit 186 and the latch-up prevention protection element 54 are connected via this pure resistance 192.

When viewed from the output terminal (bonding pad for external connection) 54 connected to the output line, the output circuit 186 is electrically higher in resistance than the latch-up prevention protection element 84. Therefore, the ratio of the surge current flowing from the output terminal 54 to the latch-up prevention protection element 84 is high, and the output circuit 18 is correspondingly increased.
The rate of flowing to 6 becomes low. As a result, the output circuit 186
It is possible to reduce the surge current that reaches the internal circuit 12 via This corresponds to a decrease in the surge current i ₄ that may trigger latch-up in the first embodiment described above. Therefore, the latch-up resistance can be made higher than that of the semiconductor device of the first embodiment.

Further, in the structure of the diffusion region of the semiconductor device of the fifth embodiment shown in FIG. 6B, the output circuit has a CMO.
S transistor (hereinafter also referred to as CMOSTr) 1
It is the same as the second embodiment except that it is 86.
In the semiconductor device shown in FIG. 6B, the output circuit 186 and the latch-up prevention protection element 126 are connected via the pure resistance 192, and the output terminal connected to the output line (external connection). Bonding pad) 54, the output circuit 186 has a latch-up prevention protection element 126.
It has a higher electrical resistance than.

Therefore, also in this case, it is possible to reduce the surge flowing through the output circuit 186 and to improve the latch-up resistance higher than that of the semiconductor device of the second embodiment.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to FIG. 7A and 7B are schematic circuit diagrams for explaining the semiconductor device according to the sixth embodiment, and FIG. 7A shows a semiconductor device formed on a P-type substrate. 7B shows a case where a semiconductor device is formed on an N-type substrate.

By the way, if a pure resistance element 192 is interposed between the output circuit 186 and the output terminal 54 in order to suppress the inflow of the surge current, the output terminal 54 responds to the signal output from the output circuit 186. There is a delay in the potential transition of. For this reason, while the latch-up resistance is improved, the drive capability of the semiconductor device is impaired.

Therefore, in the semiconductor device of the sixth embodiment shown in FIG. 7A, one of the CMOSTr 186, which is the source of the surge current injection, is the PMOSTr 188.
Only the drain of the output terminal 54 through the pure resistance 192
Connected to The source of the NMOSTr 190 that is not the surge current injection source is a pure resistor 192.
It is directly connected to the output terminal 54 without going through. Therefore, the drive capability of the NMOSTr 190 does not decrease.
As a result, it is possible to have the same latch-up resistance as the semiconductor element of the fifth embodiment and to suppress the reduction of the drive capability of the semiconductor device.

Also in the semiconductor device of the sixth embodiment shown in FIG. 7B, one of the CMOSTr 186, which is the source of the surge current injection, is the NMOSTr 190.
Only the drain of the output terminal 54 through the pure resistance 192
Connected to The source of the PMOSTr 188, which is not the surge current injection source, is a pure resistor 192.
It is directly connected to the output terminal 54 without going through. Therefore, the drive capability of the PMOSTr 188 does not decrease.
As a result, it is possible to have the same latch-up resistance as the semiconductor element of the fifth embodiment and to suppress the reduction of the drive capability of the semiconductor device.

(Seventh Embodiment) Next, a semiconductor device according to a seventh embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a schematic sectional view for explaining the semiconductor device according to the seventh embodiment. In FIG. 8, a circuit and a parasitic circuit are shown as well as a diffusion region of the circuit. Further, FIG. 9 is a plane pattern used for description of the semiconductor device of the seventh embodiment. Further, in FIG. 9, the field oxide film, the wiring, and the like on the substrate are not shown in order to show the arrangement relationship of the diffusion region in a plane pattern. In addition, FIG.
In order to facilitate understanding of the drawings, not a cross section but a part is hatched. FIG. 8 shows Y of FIG.
Corresponds to the cross-section at the cut along -Y.

The configuration of the semiconductor device of the seventh embodiment is as follows.
A drain (p +) 90 of the PMOS output circuit 82 is connected to the output terminal 54 via a pure resistance R ₃ 192, and a pure resistance element R ₄ 194 of about 30Ω is connected to the ground line around the output circuit 82. The fifth embodiment is the same as the third embodiment except that the N-type fifth diffusion region 196 connected through is provided so as to substantially surround the output circuit 82 when viewed in a plane pattern. It is the same. Therefore, detailed description of the same components as those in the third embodiment will be omitted.

The fifth diffusion region 196 is formed in a U shape around the output circuit 82 as shown in the plan pattern of FIG. By providing the fifth diffusion region 196, as shown in FIG.
6, N-well 86 of P-type substrate 10 and output circuit 82
, A seventh parasitic transistor (seventh parasitic Tr) 198 corresponding to the emitter, the base and the collector is formed.

The fifth diffusion region 196 is connected to the pure resistor R ₄ 194 via the N-type high concentration impurity diffusion region 200 having an impurity concentration higher than that of the fifth diffusion region 196. This pure resistance R ₄ 194 is the fourth parasitic Tr 108.
It is provided in order to suppress the occurrence of latch-up in the thyristor including the seventh parasitic Tr 198.

Since the pure resistance R ₃ 192 is provided, the output circuit 82 is provided as described in the sixth embodiment.
It is possible to reduce the surge current flowing into the. Therefore, the surge current i ₄ flowing from the output circuit 82 to the P-type substrate 10 can be reduced, and the latch-up resistance is improved. Since the pure resistance element R ₃ 192 is formed on the P-type substrate 10 via the insulating film, the pure resistance element R ₃ 192 does not serve as a new injection source of the surge current.

By the way, from the output circuit 82 to the P-type substrate 10
It is difficult to completely suppress the surge current i ₄ flowing to the. Therefore, in the seventh embodiment, by dividing the surge current i ₄ into the fifth diffusion region 196 and the internal circuit 12, the surge current i flowing into the internal circuit 12 is obtained.
₄ is being further reduced. As a result, the latch-up resistance can be further improved. For example, 100m
Even when a surge current of about A flows in from the output terminal 54, the occurrence of latch-up can be suppressed.

(Eighth Embodiment) Next, a semiconductor device according to an eighth embodiment will be described with reference to FIG. FIG. 10 is a schematic sectional view for explaining the semiconductor device according to the eighth embodiment. In FIG. 10, a circuit and a parasitic circuit are shown together with a diffusion region of the circuit.

The structure of the semiconductor device of the eighth embodiment is as follows.
A source (n +) 154 of the NMOS output circuit 124 is connected to the output terminal 54 via a pure resistance R ₃ 192, and a pure resistance element R ₄ 194 of about 30Ω is connected to the ground line around the output circuit 124. The P-type fifth diffusion region 202 connected through the output circuit 12 is
4 is the same as the fourth embodiment except that it is provided so as to substantially surround 4. Therefore, detailed description of the same components as in the fourth embodiment will be omitted.

By providing the fifth diffusion region 202, the fifth diffusion region 202, the N-type substrate 120 and the N well 148 of the output circuit 124 are respectively the emitter and the emitter.
A seventh parasitic transistor (seventh parasitic Tr) 204 corresponding to the base and the collector is formed.

The fifth diffusion region 202 is connected to the pure resistor R ₄ 194 via the P-type high concentration impurity diffusion region 206 having a higher impurity concentration than the fifth diffusion region 202. This pure resistance R ₄ 194 is the fourth parasitic Tr 108.
Also, it is provided in order to suppress the occurrence of latch-up in the thyristor including the seventh parasitic Tr204.

Further, by providing the pure resistance R ₃ 192, the output circuit 12 is provided as described in the seventh embodiment.
The surge flowing to 4 can be reduced. Therefore, the surge i ₄ flowing from the output circuit 124 to the N-type substrate 120 can be reduced, and the latch-up resistance is improved. Since the pure resistance element R ₃ 192 is formed on the N-type substrate 120 via the insulating film, the pure resistance element R ₃ 192
_The 3192 will not be a new source of surge current injection.

By the way, from the output circuit 124 to the N-type substrate 1
It is difficult to completely suppress the surge i ₄ flowing to 20. Therefore, in the eighth embodiment, the surge i ₄ is divided into the fifth diffusion region 202 and the internal circuit 128 to further reduce the surge i ₄ flowing into the internal circuit 128. As a result, the latch-up resistance can be further improved. For example, even when a surge of about 100 mA flows in from the output terminal 54, the occurrence of latch-up can be suppressed.

(Ninth Embodiment) Next, a semiconductor device according to a ninth embodiment will be described with reference to FIG. FIG. 11A is a top view of relevant parts for explaining the semiconductor device according to the ninth embodiment. Incidentally, FIG. 11 (A)
Then, in order to show the arrangement relationship of the diffusion region in the plane pattern, the wiring and the like on the substrate are not shown. Also, FIG.
11B is a schematic cross-sectional view taken along the line AA in FIG. 11A. Note that in FIG. 11B, a wiring and a parasitic circuit are shown in addition to the diffusion region. Further, FIG. 11C is a schematic cross-sectional view taken along the line BB of FIG. 11A.

In FIG. 11, constituent elements corresponding to those of the semiconductor device according to the first embodiment are designated by the same reference numerals. Further, the components and the parasitic circuit given the same reference numerals as those in the first embodiment operate similarly to those in the first embodiment, and thus detailed description thereof will be omitted.

In the semiconductor device of the ninth embodiment, the latch-up protection element 84 is provided around the output circuit 82 so as to surround the output circuit 82 when viewed in a plan pattern.

As a result, according to the ninth embodiment, in each of the above-described embodiments, a surge current slightly flowing from the output circuit 82 to the P-type substrate 10 (fourth embodiment in the first embodiment). Collector current i _{4 of} parasitic Tr108
(Corresponding to the above) can be taken out by the protection element 84 which is grounded so as to surround the output circuit 82. Therefore, the surge current flowing to the internal circuit 12 can be suppressed. As a result, fluctuations in the substrate potential V _BB around the output circuit 82 and the protection element 84 can be suppressed. Therefore, the occurrence of latch-up can be further suppressed.

In addition, in the ninth embodiment, the N well 86 of the output circuit 82 and the first diffusion region 96 of the protection element 84 are shared by one N well. In addition, the fourth diffusion region 102 of the protection element 84 also serves as the fifth diffusion region 196 described in the above-described seventh embodiment. Therefore, the area occupied by the protection element can be reduced without lowering the latch-up resistance.

(Tenth Embodiment) Next, a semiconductor device according to a tenth embodiment will be described with reference to FIG. FIG. 12A is a top view of relevant parts for explaining the semiconductor device according to the tenth embodiment. Note that in FIG. 12A, wiring and the like on the substrate are not shown in order to show the positional relationship in the plane pattern of the diffusion region. 12B is a schematic cross-sectional view taken along the line AA of FIG. 12A. Note that in FIG. 12B, wirings and parasitic circuits are shown in addition to the diffusion region. Further, (C) of FIG. 12 is BB of (A) of FIG.
It is a cross-sectional schematic diagram in the cut along the line.

In FIG. 12, the same components as those of the semiconductor device according to the second embodiment are designated by the same reference numerals. Further, the constituent components and the parasitic circuits given the same reference numerals as those in the second embodiment operate similarly to those in the second embodiment, and thus detailed description thereof will be omitted.

In the semiconductor device of the tenth embodiment, the latch-up protection element 126 is provided around the output circuit 124 so as to surround the output circuit 124 when viewed in a plan pattern.

As a result, according to the tenth embodiment,
In each of the above-described embodiments, a slight surge current (second surge current) flowing from the output circuit 124 to the N-type substrate 120 is used.
(Corresponding to the collector current i ₄ of the fourth parasitic Tr 176 in the above embodiment) can be drawn by the protection element 126 that is grounded so as to surround the output circuit 124. Therefore, the surge current flowing to the internal circuit 122 can be suppressed. As a result, fluctuations in the substrate potential V _BB around the output circuit 124 and the protection element 126 can be suppressed. Therefore, the occurrence of latch-up in the internal circuit 122 can be further suppressed.

In addition, in the tenth embodiment, the P well 148 of the output circuit 124 and the first protection element 126 of the protection circuit 126 are provided.
The diffusion region 158 is shared by one P well. In addition, the fourth diffusion region 164 of the protection element 126 also serves as the fifth diffusion region 202 described in the above-described eighth embodiment. Therefore, the area occupied by the protection element can be reduced without lowering the latch-up resistance.

In each of the above-described embodiments, these inventions have been described only with respect to examples in which a particular material is used and are constructed under a particular condition. However, many modifications and variations can be made to these inventions. For example, in the above-described embodiment, the fourth diffusion region is provided so as to surround the entire periphery of the first diffusion region. However, in the present invention, the fourth diffusion region necessarily surrounds the entire periphery of the first diffusion region. Need not be provided, and may be provided in, for example, a U-shape when viewed in a plane pattern.

[0133]

According to the semiconductor device of the present invention, the latch-up prevention protection element is provided in parallel with the output circuit, and the SCR formed of the parasitic bipolar transistor is formed in the latch-up prevention protection element. Surge to the power supply line or ground line. As a result, the surge flowing into the internal circuit can be reduced and the occurrence of latch-up can be suppressed.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a semiconductor device according to a first embodiment;

FIG. 2 is a plane pattern used for description of the semiconductor device of the first embodiment.

FIG. 3 is a schematic cross-sectional view for explaining a semiconductor device according to a second embodiment;

FIG. 4 is a schematic sectional view for explaining a semiconductor device according to a third embodiment.

FIG. 5 is a schematic sectional view for explaining a semiconductor device according to a fourth embodiment.

6A and 6B are schematic circuit diagrams provided for explaining a semiconductor device according to a fifth embodiment.

7A and 7B are schematic circuit diagrams provided for explaining a semiconductor device according to a sixth embodiment.

FIG. 8 is a schematic sectional view for explaining a semiconductor device according to a seventh embodiment.

FIG. 9 is a plane pattern used for explaining a semiconductor device according to a seventh embodiment.

FIG. 10 is a schematic sectional view for explaining a semiconductor device according to an eighth embodiment.

11A and 11B are diagrams for explaining a semiconductor device according to a ninth embodiment, in which FIG. 11A is a plane pattern, and FIGS. 11B and 11C are schematic sectional views of FIG.

12A and 12B are diagrams for explaining a semiconductor device according to a tenth embodiment, in which FIG. 12A is a plane pattern, and FIGS. 12B and 12C are schematic sectional views of FIG.

FIG. 13 is a schematic sectional view for explaining a semiconductor device of Comparative Example 1.

FIG. 14 is a schematic sectional view for explaining a semiconductor device of Comparative Example 2;

[Explanation of symbols]

10: P-type substrate 12: CMOS internal circuit 14: CMOS output circuit 16: P-type MOS transistor (PMOSTr) 18: N well 20: Source 22: Drain 24: N-type high concentration impurity diffusion region (n +) 26: N Type MOS transistor (NMOSTr) 28: Gate electrode 30: Source 32: Drain 34: P-type high-concentration impurity diffusion region (p +) 36: P-type MOS transistor (PMOSTr) 38: N well 40: Source 42: Drain 46: N-type MOS transistor (NMOSTr) 50: Source 52: Drain 54: Output terminal 58: P-type high-concentration impurity diffusion region (p +) 60: N-type high-concentration impurity diffusion region (n +) 62: N-type impurity diffusion region 64: a first parasitic transistor (first parasitic Tr) 66: well resistor (R ₁₎ 8: second parasitic transistor (second parasitic Tr) 70: substrate resistance (R ₂₎ 72: third parasitic transistor (third parasitic Tr) 74: fourth parasitic transistor (fourth parasitic Tr) 76: fifth parasitic transistor (Fifth Parasitic Tr) 78: Sixth Parasitic Transistor (Sixth Parasitic Tr) 80: Substrate Potential Generation Circuit 82: PMOS Output Circuit 84: Latch-up Prevention Protective Device 86: N Well 88: Source 90: Drain 92: N Type High-concentration impurity diffusion region (n +) 94: P-type high-concentration impurity diffusion region (p +) 96: First diffusion region (N well) 98: Second diffusion region (n +) 100: Third diffusion region (p +) 102: fourth diffusion region (N well) 104: N-type high-concentration impurity diffusion region 106: third parasitic transistor (third parasitic Tr) 108: fourth parasitic transistor (fourth) Raw Tr) 110: Fifth parasitic transistor (fifth parasitic Tr) 112: Sixth parasitic transistor (sixth parasitic Tr) 114: Field oxide film 120: N type substrate 122: CMOS internal circuit 124: CMOS output circuit 126: Latch Up-protection device 128: N-type MOS transistor (NMOSTr) 130: P-well 132: Drain 134: Source 136: P-type high-concentration impurity diffusion region (p +) 138: P-type MOS transistor (PMOSTr) 140: Gate electrode 142 : Drain 144: Source 148: P well 150: N type high concentration impurity diffusion region (n +) 152: Drain 154: Source 156: P type high concentration impurity diffusion region (p +) 158: First diffusion region (P well) ) 160: second diffusion region (p +) 162: third expansion Region (n +) 164: fourth diffusion region (P-well) 166: P-type high-concentration impurity diffusion region (p +) 168: first parasitic transistor (first parasitic Tr) 170: well resistor (R ₁₎ 172: second 2 parasitic transistor (2nd parasitic Tr) 174: 3rd parasitic transistor (3rd parasitic Tr) 176: 4th parasitic transistor (4th parasitic Tr) 178: 5th parasitic transistor (5th parasitic Tr) 180: 6th parasitic Transistor (sixth parasitic Tr) 182: Gate electrode 184: Gate oxide film 186: Output circuit (CMOS transistor) 188: P-type MOS transistor (PMOSTr) 190: N-type MOS transistor (NMOSTr) 192: Pure resistance (R ₃ ) 194: Pure resistance (R ₄ ) 196: Fifth diffusion region (N well) 198: Seventh parasitic transistor (No. 7 parasitic Tr) 200: N-type heavily-doped impurity diffusion region (n +) 202: Fifth diffusion region (P well) 204: Seventh parasitic transistor (seventh parasitic Tr) 206: P-type highly-concentrated impurity diffusion region ( p +)

Claims (6)

[Claims] 1. A substrate potential generation circuit for applying a potential to a first conductivity type substrate, an internal circuit, an output circuit for outputting a signal from the internal circuit to an output line, and an internal circuit of the internal circuit. A semiconductor device comprising a latch-up prevention protection element for preventing latch-up, wherein the latch-up prevention protection element includes a first power supply line and a second power supply line to which different potentials are applied. A second conductive type first diffusion region connected to the output circuit in parallel and provided on the substrate, and an impurity concentration higher than the first diffusion region provided on the first diffusion region. A second conductivity type second having an impurity concentration
A diffusion region, a third diffusion region of the first conductivity type provided in the first diffusion region and separated from the second diffusion region, and the first diffusion on the substrate around the first diffusion region. A fourth diffusion region of a second conductivity type that is provided so as to be spaced apart from the region and substantially surrounds the first diffusion region when viewed in a plane pattern, wherein the third diffusion region is the output. Connected to a line, the second diffusion region is connected to the first power supply line, the fourth diffusion region is connected to the second power supply line, and is generated by the substrate potential generation circuit. An internal potential generation line to which the applied potential is applied is connected to the substrate outside the latch-up prevention protection element. 2. The semiconductor device according to claim 1, wherein the first diffusion region between the second diffusion region and the third diffusion region.
A semiconductor device comprising a gate electrode of a MOS transistor on a diffusion region. 3. The semiconductor device according to claim 1, wherein the output circuit is provided around the output circuit so as to substantially surround the output circuit, and a pure resistance is provided to the second power supply line. A semiconductor device comprising a fifth diffusion region of the second conductivity type connected via the semiconductor device. 4. The semiconductor device according to claim 1, wherein the output circuit has an electrical resistance higher than that of the latch-up prevention protection element when viewed from an external connection bonding pad connected to the output line. The semiconductor device is characterized in that the output circuit is connected to the output line via a pure resistance element separated from the substrate by an insulating film. 5. The semiconductor device according to claim 4, wherein the output circuit is configured by a CMOS circuit including a first conductivity type MOS circuit and a second conductivity type MOS circuit, Type MOS circuit and the second conductivity type MOS
A semiconductor device characterized in that, of the circuits, a MOS circuit that is a source of injection of a surge that triggers the occurrence of latch-up is connected to the pure resistance element. 6. The semiconductor device according to claim 1, wherein the latch-up prevention protection element is provided around the output circuit so as to surround the output circuit when viewed in a plan pattern. Semiconductor device.