JPH11111838A - Isolation of trench element using silicon-rich silicon nitride film - Google Patents
Isolation of trench element using silicon-rich silicon nitride filmInfo
- Publication number
- JPH11111838A JPH11111838A JP10130370A JP13037098A JPH11111838A JP H11111838 A JPH11111838 A JP H11111838A JP 10130370 A JP10130370 A JP 10130370A JP 13037098 A JP13037098 A JP 13037098A JP H11111838 A JPH11111838 A JP H11111838A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride film
- trench
- film
- rich silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 55
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 14
- 239000010703 silicon Substances 0.000 title claims abstract description 14
- 238000002955 isolation Methods 0.000 title description 20
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910007277 Si3 N4 Inorganic materials 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の素子分
離方法に係り、特にマスクパターンとしてシリコン窒化
膜を使用する半導体装置のトレンチ素子分離方法に関す
る。The present invention relates to a device isolation method for a semiconductor device, and more particularly to a trench device isolation method for a semiconductor device using a silicon nitride film as a mask pattern.
【０００２】[0002]
【従来の技術】半導体装置が高集積化され微細化される
につれ、素子間を分離する素子分離領域の縮少は重要な
問題になってきている。素子分離領域の形成は半導体製
造のためのすべての工程中初期段階の工程に該当するこ
とで、活性領域の大きさ及び後工程段階の工程マージン
を左右する。2. Description of the Related Art As a semiconductor device is highly integrated and miniaturized, reduction of an element isolation region for isolating elements has become an important problem. The formation of the element isolation region corresponds to an early stage of all processes for manufacturing a semiconductor, and thus determines the size of an active region and a process margin in a later process.
【０００３】一般的に、半導体装置の製造に広く利用す
るＬＯＣＯＳ（Local Oxidation ofSilicon）による素
子分離方法は工程が簡単であるという利点を有するが、
２５６Ｍ ＤＲＡＭ級以上の高集積半導体装置において
は、素子分離の幅が減少することにより酸化工程時に隨
伴するバーズビーク（bird's beak）によるパンチスル
ー（punch-through）とフィールド酸化膜の厚さ減少な
どの問題点によってその限界に至っている。In general, an element isolation method by LOCOS (Local Oxidation of Silicon) widely used in the manufacture of semiconductor devices has an advantage that the process is simple.
In a highly integrated semiconductor device of 256M DRAM class or higher, the width of element isolation is reduced so that punch-through due to bird's beak and thickness reduction of a field oxide film accompanying the oxidation process are reduced. Problems have reached their limits.
【０００４】前記のようなＬＯＣＯＳ方法での問題点を
解決するために、トレンチ素子分離方法が提案された。
トレンチ素子分離方法はＬＯＣＯＳ方法とは異なり熱酸
化工程を利用しないので、熱酸化工程により誘発される
問題をある程度減らすことができる。また、シリコン基
板にトレンチを形成した後その内部を酸化膜などのよう
な絶縁物質で充填することによって、一定の素子分離幅
内でより効果の良い素子分離深さを持つことができ、素
子分離領域をＬＯＣＯＳ方法より小さくできる。In order to solve the problems of the LOCOS method, a trench isolation method has been proposed.
Unlike the LOCOS method, the trench isolation method does not use a thermal oxidation process, so that problems induced by the thermal oxidation process can be reduced to some extent. In addition, by forming a trench in a silicon substrate and then filling the inside with an insulating material such as an oxide film, it is possible to have a more effective element isolation depth within a certain element isolation width. The area can be made smaller than the LOCOS method.
【０００５】トレンチ素子分離方法によって半導体基板
に素子分離領域を形成するために、一般的に半導体基板
上にパッド酸化膜とシリコン窒化膜でなるマスクパター
ンを形成する工程、前記マスクパターンをマスクとして
半導体基板にトレンチを形成する工程、前記トレンチ内
壁に熱酸化膜を形成する工程、前記トレンチ内部を絶縁
物質で埋立する工程、前記トレンチ内部に埋立された絶
縁物質を緻密化するために、約１、０００℃以上の高温
で熱処理する工程をたどるようになる。In order to form an element isolation region in a semiconductor substrate by a trench element isolation method, generally, a step of forming a mask pattern comprising a pad oxide film and a silicon nitride film on a semiconductor substrate, and using the mask pattern as a mask, Forming a trench in the substrate, forming a thermal oxide film on the inner wall of the trench, filling the inside of the trench with an insulating material, and densifying the insulating material filled in the trench by about 1, The process of heat treatment at a high temperature of 000 ° C. or more is followed.
【０００６】しかし、従来の技術でマスクパターンに使
われるシリコン窒化膜は、これを構成するシリコン窒化
物でのシリコンと窒素の組成比が３：４である。このよ
うな組成を持つシリコン窒化膜の屈折率は約１．９〜
２．０、引張応力が１Ｅ１０〜５Ｅ１０ｄｙｎｅ／ｃｍ
2 程度でかなり大きい。したがって、前記のような組成
を持つシリコン窒化膜をマスクパターンとして使用する
時、後続工程でトレンチ内部に埋立された絶縁物質を緻
密化するために高温で熱処理すれば、熱処理が進行され
る間シリコン窒化膜の引張応力によって、パッド酸化膜
下の活性領域でシリコン基板表面が損傷を受けるように
なる。このように、活性領域の表面が損傷を受けるよう
になれば、後続工程でトランジスター製作のために形成
されるゲート酸化膜もその影響を受けるようになって、
結局、ゲート酸化膜の絶縁特性が劣化することとなる。However, the silicon nitride film used for the mask pattern in the conventional technology has a silicon nitride composition ratio of 3: 4 in the silicon nitride constituting the silicon nitride film. The refractive index of the silicon nitride film having such a composition is about 1.9 to
2.0, tensile stress is 1E10-5E10dyne / cm
It is quite large at around 2 . Therefore, when a silicon nitride film having the above composition is used as a mask pattern, a heat treatment is performed at a high temperature to densify the insulating material buried in the trench in a subsequent process. The tensile stress of the nitride film causes the silicon substrate surface to be damaged in the active region below the pad oxide film. As described above, if the surface of the active region is damaged, a gate oxide film formed for manufacturing a transistor in a subsequent process is also affected.
As a result, the insulation characteristics of the gate oxide film deteriorate.
【０００７】[0007]
【発明が解決しようとする課題】本発明の目的は、半導
体基板の活性領域表面が応力により損傷を受けることを
効果的に防止することによって、ゲート酸化膜の絶縁特
性が劣化することを防止できる半導体装置のトレンチ素
子分離方法を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to effectively prevent the surface of an active region of a semiconductor substrate from being damaged by stress, thereby preventing the insulating characteristics of a gate oxide film from deteriorating. An object of the present invention is to provide a trench element isolation method for a semiconductor device.
【０００８】[0008]
【課題を解決するための手段】前記目的を達成するた
め、本発明によるトレンチ素子分離方法では、半導体基
板上にＳｉ−リッチシリコン窒化膜を含むマスク層を形
成する。前記マスク層を形成するために、半導体基板上
にパッド酸化膜とＳｉ−リッチシリコン窒化膜を順に形
成して、これを再び順にパターニングする。前記マスク
層を蝕刻マスクとして前記半導体基板にトレンチを形成
する。前記トレンチの内壁に熱酸化膜を形成する。前記
トレンチ内部及び前記マスク層の上部にトレンチ埋立用
絶縁層を形成する。前記トレンチ埋立用絶縁層を熱処理
する。In order to achieve the above-mentioned object, in a trench element isolation method according to the present invention, a mask layer including a Si-rich silicon nitride film is formed on a semiconductor substrate. In order to form the mask layer, a pad oxide film and a Si-rich silicon nitride film are sequentially formed on a semiconductor substrate, and are sequentially patterned again. A trench is formed in the semiconductor substrate using the mask layer as an etching mask. A thermal oxide film is formed on an inner wall of the trench. An insulating layer for trench filling is formed inside the trench and above the mask layer. The heat treatment is performed on the trench filling insulating layer.
【０００９】前記Ｓｉ−リッチシリコン窒化膜でのシリ
コン含量は、Ｓｉ3 Ｎ4 でのシリコン含量よりさらに大
きい。The silicon content of the Si-rich silicon nitride film is greater than that of Si 3 N 4 .
【００１０】本発明によれば、トレンチ形成のための蝕
刻マスクで使われるシリコン窒化膜としてＳｉ−リッチ
シリコン窒化膜を使用するので、活性領域表面がシリコ
ン窒化膜の応力によって損傷を受けることを防止して、
ゲート酸化膜の絶縁特性が劣化されることを防止でき
る。According to the present invention, since the Si-rich silicon nitride film is used as the silicon nitride film used as the etching mask for forming the trench, the surface of the active region is prevented from being damaged by the stress of the silicon nitride film. do it,
Deterioration of the insulating properties of the gate oxide film can be prevented.
【００１１】[0011]
【発明の実施の形態】図１ないし図５は本発明の望まし
い実施例による半導体装置のトレンチ素子分離方法を説
明するための断面図である。なお、各図において、同一
符号は同一部材又は部分を示す。1 to 5 are cross-sectional views illustrating a method of isolating a trench in a semiconductor device according to a preferred embodiment of the present invention. In the drawings, the same reference numerals indicate the same members or portions.
【００１２】図１を参照すれば、半導体基板１０上にパ
ッド酸化膜１２を成長させて、その上にシリコン含量が
高いシリコン窒化膜（以下、”Ｓｉ−リッチシリコン窒
化膜”と言う）１４を形成する。ここで、前記Ｓｉ−リ
ッチシリコン窒化膜１４を構成するシリコン窒化物にお
けるシリコン含量はＳｉ3 Ｎ4 におけるシリコン含量よ
り大きくて、望ましくは前記Ｓｉ−リッチシリコン窒化
膜１４でのシリコンと窒素の比率（原子比）は１：１で
ある。このような構成を持つＳｉ−リッチシリコン窒化
膜１４は、シリコンの含量が高いため、その屈折率が
２．０以上と高くて、引張応力が１Ｅ１０ｄｙｎｅ／ｃ
ｍ2 以下と小さい。Referring to FIG. 1, a pad oxide film 12 is grown on a semiconductor substrate 10 and a silicon nitride film 14 having a high silicon content (hereinafter referred to as "Si-rich silicon nitride film") 14 is formed thereon. Form. Here, the silicon content of the silicon nitride forming the Si-rich silicon nitride film 14 is greater than the silicon content of the Si 3 N 4 , and preferably, the ratio of silicon to nitrogen in the Si-rich silicon nitride film 14 ( Atomic ratio) is 1: 1. Since the Si-rich silicon nitride film 14 having such a configuration has a high silicon content, its refractive index is as high as 2.0 or more, and its tensile stress is 1E10 dyne / c.
m 2 or less and small.
【００１３】図２を参照すれば、フォトリソグラフィ工
程によって前記Ｓｉ−リッチシリコン窒化膜１４及びパ
ッド酸化膜１２を順にパターニングして、前記半導体基
板１０の活性領域と非活性領域を限定するＳｉ−リッチ
シリコン窒化膜パターン１４Ａ及びパッド酸化膜パター
ン１２Ａを形成する。ここで、前記Ｓｉ−リッチシリコ
ン窒化膜パターン１４Ａ及びパッド酸化膜パターン１２
Ａは、トレンチ形成のための蝕刻工程のマスク層１６を
形成する。また、パッド膜は、具体的に説明すればＳｉ
Ｏ2 膜を示す。本発明において、パッド酸化膜１２はト
レンチ形成のための食刻時ストレスバッファの役割を果
たすとともに、半導体基板の活性領域を保護する役割を
果たすもので、熱酸化工程により形成される。Referring to FIG. 2, the Si-rich silicon nitride film 14 and the pad oxide film 12 are sequentially patterned by a photolithography process to define an active region and an inactive region of the semiconductor substrate 10. A silicon nitride pattern 14A and a pad oxide pattern 12A are formed. Here, the Si-rich silicon nitride film pattern 14A and the pad oxide film pattern 12
A forms a mask layer 16 in an etching process for forming a trench. The pad film is made of Si
2 shows an O 2 film. In the present invention, the pad oxide film 12 serves as a stress buffer at the time of etching for forming a trench and also serves to protect an active region of a semiconductor substrate, and is formed by a thermal oxidation process.
【００１４】図３を参照すれば、前記マスク層１６を蝕
刻マスクとして前記半導体基板１０を乾式蝕刻してトレ
ンチＴを形成する。続いて、前記トレンチＴの内壁に熱
酸化膜２０を成長させる。ここで、熱酸化膜２０は熱酸
化工程（酸素雰囲気で温度を上昇させる）によりトレン
チの側壁を酸化させて得られるＳｉＯ2 膜を意味する。
このように、トレンチの内壁に熱酸化膜２０を形成する
ことは、トレンチの形成時基板の受ける損傷の影響を最
小化し、トレンチの内壁の表面を均一にするためです。
また、熱酸化膜２０により後続工程で受けるストレスに
よる損傷が防止されることもあります。Referring to FIG. 3, the trench T is formed by dry etching the semiconductor substrate 10 using the mask layer 16 as an etching mask. Subsequently, a thermal oxide film 20 is grown on the inner wall of the trench T. Here, the thermal oxide film 20 means an SiO 2 film obtained by oxidizing the side wall of the trench by a thermal oxidation process (raising the temperature in an oxygen atmosphere).
The formation of the thermal oxide film 20 on the inner wall of the trench is intended to minimize the influence of damage to the substrate when forming the trench and to make the surface of the inner wall of the trench uniform.
In addition, the thermal oxide film 20 may prevent damage due to stress received in a subsequent process.
【００１５】図４を参照すれば、内壁に熱酸化膜２０が
形成された前記トレンチＴ内部及び前記Ｓｉ−リッチシ
リコン窒化膜パターン１４Ａの上部に、トレンチ埋立用
絶縁層３０を形成する。前記絶縁層３０は、例えばＣＶ
Ｄ方法によって形成されたＵＳＧ（Undoped Silicate G
lass）膜で形成する。続いて、前記絶縁層３０を緻密化
させるために前記結果物を１，０００℃以上、例えば
１，０００〜１，２００℃の高温で熱処理する。この
時、前記Ｓｉ−リッチシリコン窒化膜パターン１４Ａは
引張応力が小さいので、前記のような高温熱処理時に前
記Ｓｉ−リッチシリコン窒化膜パターン１４Ａの下にお
ける前記半導体基板１０の活性領域表面が損傷を受けな
いようになる。したがって、後続のトランジスター製作
時に形成されるゲート酸化膜の特性の低下を防止でき
る。Referring to FIG. 4, a trench filling insulating layer 30 is formed inside the trench T where the thermal oxide film 20 is formed on the inner wall and above the Si-rich silicon nitride film pattern 14A. The insulating layer 30 is made of, for example, CV
USG (Undoped Silicate G) formed by Method D
lass) formed of a film. Subsequently, the resulting product is heat-treated at a high temperature of 1,000 ° C. or more, for example, 1,000 to 1,200 ° C. in order to densify the insulating layer 30. At this time, since the Si-rich silicon nitride film pattern 14A has a small tensile stress, the surface of the active region of the semiconductor substrate 10 under the Si-rich silicon nitride film pattern 14A is damaged during the high temperature heat treatment. Will not be. Therefore, it is possible to prevent the characteristics of the gate oxide film formed at the time of manufacturing the subsequent transistor from being deteriorated.
【００１６】図５を参照すれば、前記絶縁層３０を前記
Ｓｉ−リッチシリコン窒化膜パターン１４Ａの上面が露
出するまでＣＭＰ（Chemical Mechanical Polishing）
工程を利用して平坦化する。その後、前記マスク層１６
を湿式蝕刻方法によって取り除く。具体的に説明すれ
ば、前記Ｓｉ−リッチシリコン窒化膜パターン１４Ａを
燐酸のような蝕刻液を使用して湿式蝕刻によって取り除
き、ＢＯＥ（Buffered Oxide Etchant）またはフッ酸の
ような酸化膜蝕刻液を使用して前記パッド酸化膜パター
ン１２Ａを取り除くことによって、図５に示すような素
子分離膜３０Ａを形成する。Referring to FIG. 5, the insulating layer 30 is removed by CMP (Chemical Mechanical Polishing) until the upper surface of the Si-rich silicon nitride film pattern 14A is exposed.
Flatten using a process. Then, the mask layer 16
Is removed by a wet etching method. More specifically, the Si-rich silicon nitride film pattern 14A is removed by wet etching using an etching solution such as phosphoric acid and using an oxide film etching solution such as BOE (Buffered Oxide Etchant) or hydrofluoric acid. By removing the pad oxide film pattern 12A, an element isolation film 30A as shown in FIG. 5 is formed.
【００１７】図６は、トレンチ素子分離工程で、トレン
チ形成のためのマスク層を形成するために通常のシリコ
ン窒化膜を使用した場合（■）と、本発明によるＳｉ−
リッチシリコン窒化膜を使用した場合（□）に対し、各
々ＤＲＡＭ製造工程をたどった後に、ゲート酸化膜での
Ｑｂｄ特性を比較して蓄積分布率で示したグラフであ
る。FIG. 6 shows a case where a normal silicon nitride film is used to form a mask layer for forming a trench in a trench element isolation step (■) and a case where a silicon nitride film according to the present invention is used.
This is a graph showing the accumulation distribution ratio by comparing the Qbd characteristics of the gate oxide film after tracing the DRAM manufacturing process for each case where the rich silicon nitride film is used (□).
【００１８】図６の結果から、本発明によってＳｉ−リ
ッチシリコン窒化膜を適用した場合に、ゲート酸化膜の
Ｑｂｄ特性が優秀なことがわかる。これは通常のシリコ
ン窒化膜よりＳｉ−リッチシリコン窒化膜の引張応力が
小さいので、後続の高温熱処理時に半導体基板の活性領
域が応力による損傷を受けなかったためである。したが
って、トレンチ素子分離工程でトレンチ形成のためのマ
スク層において、シリコン窒化膜としてＳｉ−リッチシ
リコン窒化膜を使用すれば、ゲート酸化膜の絶縁特性を
向上させることができる。FIG. 6 shows that the Qbd characteristic of the gate oxide film is excellent when the Si-rich silicon nitride film is applied according to the present invention. This is because the active region of the semiconductor substrate was not damaged by the stress during the subsequent high-temperature heat treatment because the tensile stress of the Si-rich silicon nitride film was smaller than that of the normal silicon nitride film. Therefore, if the Si-rich silicon nitride film is used as the silicon nitride film in the mask layer for forming the trench in the trench element isolation step, the insulation characteristics of the gate oxide film can be improved.
【００１９】[0019]
【発明の効果】前記したように、本発明によれば、トレ
ンチ形成のための蝕刻マスクに使われるシリコン窒化膜
として、高温熱処理時引張応力が小さなＳｉ−リッチシ
リコン窒化膜を使用するので、半導体基板の活性領域表
面がシリコン窒化膜の応力によって損傷されることを根
本的に防止して、後続工程で形成されるトランジスター
でゲート酸化膜の絶縁特性が劣化することを防止でき
る。As described above, according to the present invention, a Si-rich silicon nitride film having a small tensile stress during high-temperature heat treatment is used as a silicon nitride film used as an etching mask for forming a trench. It is possible to fundamentally prevent the active region surface of the substrate from being damaged by the stress of the silicon nitride film, thereby preventing the transistor formed in a subsequent process from deteriorating the insulating characteristics of the gate oxide film.
【００２０】以上、本発明を望ましい実施例を挙げて詳
細に説明したが、本発明は前記実施例に限定されなく、
本発明の技術的思想の範囲内で当分野で通常の知識を持
った者によって多様な変形が可能である。Although the present invention has been described in detail with reference to the preferred embodiments, the present invention is not limited to the above embodiments.
Various modifications can be made by those having ordinary skill in the art without departing from the technical spirit of the present invention.
【図１】本発明の望ましい実施例による半導体装置のト
レンチ素子分離方法の一工程を説明するための断面図で
ある。FIG. 1 is a cross-sectional view illustrating a process of a method for isolating a trench in a semiconductor device according to a preferred embodiment of the present invention.
【図２】本発明の望ましい実施例による半導体装置のト
レンチ素子分離方法の一工程を説明するための断面図で
ある。FIG. 2 is a cross-sectional view illustrating a process of a method of isolating a trench in a semiconductor device according to a preferred embodiment of the present invention;
【図３】本発明の望ましい実施例による半導体装置のト
レンチ素子分離方法の一工程を説明するための断面図で
ある。FIG. 3 is a cross-sectional view illustrating a process of a method of isolating a trench in a semiconductor device according to a preferred embodiment of the present invention;
【図４】本発明の望ましい実施例による半導体装置のト
レンチ素子分離方法の一工程を説明するための断面図で
ある。FIG. 4 is a cross-sectional view illustrating a process of a method for isolating a trench element of a semiconductor device according to a preferred embodiment of the present invention;
【図５】本発明の望ましい実施例による半導体装置のト
レンチ素子分離方法の一工程を説明するための断面図で
ある。FIG. 5 is a cross-sectional view illustrating a process of a method of isolating a trench in a semiconductor device according to a preferred embodiment of the present invention;
【図６】トレンチ素子分離工程でトレンチ形成のための
マスク層形成時通常のシリコン窒化膜を使用した場合
と、本発明にともなうＳｉ−リッチシリコン窒化膜を使
用した場合に対し、各々Ｑｂｄ（charge to breakdow
n）特性を比較したグラフである。FIG. 6 shows Qbd (charge) for a case where a normal silicon nitride film is used when forming a mask layer for forming a trench in a trench element isolation step and a case where a Si-rich silicon nitride film according to the present invention is used. to breakdow
n) A graph comparing characteristics.
１２Ａ…パッド酸化膜パターン １４Ａ…Ｓｉ−リッチシリコン窒化膜パターン １６…マスク層 ３０…絶縁層 ３０Ａ…素子分離膜 12A: Pad oxide film pattern 14A: Si-rich silicon nitride film pattern 16: Mask layer 30: Insulating layer 30A: Element isolation film
Claims (9)
化膜を含むマスク層を形成する段階と、 前記マスク層を蝕刻マスクとして前記半導体基板にトレ
ンチを形成する段階と、 前記トレンチの内壁に熱酸化膜を形成する段階と、 前記トレンチ内部及び前記マスク層の上部にトレンチ埋
立用絶縁層を形成する段階と、 前記トレンチ埋立用絶縁層を熱処理する段階を含むこと
を特徴とするトレンチ素子分離方法。A step of forming a mask layer including a Si-rich silicon nitride film on a semiconductor substrate; forming a trench in the semiconductor substrate using the mask layer as an etching mask; and thermally oxidizing an inner wall of the trench. Forming a film; forming a trench filling insulating layer inside the trench and above the mask layer; and heat-treating the trench filling insulating layer.
板上にパッド酸化膜を成長させる段階と、 前記パッド酸化膜上にＳｉ−リッチシリコン窒化膜を形
成する段階と、 前記Ｓｉ−リッチシリコン窒化膜及びパッド酸化膜を順
にパターニングして前記半導体基板の活性領域と非活性
領域を限定するマスク層を形成する段階を含むことを特
徴とする請求項１に記載のトレンチ素子分離方法。2. The step of forming the mask layer includes growing a pad oxide film on a semiconductor substrate; forming a Si-rich silicon nitride film on the pad oxide film; 2. The method of claim 1, further comprising forming a mask layer defining an active region and a non-active region of the semiconductor substrate by sequentially patterning the film and the pad oxide film.
リコン含量はＳｉ3Ｎ4 でのシリコン含量よりさらに多
いことを特徴とする請求項２に記載のトレンチ素子分離
方法。3. The method of claim 2, wherein the silicon content of the Si-rich silicon nitride film is greater than the silicon content of Si 3 N 4 .
リコンと窒素の比は１：１であることを特徴とする請求
項３に記載のトレンチ素子分離方法。4. The method according to claim 3, wherein a ratio of silicon to nitrogen in the Si-rich silicon nitride film is 1: 1.
によって形成されるＵＳＧ膜であることを特徴とする請
求項１に記載のトレンチ素子分離方法。5. The method according to claim 1, wherein the trench filling insulating layer is a USG film formed by a CVD method.
１，０００〜１，２００℃の温度で行なうことを特徴と
する請求項１に記載のトレンチ素子分離方法。6. The method according to claim 1, wherein the heat treatment of the trench filling insulating layer is performed at a temperature of 1,000 to 1,200 ° C.
絶縁層を前記マスク層の上面が露出される時まで平坦化
する段階と、 前記マスク層を取り除く段階をさらに含むことを特徴と
する請求項１に記載のトレンチ素子分離方法。7. The method of claim 1, further comprising: flattening the trench filling insulating layer until the upper surface of the mask layer is exposed after the heat treatment step; and removing the mask layer. 3. The method for separating a trench element according to item 1.
絶縁層を前記Ｓｉ−リッチシリコン窒化膜の上面が露出
される時まで平坦化する段階と、 前記Ｓｉ−リッチシリコン窒化膜及びパッド酸化膜を順
に取り除く段階をさらに含むことを特徴とする請求項２
に記載のトレンチ素子分離方法。8. A step of flattening the trench filling insulating layer until the upper surface of the Si-rich silicon nitride film is exposed after the heat treatment step, and sequentially removing the Si-rich silicon nitride film and the pad oxide film. 3. The method of claim 2, further comprising the step of removing.
3. The method for separating a trench element according to item 1.
ッド酸化膜の除去は湿式蝕刻によって行なわれることを
特徴とする請求項８に記載のトレンチ素子分離方法。9. The method according to claim 8, wherein the removal of the Si-rich silicon nitride film and the pad oxide film is performed by wet etching.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970049760A KR100238254B1 (en) | 1997-09-29 | 1997-09-29 | Trench isolation method using si-rich silicon nitride film |
| KR97P49760 | 1997-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11111838A true JPH11111838A (en) | 1999-04-23 |
Family
ID=19521912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10130370A Withdrawn JPH11111838A (en) | 1997-09-29 | 1998-05-13 | Isolation of trench element using silicon-rich silicon nitride film |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH11111838A (en) |
| KR (1) | KR100238254B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004040093A (en) * | 2002-07-05 | 2004-02-05 | Samsung Electronics Co Ltd | Soi wafer and method of manufacturing the same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100560288B1 (en) * | 1999-12-24 | 2006-03-10 | 주식회사 하이닉스반도체 | A method for forming isolation layer of semiconductor device |
| KR100703836B1 (en) * | 2005-06-30 | 2007-04-06 | 주식회사 하이닉스반도체 | Method for forming trench type isolation layer in semiconductor device |
-
1997
- 1997-09-29 KR KR1019970049760A patent/KR100238254B1/en not_active IP Right Cessation
-
1998
- 1998-05-13 JP JP10130370A patent/JPH11111838A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004040093A (en) * | 2002-07-05 | 2004-02-05 | Samsung Electronics Co Ltd | Soi wafer and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990027323A (en) | 1999-04-15 |
| KR100238254B1 (en) | 2000-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6228727B1 (en) | Method to form shallow trench isolations with rounded corners and reduced trench oxide recess | |
| US7763523B2 (en) | Method for forming device isolation structure of semiconductor device using annealing steps to anneal flowable insulation layer | |
| US5989978A (en) | Shallow trench isolation of MOSFETS with reduced corner parasitic currents | |
| US5151381A (en) | Method for local oxidation of silicon employing two oxidation steps | |
| US5445989A (en) | Method of forming device isolation regions | |
| JPH113936A (en) | Manufacture of semiconductor device | |
| JPH11233612A (en) | Method of isolating and forming trench of semiconductor device | |
| US6875670B2 (en) | Trench isolation method | |
| US5565376A (en) | Device isolation technology by liquid phase deposition | |
| JP3539483B2 (en) | Method for manufacturing semiconductor device | |
| JP3974286B2 (en) | Shallow trench isolation method | |
| JP3974269B2 (en) | Method for forming trench isolation in semiconductor device | |
| JP4414026B2 (en) | Method for forming STI of semiconductor element | |
| KR0165462B1 (en) | Method of trench isolation | |
| US5891789A (en) | Method for fabricating isolation layer in semiconductor device | |
| JPH11111838A (en) | Isolation of trench element using silicon-rich silicon nitride film | |
| US5804492A (en) | Method of fabricating an isolation region for semiconductor device | |
| US6303467B1 (en) | Method for manufacturing trench isolation | |
| KR100381849B1 (en) | Trench isolation method | |
| JPH1070117A (en) | Method for forming field oxide film | |
| JP3844896B2 (en) | Semiconductor device isolation structure and method of forming the same | |
| US20020090797A1 (en) | Method for protecting insulation corners of shallow trenches by oxidation of poly silicon | |
| KR100242385B1 (en) | Method of forming an element isolation region in a semiconductor device | |
| US6197662B1 (en) | Semiconductor processing method of forming field isolation oxide using a polybuffered mask which includes a base nitride layer on the substrate, and other semiconductor processing methods | |
| JPS6257232A (en) | Isolation device and making thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050802 |