JPH11108996A - Deficiency analyzer for semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a deficiency analyser for a semiconductor element tester which enables speeding up, miniaturization and lowing of costs. SOLUTION: This analyzer is provided with an address pointer 11 to generate and output a first address signal FAD for analyzing the deficiency of a semiconductor logic element, a selector 12 which inputs the first address signal FAD and a second address signal SAD for analyzing the deficiency of a semiconductor memory element and outputs a third address signal TAD as any one of the first address signal FAD and the second address signal SAD according to a mode switching signal MD, and a memory device 13 which inputs the third address signal TAD as address input signal and a deficiency information data signal FDT as data input signal. An address input of the memory device 13 is altered at each time of testing the semiconductor logic element and the semiconductor memory element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analyzer for a semiconductor test device used for failure analysis of a semiconductor logic device and a semiconductor memory device.

[0002]

2. Description of the Related Art In testing a semiconductor logic device, a test signal is sequentially input from a predetermined test input terminal of a semiconductor logic device to be tested using a signal applying tester pin, and each time a test signal is input from a predetermined terminal. Is measured using a signal detection tester, and the measurement results are sequentially collected. Then, a failure analysis of the semiconductor logic element to be tested is performed based on the mode of the applied signal and the mode of the measurement signal measured and collected for each mode of the applied signal.

In testing a semiconductor memory device, a test address signal and a test data signal are applied to a semiconductor memory device to be tested, and a data value read after writing specified data to a specified address is read. Measure,
Collect measurement results for each address value. Then, based on the write data and the read data at each memory address, a failure analysis of the semiconductor memory element to be tested is performed.

A semiconductor testing device used for analyzing a failure of a semiconductor device includes a measuring device which applies a signal to a semiconductor device from a predetermined signal input terminal and measures a signal output from a predetermined signal output terminal. And a failure analysis device for storing and analyzing data measured by the measurement device.

FIG. 3 is a configuration diagram of a conventional failure analysis device for a semiconductor test device. As shown in FIG. 3, the failure analysis device 20 includes (a) an address pointer 21 for generating and outputting a first address signal FAD for failure analysis of a semiconductor logic element, and (b) a first address signal FAD. A fail log memory 22 that inputs as an address input signal and inputs a failure information data signal FDT from a measuring device (not shown) as a data input signal, and (c) receives a failure information data signal FDT and responds to a selection instruction signal MDS A selector 23 for selecting arbitrary failure information data and outputting a signal SDT; and (d) a second address signal indicating a test memory address of the semiconductor memory device to be tested, which is used for failure analysis of the semiconductor memory device. An analysis memory 24 for inputting the SAD as an address input signal and inputting the signal SDT as a data input signal;

In this device 20, when the test object is a semiconductor logic element, the failure information data is stored in the fail log memory 22 by the first address signal FAD and the failure information data FDT, and the test object is the semiconductor memory element. In this case, the failure information data is stored in the analysis memory 24 by the second address signal SAD and the signal SDT.

[0007] At the time of failure analysis of the semiconductor logic element, failure analysis is performed using the fail log memory 22, and at the time of failure analysis of the semiconductor memory element, failure analysis is performed using the analysis memory 24. I was

[0008]

Since the conventional failure analyzer of a semiconductor test apparatus is configured as described above, an analysis memory for analyzing a failure of a semiconductor memory element and a failure analysis apparatus for analyzing a failure of a semiconductor logic element are provided. A separate fail log memory is required, and it has been difficult to increase the speed, reduce the size, and reduce the cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has as its object to provide a failure analysis apparatus for a semiconductor test apparatus that can be operated at high speed, reduced in size, and reduced in cost.

[0010]

In order to achieve the above object, the present invention employs a system in which a memory device for a semiconductor logic device and a memory device for failure analysis of a semiconductor memory device are shared. .

That is, the defect analyzer for a semiconductor test device according to the present invention comprises: (a) an address pointer for generating and outputting a first address signal for defect analysis of a semiconductor logic element; and (b) a first address signal. A selector for receiving a second address signal for analyzing a failure of the semiconductor memory element and outputting a third address signal reflecting one of the first address signal and the second address signal in response to a mode switching signal; , (C) a memory device that inputs a third address signal as an address input signal and receives a failure information data signal as a data input signal.

According to the defect analyzer for a semiconductor test device of the present invention, at the time of testing a semiconductor logic element, the mode switching signal is set to a logic test mode value and the first signal is stored in the memory device.
A dress signal is supplied, and failure information data in a test of the semiconductor logic element is stored in the memory device. Also,
When testing the semiconductor memory device, the mode switching signal is set as a memory test mode value, a second address signal is supplied to the memory device, and the failure information data in the test of the semiconductor memory device is stored in the memory device.

The same memory device is used for the failure analysis of the semiconductor logic element and the failure analysis of the semiconductor memory element, and the failure analysis is performed.

In the failure analysis apparatus for a semiconductor test apparatus according to the present invention, the failure information data can be raw measurement value data from the semiconductor element to be tested, but the raw measurement value data from the semiconductor element to be tested can be used. It is also possible to use the result of comparison between the data and the expected value data.

When the defect information data is the result of comparison between the raw measurement value data and the expected value data, the defect information data stored in the memory device is assumed to be compressed as compared with the case where the raw measurement data is obtained. be able to.

Further, in the failure analysis device for a semiconductor test device according to the present invention, the address pointer can be suitably provided with an up counter.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor test failure analyzing apparatus according to an embodiment of the present invention;

FIG. 1 is a schematic block diagram of an embodiment of a semiconductor test failure analysis apparatus according to the present invention. As shown in FIG. 1, the device 10 includes (a) an address pointer 11 for generating and outputting a first address signal FAD for failure analysis of a semiconductor logic element, and (b) a first address signal FAD.
And a second address signal S for failure analysis of the semiconductor memory element
AD as an input, and the first signal is inputted according to the mode switching signal MD.
A selector 12 for outputting a third address signal TAD, which is one of the address signal FAD and the second address signal SAD; and (c) inputting the third address signal TAD as an address input signal, and outputting a failure information data signal FDT. A memory device 13 to be input as a data input signal.

In this embodiment, an up counter with a reset function is employed as the address pointer 11. Therefore, in the failure analysis of the semiconductor logic element, the time order of the failure information and the address order of the memory device can be matched.

In this embodiment, if the value of the mode switching signal MD is "L", the selector 12 outputs the value of the first address signal FAD as the value of the third address signal TAD. If the value of the mode switching signal MD is “H”, the value of the second address signal SAD is output as the value of the third address signal TAD.

Further, in the present embodiment, the result of comparison between the raw measurement value data and the expected value data is adopted as the defect information data, and when the comparison result matches (ie, good), the value “0” is set. ”Indicates that the comparison result does not match (ie, is bad)
In this case, the value “1” is the defect information data value.

This device 10 operates as follows.
FIG. 2 is a timing chart for explaining the operation of this device. FIG. 2A is a timing chart at the time of testing a semiconductor logic element, and FIG.
Is a timing chart at the time of testing the semiconductor memory device.

First, the case of failure analysis of a semiconductor logic element will be described. In analyzing the failure of the semiconductor logic element, the mode switching signal MD is set to “L” and supplied to the selector 12. Then, the address pointer 11 is reset, the first address signal FAD is initialized to “0”,
In accordance with the test cycle of the semiconductor logic element by the failure analysis, "+1" is generated to generate the first address signal FAD,
Output to selector 12.

Since the mode switching signal MD is set to "L", the selector 12 selects and outputs the value of the first address signal FAD as the value of the third address signal TAD,
The address input signal of the memory device 13 is used. Then, as the data input to the memory device 13, the defect information data FD
T is supplied.

In this manner, the defect information data value indicating the test result in the test cycle (“0” value when the test result is good, and “0” when the test result is bad) corresponding to the address of the sequential value in each test cycle. Is written to the memory device 13.

At the time of failure analysis of the semiconductor logic element, the contents of the memory device 13 are read out to obtain pass / fail information for each test cycle, and the failure contents are analyzed.

Next, a case of failure analysis of a semiconductor memory device will be described. In analyzing the failure of the semiconductor memory device, the mode switching signal MD is set to “H” to select the selector 12.
To supply.

Since the mode switching signal MD is set to “H”, the selector 12 selects and outputs the value of the second address signal SAD as the value of the third address signal TAD, and outputs the address input of the memory device 13. Signal. Then, the defect information data FDT is supplied as a data input to the memory device 13.

In this way, for each test cycle,
A failure information data value indicating a test result in a test cycle corresponding to an address which is a memory test address value of a semiconductor memory element to be tested (“0” value when the test result is good, and “0” when the test result is bad) Is "1"
Value) is written to the memory device 13.

At the time of failure analysis of the semiconductor memory device, the contents of the memory device 13 are read out to obtain pass / fail information as to which address of the test target semiconductor memory device caused the pass / fail. The content is parsed.

The present invention is not limited to the above embodiment, but can be modified. For example, in the above embodiment, the up counter is used as the address pointer, but another type of element (for example, a down counter) that generates an address value capable of associating the address of the memory device with the test cycle is employed. It is also possible.

If the expected value in each test cycle or memory address is separately managed,
As the failure information data, raw measurement data such as memory read data from a semiconductor element to be tested can be adopted.

[0033]

As described above in detail, according to the failure analysis apparatus for semiconductor testing of the present invention, one memory device for storing failure data for failure analysis is provided for testing semiconductor logic elements. Since the address input of the memory device is changed during the test of the semiconductor memory device and the semiconductor memory device, the semiconductor logic device and the semiconductor device can be used without having a dedicated analysis memory and a dedicated selector for analyzing the failure of the semiconductor memory device. High speed,
The size and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a failure analysis device for a semiconductor test device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining operations of a semiconductor logic element and a semiconductor memory element in the failure analysis device of FIG. 1;

FIG. 3 is a configuration diagram of a conventional failure analysis device for a semiconductor test device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Failure analyzer for semiconductor test equipment 11 Address pointer 12 Selector 13 Memory device

Claims (3)

[Claims] 1. A first method for analyzing a failure of a semiconductor logic element.
An address pointer for generating and outputting an address signal, the first address signal and a second address signal for failure analysis of a semiconductor memory element are input, and the first address signal and the second address signal are input in response to a mode switching signal. A selector that outputs a third address signal reflecting one of the two address signals; and a memory device that receives the third address signal as an address input signal and receives a failure information data signal as a data input signal. A failure analysis device for a semiconductor test device, comprising: 2. The semiconductor test apparatus according to claim 1, wherein the failure information data signal reflects a comparison result between raw measurement value data and expected value data from a semiconductor element to be tested. Failure analysis device. 3. The failure analyzer according to claim 1, wherein the address pointer includes an up counter.