JPH11103168A - Manufacture of multilayered wiring board using insulating resin containing specified oxidation inhibitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayered wiring board having an insulating layer, wherein a microscopic via hole can be formed while the layer maintains heat resistance and insulation reliability in a moistening state. SOLUTION: In a method for manufacturing a wiring board, which is formed into a multilayered structure by a method, wherein an insulating layer 3 is formed on the surface of a first circuit 2 on an insulating board 1 with the first circuit 2 formed thereon, a via hole 6 for connecting the layer 3 with the circuit 2 is formed in the layer 3, second circuits 8 are formed on the surface of the layer 3 by a copper plating and the inter-layer connection of the via hole 6 is made, a photosensitive resin containing a hindered phenol oxidation inhibitor as its essential component or an insulating resin concurrently using photosensitivity and thermosetting is used for the layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to an insulating resin for a multilayer wiring board in which an interlayer insulating layer is formed by a build-up method.

[0002]

2. Description of the Related Art A general multilayer wiring board is formed by laminating a semi-cured material obtained by impregnating a glass cloth called a prepreg with an epoxy resin on a semi-cured state on a copper foil on an insulating substrate having an inner layer circuit formed thereon, and hot-pressing the laminated body. After drilling, a through hole for interlayer connection is drilled, electroless plating is performed on the inner wall of the through hole and the copper foil surface, and electrolytic plating is further performed as necessary to obtain a circuit conductor of a required thickness. Then, unnecessary copper is removed to manufacture a multilayer wiring board. In recent years, the miniaturization, weight reduction, and multifunctionalization of electronic devices have progressed further, and with this, LS
As the degree of integration of ICs and chip components is increasing, the form is rapidly changing to increase the number of pins and reduce the size. In response to these,
In order to improve the mounting density of electronic components, multilayer wiring boards
Development of fine wiring is underway. However, there is a technical limit in reducing the wiring width, and the wiring width that can be mass-produced at present is 75 to 100 μm. For this reason, it is difficult to achieve a significant increase in wiring density simply by reducing the wiring width. A bottleneck for improving the wiring density is a through hole having an area of about 300 μm in diameter. Since the through holes are generally formed by a mechanical drill, the dimensions thereof are relatively large, and therefore, the degree of freedom in wiring design is poor. In order to solve these problems, a method is known in which an insulating resin having photosensitivity is formed on an insulating substrate on which a circuit is formed, and fine via holes are formed in the insulating resin by a photo process to perform interlayer connection. −
These are disclosed in Japanese Patent Application Laid-Open No. 55555 and Japanese Patent Application Laid-Open No. 63-126296.

[0003]

As described above, a multilayer wiring board connected between layers by minute via holes formed by a photo process greatly contributes to the problem of improving the wiring density of a multilayer wiring board which has been conventionally faced. It is. The via hole formed by this photo process is advantageous in that the smaller the diameter, the greater the degree of freedom in wiring design. However, in order to obtain minute via holes, it is necessary to design the insulating layer with a material having increased hydrophilicity. Increasing the hydrophilicity of the resin itself can be easily achieved by adding a hydrophilic group to the resin. However, since increasing the hydrophilicity is the same as increasing the water absorption, it goes without saying that the water absorption properties of the insulating layer, that is, the heat resistance in a humidified state and the insulation reliability are likely to be reduced. Therefore, it is not easy to reduce the diameter of the via hole while maintaining the characteristics as an insulating layer. The present invention is to solve such a point, while maintaining the characteristics required as an insulating layer by adding a specific antioxidant,
The present inventors have found a technique that can easily realize a reduction in the diameter of a via hole.

[0004]

According to the present invention, an insulating layer is formed on a circuit surface of an insulating substrate on which a first circuit is formed, and a via hole for connecting to the first circuit is formed in the insulating layer. In a method of manufacturing a wiring board in which a second circuit is formed on a surface of an insulating layer by copper plating and interlayer connection of via holes is performed to form a multilayer, the insulating layer essentially contains a hindered phenolic antioxidant. A resin or an insulating resin having both photosensitivity and thermosetting properties is used. In the present invention, the hindered phenol-based antioxidant is a compound comprising butylated hydroxyanisole, 2,6-di-t-butyl-4-ethylphenol, 2,2′-methylene-bis (4-methyl-6-t -Butylphenol), 4,4'-thiobis- (3-methyl-6-t-butylphenol), 4,4'-butylidenebis- (3-methyl-6-t
-Butylphenol), 1,1,3-tris (2-methyl-4hydroxy-5-t-butylphenyl) butane, 1,3,5- (4-hydroxybenzyl) benzene, tetrakis- [methylene-3-
The use of at least one selected from the group of (3 ', 5'-di-tert-butyl-4'-hydroxylphenylpropionate) methane is a preferred method for producing a multilayer wiring board.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION The hindered phenolic antioxidant used in the present invention may be used in combination of several kinds. The compounding amount is 0.01 to 100 parts by weight of the insulating resin excluding the antioxidant. ~ 5 parts by weight are preferred. If less than 0.01 parts by weight,
There is no effect in reducing the diameter of the via hole, that is, in improving the resolution. When the content exceeds 5 parts by weight, the photocurability becomes insufficient, so that the insulating properties and solder heat resistance tend to decrease.

The photosensitive resin used in the present invention or the insulating resin having both photosensitivity and thermosetting properties includes a composition containing a copolymer or a monomer having a functional group which can be crosslinked by light, or a composition containing light. In addition, any composition may be used as long as it is a composition in which a thermally crosslinkable functional group and a thermal initiator are mixed. The first group of other resin components that can be used together with the above components include epoxy resins, brominated epoxy resins, rubber-modified epoxy resins, alicyclic epoxy resins such as rubber-dispersed epoxy resins, and bisphenol-A-based resins. Examples include epoxy resins and acid-modified products of these epoxy resins. In particular, when photo-curing is performed by irradiating light, modified products of these epoxy resins and unsaturated acids are preferable. Examples of the unsaturated acid include maleic anhydride, tetrahydrophthalic anhydride, itaconic anhydride, acrylic acid, methacrylic acid and the like. These can be obtained by reacting the unsaturated carboxylic acid with the epoxy group of the epoxy resin in an equivalent amount or a mixing ratio of the equivalent or less. In addition, a thermosetting material such as a melamine resin and a cyanate ester resin is also one of preferable application examples. Another suitable combination is the use of a flexibility-imparting material, such as butadiene acrylonitrile rubber, natural rubber,
Examples include acrylic rubber, SBR, carboxylic acid-modified butadiene acrylonitrile rubber, carboxylic acid-modified acrylic rubber, crosslinked NBR particles, carboxylic acid-modified crosslinked NBR particles, and the like. By adding such various resin components, it becomes possible to impart various properties to the cured product while maintaining basic properties such as photocurability and thermosetting properties.

When a rubber component is compounded, the cured product is given tough properties, and the surface of the cured product can be easily roughened by surface treatment with an oxidizing chemical. In the curable composition using the photosensitive resin of the present invention or the resin combining photosensitivity and thermosetting, commonly used additives (polymerization stabilizer, leveling agent, pigment, dye, etc.) may be used. . There is no problem in adding a filler. As fillers, inorganic fine particles such as silica, fused silica, talc, alumina, hydrated alumina, barium sulfate, calcium hydroxide, aerosil, and calcium carbonate, organic fine particles such as powdery epoxy resin, powdery polyimide particles, and powdery Teflon particles And the like. These fillers may be subjected to a coupling treatment in advance. These dispersions are achieved by known kneading methods such as kneaders, ball mills, bead mills, and three rolls.

Using the insulating layer composition described above, FIG.
The multilayer wiring board is manufactured by the steps shown in (1). This will be described in detail according to the steps shown in FIG. First, an insulating substrate on which a first circuit is formed is prepared (FIG. 1- (a)). This insulating substrate is not particularly limited, and a glass cloth-epoxy resin,
An insulating substrate used for a normal wiring board such as paper-phenol resin, paper-epoxy resin, glass cloth / glass paper-epoxy resin can be used. As a method of forming the first circuit, using a copper-clad laminate obtained by laminating a copper foil and the insulating substrate,
An ordinary wiring board manufacturing method such as a subtractive method of etching and removing unnecessary portions of a copper foil and an additive method of forming a circuit by electroless plating at a necessary portion of the insulating substrate can be used. Next, the insulating layer is formed on the circuit surface on which the first circuit is formed (FIG. 1).
(B)). As a forming method, a method in which a liquid resin is applied by a method such as roll coating, curtain coating, or dip coating, or a method in which the insulating resin is formed into a film and bonded by lamination can be used. Next, the insulating layer is exposed through a photomask to form a via hole connected to the first circuit (FIG. 1- (c)), and the unexposed portion is etched by a developing solution. A via hole connecting to the first circuit is formed in the layer (FIG. 1)
(D)). Exposure is performed using the same method as that for forming a normal wiring board resist. Further, the developing solution for etching the unexposed portion with a developing solution is determined depending on the type of development of the resin composition used for the insulating layer, and includes an alkali developing solution, a semi-aqueous developing solution, and a solvent developing solution. For example, a general one can be used. Next, after treating the insulating layer with an oxidizing roughening solution, copper plating is deposited on the insulating layer to form a second circuit and connect via holes between layers (FIG. 1).
(E)). In this case, it is also possible to use a method in which the insulating layer is cured with ultraviolet light or ultraviolet light and heat and then immersed in an oxidizing roughening liquid. As the oxidizing roughening solution, a roughening solution of chromium / sulfuric acid, a roughening solution of alkali permanganate, a roughening solution of sodium fluoride / chromium / sulfuric acid, a roughening solution of borofluoric acid, or the like can be used. Further, as a method of forming the second circuit, a catalyst for electroless plating is applied to the surface of the roughened insulating layer to deposit electroless plated copper on the entire surface, and if necessary, a circuit conductor is formed by electrolytic plating. To the required thickness,
A method of forming by removing unnecessary portions by etching, a method of forming a plating resist using an insulating layer containing a plating catalyst, and forming a circuit by electroless plating only at necessary portions, and an insulating layer containing no plating catalyst And a method of forming a plating resist after applying a plating catalyst and forming a circuit by electroless plating only at a necessary portion. When the present invention is multi-layered, the above method (FIG. 1- (b) to FIG. 1- (e)) is repeated to form a multi-layer (step: FIG. 1- (f) to FIG. 1- (h)). ). At this time, preferably, before forming an insulating layer for supporting the next circuit layer, the surface of a circuit layer conductor thereunder is roughened to form irregularities, or a circuit is used as in a conventional multilayer wiring board. Irregularities can be formed by oxidizing the surface of the layer conductor, or the irregularities formed by oxidation can be reduced using an alkaline reducing agent such as sodium borohydride or dimethylamine borane to increase the adhesion between the layers.

The present invention relates to a method for producing a wiring board in which a specific additive is added to a resin composition for an insulating layer to form a multilayer structure by a build-up method capable of reducing the diameter of a via hole required for interlayer connection. A multilayer wiring board excellent in high density can be provided. Hereinafter, the present invention will be described specifically with reference to Examples.

[0010]

【Example】

(Example 1) (1) MCL-E-67 which is a copper-clad glass cloth epoxy resin laminate having 18 μm double-sided roughened foil adhered to both sides.
An unnecessary portion of the copper foil was removed by etching using (trade name of Hitachi Chemical Co., Ltd.) to form a first circuit (shown in FIG. 1- (a)). (2) On one side of this surface, an insulating resin having the following composition was applied using a roll coater and dried at 80 ° C. for 10 minutes to form an insulating layer having a thickness of 50 μm (shown in FIG. 1- (b)). . 70% by weight of phthalic acid-modified novolak epoxy acrylate (R-5259: Nippon Kayaku Co., Ltd.) 10 parts by weight of carboxylic acid-modified butadiene (Hiker CTBN1300 × 13: Ube Industries, Ltd.) Novolak-type Br-epoxy resin (BREN-S: trade name, manufactured by Nippon Kayaku Co., Ltd.) 15 parts by weight Photoinitiator (Irgacure 651: trade name, manufactured by Ciba Geigy Corporation) 5 parts by weight Filler, aluminum hydroxide ( Heidilite H-42M: trade name, manufactured by Showa Denko KK 10 parts by weight ・ 0.5 parts by weight of 4,4'-butylidenebis- (3-methyl-6-t-butylphenol) (3) In a portion to be a via hole through a photomask to form a shield portion, and irradiated with ultraviolet light exposure amount 300 mJ / cm ² (shown in FIG. 1- (c)), a further unexposed portions, 2,2 Bed Butoxyethanol and 10 vol%, to form a via hole to a 30 ° C. -1 min spraying with containing 4 sodium borate 8 g / l developer. (4) Post-exposure was performed by irradiating the insulating layer with ultraviolet rays at ² J / cm ² . (5) Heating was performed at 150 ° C. for one hour. (6) In order to chemically roughen the insulating layer, K
An aqueous solution of MnO ₄ : 60 g / l and NaOH: 40 g / l is prepared, heated to 50 ° C., and immersed for 5 minutes. KM
After immersion in nO ₄ , SnCl ₂ : 30 g / l, HCl:
It was neutralized by immersion treatment in a 300 ml / l aqueous solution at room temperature for 5 minutes to form a roughened uneven shape (shown in FIG. 1- (d)). (7) In order to form a second circuit on the surface of the first insulating layer, first, a catalyst for electroless plating containing PdCl ₂ , HS-202B (trade name, manufactured by Hitachi Chemical Co., Ltd.)
After immersion treatment at room temperature for 10 minutes, washing with water, immersion in an L-59 plating solution (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is electroless copper plating at 70 ° C. for 30 minutes, and further performing copper sulfate electrolytic plating, A conductor layer having a thickness of 20 μm was formed on the surface of the insulating layer. Next, an etching resist is formed to remove unnecessary portions of the plated conductor by etching, etching is performed, and then the etching resist is removed to form a second circuit including a via hole connected to the first circuit. (Shown in FIG. 1- (e)). (8) Further, in order to form a multilayer, the surface of the second circuit conductor is made of sodium chlorite: 50 g / l, NaOH: 20
g / l, trisodium phosphate: 8 in 10 g / l aqueous solution
It was immersed at 5 ° C. for 20 minutes, washed with water, and dried at 80 ° C. for 20 minutes to form copper oxide irregularities on the surface of the second circuit conductor. (9) The steps (2) to (8) were repeated to produce a three-layer multilayer wiring board (shown in FIGS. 1- (f) to 1- (h)).

(Example 2) Instead of 4,4'-butylidenebis- (3-methyl-6-t-butylphenol) in Example 1, 1,1,3-tris (2-methyl-4-hydroxy- 5-t-
(Butylphenyl) butane was added in an amount of 0.5 part by weight. Otherwise, the procedure was the same as in Example 1.

Example 3 Instead of 4,4'-butylidenebis- (3-methyl-6-t-butylphenol) in Example 1, tetrakis- [methylene-3- (3 ', 5'-di- t-butyl-4'-hydroxylphenylpropionate].
5 parts by weight were blended. Otherwise, the procedure was the same as in Example 1.

Comparative Example 1 A multilayer wiring board was produced in the same manner as in Example 1, except that 4,4'-butylidenebis- (3-methyl-6-t-butylphenol) was not blended. did.

Table 1 shows the characteristics of the multilayer wiring board manufactured as described above. In addition, the measurement was performed as follows. Via-hole resolution: The via-hole formed portion of the substrate exposed and developed using a photomask having a different via-hole diameter is observed by using a metallographic microscope and a scanning electron microscope to observe the resin residue and the via-hole shape at the bottom of the via-hole. evaluated. The minimum diameter at which a via hole having no resin residue at the bottom of the via hole and without peeling or dent was formed was defined as via hole resolution. Peel strength: 9 plated copper according to JIS C6481
The adhesive strength when peeled at a width of 10 mm in the 0 degree direction was determined. 288 ° C. solder heat resistance: 3 prepared in Examples and Comparative Examples
The multilayer wiring board having the layers was cut into 25 mm, floated in a solder bath adjusted to 288 ± 1 ° C. for 60 seconds, and examined for occurrence of abnormalities such as blistering. Those with blisters and the like were evaluated as "good" and those without blisters were evaluated as "no". 260 solder heat resistance (40 ° C-90% RH 2 days treatment):
The multilayer wiring board of three layers produced in the example and the comparative example is 25 m
m, and placed in a thermo-hygrostat adjusted to 40 ° C. and 90% RH for 2 days. After the treatment, it was left at room temperature for 1 hour, and then examined for the occurrence of abnormalities such as blistering in a solder bath adjusted to 260 ± 1 ° C. for 30 seconds. Those with blisters and the like were evaluated as "good" and those without blisters were evaluated as "no". Interlayer insulation resistance: Leads are respectively taken out of the first circuit and the second circuit by soldering, and the first circuit and the second circuit are separated at room temperature.
Was measured when a DC voltage of 100 V was applied between the circuits for 1 minute.

[0015]

[Table 1] Item Example 1 Example 2 Example 3 Comparative Example 1 Wirehole resolution (diameter, mm) 0.08 0.09 0.08 0.15 Peel strength (KN / m) 1.0 0.9 1.0 1.1 288 ° C Soldering heat resistance (normal state, 60 seconds) None No No No 260 ° C solder heat resistance (30 seconds) No No No No (40 ° C-90% RH-2 days treatment) Interlayer insulation resistance (Ω) 10 ¹² or more 10 ¹² or more 10 ¹² or more 10 ¹² or more

From Table 1, it can be seen that Examples 1 to 3 in which a hindered phenolic antioxidant is blended with the photosensitive resin of the present invention or a resin having both photosensitivity and thermosetting properties are Comparative Examples containing no antioxidant. 1 is superior in resolution of the via hole. Despite the addition of the hindered phenolic antioxidant, no heat resistance at 288 ° C., no solder heat resistance after two days of treatment at 40 ° C.-90% RH, and no interlayer insulation resistance Comparative Example 1 is equal to or more than that of Comparative Example 1, and other characteristics are not deteriorated.

[0017]

As described above, by using the insulating resin composition of the present invention, it was possible to provide a build-up type multilayer wiring board excellent in forming small-diameter via holes.

[Brief description of the drawings]

FIGS. 1A to 1H are cross-sectional views illustrating the present invention.

[Explanation of symbols]

 1. 1. Insulating substrate 2. First circuit First insulating layer 4. Photomask 5. UV rays 6. Via hole 61. Via hole 7. Roughened surface 71. Roughened surface 8. Second circuit 9. Second insulating layer 10. Third circuit

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Shuichi Hatakeyama 1500 Odai Ogawa, Shimodate City, Ibaraki Prefecture Inside the Shimodate Research Laboratory, Hitachi Chemical Co., Ltd. (72) Inventor Hiroyuki Fukai 1500 Odai Ogawa Shimodate City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Inside the Shimodate factory

Claims (2)

[Claims] An insulating layer is formed on a circuit surface of an insulating substrate on which a first circuit is formed, a via hole for connecting the first circuit to the insulating circuit is formed on the insulating layer, and the insulating layer surface is formed by copper plating. In the method for manufacturing a wiring board in which a second circuit is formed and a via hole is connected between layers to form a multilayer, the insulating layer is made of a photosensitive resin containing a hindered phenol-based antioxidant or a photosensitive and thermosetting resin. A method for manufacturing a multilayer wiring board, characterized by using an insulating resin which is used in combination with the above. 2. The hindered phenolic antioxidant comprises:
Butylated hydroxyanisole, 2,6-di-t-butyl-4-ethylphenol, 2,2'-methylene-bis (4-methyl-6-t-t-
Butylphenol), 4,4'-thiobis- (3-methyl-6-t
-Butylphenol), 4,4'-butylidenebis- (3-methyl-6-t-butylphenol), 1,1,3-tris (2-methylphenol
-4 hydroxy-5-t-butylphenyl) butane, 1,3,5-
(4-hydroxybenzyl) benzene and at least one selected from the group consisting of tetrakis- [methylene-3- (3 ', 5'-di-tert-butyl-4'-hydroxylphenylpropionate] methane. 2. The method for producing a multilayer wiring board according to 1.