JPH1098496A - Packet transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deviation of phases between a preample signal and the clock of packet data by starting the generation of packet data at timing after the lapse of fixed time from an end preanounce signal and changing over a switch circuit so as to output this signal from a packet transmission circuit to the outside in place of the preample signal. SOLUTION: A preample signal generation circuit 1 outputs a preample signal (a) to a switch circuit 3 and a controller 4 dispatches data b' for transmission to an IC 2 dedicated to packet generation so as to output the data b' for transmission as packet data based on a communication protocol to be used for this packet transmission circuit. Besides, the controller 4 sends a preample output control signal (g) to the preample generation circuit 1 and inverts a switching control signal (e) to the switch circuit 3 again. Thus, the preample signal (a) to be added to the head of the next packet data can be generated by the preample generation circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet transmitting circuit for adding a preamble signal for bit synchronization to the head of packet data and outputting the packet data. That is, the present invention relates to a circuit for transmitting packet data to a single wired or wireless line having no clock transmission line.

[0002]

2. Description of the Related Art In a packet communication system, HDLC is used.
Communication control conforming to a communication protocol such as (High level Data Link Connection) is performed. Further, a transmitter used in a packet communication system may include a dedicated IC for processing data to be transmitted and generating packet data according to the communication protocol.

In a packet communication system, when communication is performed using a single line without providing a line for clock transmission, a data sequence for bit synchronization called a preamble signal (usually a preamble signal) is provided at the beginning of each packet data. Is "1010.
・ ・ ”) Is added. This preamble signal is generated from, for example, the dedicated IC.

[0004]

There is a demand to generate the preamble signal and the packet data by separate IC circuits. That is, there is a demand that the dedicated IC is configured as an IC dedicated to packet data generation, and the preamble signal is generated from another IC. This is because the circuit configuration of the IC for generating the packet data can be simplified. In addition, if such an IC is used, the number of models that can be incorporated is increased, and the versatility of use is increased.

In a packet sending circuit in which a circuit for generating the preamble signal and an IC for generating the packet data are separately provided, the preamble signal and the packet data following the preamble signal are switched at an accurate timing, and the preamble signal and the packet data are switched. It is necessary to prevent a phase shift from occurring with the data clock. That is, it is necessary to prevent an error in packet data determination on the receiver side due to the phase shift by preventing the phase shift.
An object of the present invention is to prevent the above phase shift.

[0006]

According to the present invention, there is provided a preamble generating circuit for generating a preamble signal for bit synchronization and generating an end notice signal for notifying the end of the preamble signal a predetermined time before the scheduled end time, A packet generation circuit that processes transmission data to generate packet data conforming to a predetermined communication protocol, a switch circuit that switches and outputs one of the preamble signal and the packet data, and an end notice signal. And control means for causing the packet generation circuit to start generating packet data after the elapse of the predetermined time and to switch the output of the switch circuit to the packet data. The fixed time needs to be set in advance, but the value is arbitrary. For example, as in the illustrated device, a time corresponding to one octet (byte: one byte is eight bits in this example) can be adopted. The predetermined communication protocol is, for example, a communication protocol in which frame synchronization is established after bit synchronization is established, such as HDLC.

[0007]

FIG. 1 is a block diagram showing a configuration example of a packet transmission circuit according to an embodiment of the present invention, and FIG. 2 is a chart showing a data sequence shown in FIG. FIG.
Is a preamble generation circuit 1
, A packet generation IC 2, a switch circuit 3, and a controller 4.

The preamble generating circuit 1 generates a preamble signal a for bit synchronization and outputs it to the switch circuit 3. As shown in FIG. 2, the preamble signal a is “1”.
010..., And here, 8
Octets are generated. The preamble signal a is used for extracting the repetition period of the packet data on the receiver side. The bit amount (time) of the preamble signal a needs to be determined in advance, but does not necessarily have to be 8 octets.

As shown in FIG. 2, the preamble generating circuit 1 generates a "one-byte remaining signal c" so that the ungenerated preamble signal "a" falls at a timing when the remaining one byte becomes one. Output to The remaining one-byte signal c corresponds to an “end notice signal” described in claims.

The controller 4 transmits the transmission data b '
The transmission data b 'is passed to the packet generation IC 2 so as to be output as packet data b conforming to the communication protocol (eg, HDLC) used in the packet transmission circuit. Further, it generates a "packet output control signal d" so as to fall at a timing when a time corresponding to one byte elapses from the fall time of the remaining one byte signal c, and outputs it to the packet generation IC2. In response to this, the IC 2 dedicated to packet generation starts outputting the packet data b conforming to the communication protocol.

The controller 4 inverts the "switching control signal e" to the switch circuit 3 at a timing when a time corresponding to one byte elapses from the falling time of the remaining one byte signal c. In response to this, the switch circuit 3 is switched to the output side of the IC 2 dedicated for packet generation, and as shown in FIG. 2, the packet data b is output as an output signal f from the present packet transmission circuit to the outside.

Further, the controller 4 counts the transmission data b 'to be transferred to the packet-generating IC 2 and, when the transmission of transmission data b' (for example, 4096 bytes) corresponding to one packet is completed, the one packet. The preamble output control is performed at the timing when the last bit of the packet data b generated from the corresponding transmission data b 'is output to the outside through the switch circuit 3 (a predetermined timing determined according to the communication protocol used). The signal g is sent to the preamble generation circuit 1, and the "switch control signal e" to the switch circuit 3 is again inverted. As a result, a preamble signal a to be added to the head of the next packet data is generated by the preamble generation circuit 1 and starts to be output to the outside through the switch circuit 3. The end of the packet is known by measuring the time corresponding to the maximum length of one packet determined according to the communication protocol used.
Control for switching to output the preamble signal for the next packet is also possible.

In the above-mentioned circuit, the remaining one-byte signal c is generated by the preamble generating circuit 1 and sent to the controller 4. However, the controller 4 monitors the preamble signal a, and the remaining preamble signal a becomes one. When it is detected that a byte (predetermined time other than 1 byte may be used) is detected, a signal of the remaining 1 byte may be generated accordingly. That is, a circuit for generating a preamble signal for bit synchronization, a means for monitoring the preamble signal and generating an end notice signal a predetermined time before the scheduled end time thereof, and a circuit for processing transmission data and performing predetermined communication. A packet generation circuit for generating packet data conforming to a protocol, a switch circuit for switching and outputting any one of the preamble signal and the packet data, and the packet after a predetermined time elapses when the end notice signal is generated. The packet transmission circuit may include a control unit that causes the generation circuit to start generating packet data and switch the output of the switch circuit to the packet data.

[0014]

According to the packet sending circuit of the present invention, an end notice signal for notifying the end of the preamble signal for bit synchronization is generated a fixed time before the scheduled end time, and the fixed time elapses from the end notice signal. At the timing, the generation of packet data by the packet generation circuit is started, and
Since the switch circuit is switched so as to output the packet data from the present packet sending circuit to the outside instead of the preamble signal, it is possible to prevent a phase shift between the preamble signal and the clock of the packet data. Therefore, it is possible to prevent packet data determination errors on the receiver side due to the phase shift.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a packet transmission circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing each signal shown in FIG. 1;

[Explanation of symbols]

 1 Preamble generation circuit 2 Packet generation IC circuit 3 Switch circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoyuki Yamada 41-cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture Inside Toyota Central Research Institute, Inc. 41, Chuotaku Yokomichi, Toyota Chuo Research Institute, Inc. (72) Inventor Masanori Miyashita 41, Chukaku Yokomichi, Daikaku-cho, Aichi-gun, Aichi, Japan Toyota Motor Central Research Institute Co., Ltd. 1-1 1-1 Showa-cho, Kariya-shi, Nippon Denso Co., Ltd.

Claims (1)

[Claims] 1. A preamble generating circuit for generating a preamble signal for bit synchronization and generating an end notice signal for notifying the end of the preamble signal a predetermined time before an expected end time, and processing data for transmission. A packet generating circuit for generating packet data conforming to a predetermined communication protocol, a switch circuit for switching and outputting any one of the preamble signal and the packet data, and the constant when the end notice signal is generated. Control means for causing the packet generation circuit to start generating packet data after a lapse of time and switching the output of the switch circuit to the packet data.