JPH1098140A - Multiple-chip type semiconductor device - Google Patents

Multiple-chip type semiconductor device

Info

Publication number
JPH1098140A
JPH1098140A JP25120296A JP25120296A JPH1098140A JP H1098140 A JPH1098140 A JP H1098140A JP 25120296 A JP25120296 A JP 25120296A JP 25120296 A JP25120296 A JP 25120296A JP H1098140 A JPH1098140 A JP H1098140A
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
semiconductor
elastic body
common electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25120296A
Other languages
Japanese (ja)
Inventor
Takashi Fukumaki
孝 服巻
Izumi Sakurai
泉 桜井
Noritoshi Ishikawa
文紀 石川
Hironori Kodama
弘則 児玉
Koichi Inoue
広一 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP25120296A priority Critical patent/JPH1098140A/en
Publication of JPH1098140A publication Critical patent/JPH1098140A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To improve the heat radiation effect and electric continuity by inserting an elastic multiple structure for absorbing the height dispersion between semiconductor chips which are different in height and heat radiating member and connecting the chips to the radiating member by a pressing force to contact them to one flat plate en bloc, without arranging their heights. SOLUTION: Semiconductor chips 1a, 1b, 1c, different in height are disposed on an Mo, W or Cu-C composite strain buffer board 2 having a thermal expansion coefficient equal to that of the semiconductor and mounted on a common collector electrode 3. On the semiconductor chips an Mo, W, or Cu-C composite strain buffer board 4, having a thermal expansion coefficient equal to that of the semiconductor, is disposed and covered with an elastic multiple structure 5 for absorbing steps. It is a double structure made of Cu pipes, such that the small-aperture pipe is inserted in the large-aperture one, made flat, with a center hollow space 6 formed in its contral part and connected to a common emitter electrode 7 thereon, allowing simultaneous connections to one common electrode.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、基板上に搭載した
高さの異なる複数の半導体チップに共通の放熱フィンの
作用も兼ね備える共通電極を取り付けることのできるマ
ルチチップ型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip type semiconductor device in which a plurality of semiconductor chips having different heights mounted on a substrate can be provided with a common electrode which also functions as a common radiating fin.

【0002】[0002]

【従来の技術】近年コンピュータシステムの高速化に伴
い、集積回路(IC)パッケージ内に一つの半導体チッ
プのみを搭載するシングルチップ型のパッケージ構造の
ものから、複数の半導体チップを搭載できるマルチチッ
プモジュール構造の半導体装置へ移行しつつある。この
ため、各種のマルチチップモジュール構造が模索され、
開発されているが、複数の半導体チップを直接一つの放
熱材及び電極に密着させようとする場合、複数の半導体
チップについての段差,所謂高さの差をなくすことが重
要である。
2. Description of the Related Art In recent years, with the increase in the speed of computer systems, a multi-chip module capable of mounting a plurality of semiconductor chips from a single-chip type package structure in which only one semiconductor chip is mounted in an integrated circuit (IC) package. It is shifting to a semiconductor device having a structure. For this reason, various multi-chip module structures have been sought.
Although it has been developed, it is important to eliminate a step, that is, a so-called height difference between the plurality of semiconductor chips when the plurality of semiconductor chips are to be directly adhered to one heat radiating material and one electrode.

【0003】従来のマルチチップ型の半導体装置におい
て、複数の半導体チップを、一つの放熱フィンに直接密
着させて放熱を行うには、パッケージがハーメチックタ
イプである場合は、半導体チップと放熱フィンとの間で
ろう材を溶融させて熱伝導を図り、またパッケージがノ
ン・ハーメチックタイプである場合は、半導体チップと
放熱フィンとの間に熱伝導性の良好なシートを挟み、低
抵抗化を図っていた。しかしながら、実際にマルチチッ
プ型の半導体パッケージを製造する場合は、全てのチッ
プの高さを揃える必要があるが、事実上チップの高さは
不均一である。図10は従来の加圧型のマルチチップ型
半導体装置の概略図である。高さの異なる複数の半導体
チップ21a,21b,21cを歪緩衝板22の上に配
置し、それらは共通電極コレクタ23上に搭載する。半
導体チップ21の上には歪緩衝板24が配置されてい
る。従来の段差吸収材となる多重構造弾性体25は半導
体チップ21と歪緩衝板22の間に配置される。この段
差吸収材となる多重構造弾性体25は、はんだ材を適用
している。そして共通電極エミッタ27が上から接続さ
れる。
In a conventional multi-chip type semiconductor device, in order to dissipate heat by directly adhering a plurality of semiconductor chips to one radiating fin, if the package is a hermetic type, the semiconductor chip and the radiating fin must be connected to each other. The brazing material is melted between them to achieve heat conduction. If the package is a non-hermetic type, a sheet with good heat conductivity is sandwiched between the semiconductor chip and the radiating fins to reduce resistance. Was. However, when actually manufacturing a multi-chip type semiconductor package, the heights of all chips need to be uniform, but the heights of the chips are practically non-uniform. FIG. 10 is a schematic view of a conventional pressurized multi-chip semiconductor device. A plurality of semiconductor chips 21 a, 21 b, 21 c having different heights are arranged on a strain buffer 22, and they are mounted on a common electrode collector 23. A strain buffer 24 is disposed on the semiconductor chip 21. A multi-layered elastic body 25 serving as a conventional step absorber is disposed between the semiconductor chip 21 and the strain buffer 22. The multi-structure elastic body 25 serving as the step difference absorbing material uses a solder material. Then, the common electrode emitter 27 is connected from above.

【0004】また半導体チップ21の端部にゲート電極
28を配置し、共通電極コレクタ23上の絶縁板29上
にゲート配線網210を配置する。ゲート電極28とゲ
ート配線網210はワイヤリード211で接続される。
この様に半導体チップ21a,21b,21cを中心として
各部材が搭載され、共通電極コレクタ23と共通電極エ
ミッタ27は絶縁外筒212により固定されている。ま
た、半導体チップの配置は絶縁位置決め板213により
行われる。これが1単位モジュールの形状である。
A gate electrode 28 is disposed at an end of the semiconductor chip 21, and a gate wiring network 210 is disposed on an insulating plate 29 on the common electrode collector 23. The gate electrode 28 and the gate wiring network 210 are connected by a wire lead 211.
As described above, each member is mounted around the semiconductor chips 21a, 21b, and 21c, and the common electrode collector 23 and the common electrode emitter 27 are fixed by the insulating outer tube 212. The semiconductor chips are arranged by the insulating positioning plate 213. This is the shape of one unit module.

【0005】複数の半導体チップ21a,21b,21
cは,図に示すように夫々高さが異なっているで、この
系の材料の中で最も軟らかいはんだ材が多重構造弾性体
25として圧縮される。初期の加圧による各部材の接触
は、はんだ材の変形で良好となる。しかし、半導体装置
は使用したり、停止したりを繰り返す。即ち、使用時に
は半導体チップは発熱して温度が上昇し、また、停止時
には半導体チップは冷却され温度は下がる。つまり、加
熱,冷却が繰り返される半導体モジュールは、熱膨脹を
繰り返すことになる。その場合、段差吸収材のはんだ材
は熱膨脹を繰り返すがばね性は有しない。ばね性を有し
ないため加圧接触している歪緩衝板24と共通電極エミ
ッタ27の間で空間が発生し、電気的及び熱伝導が遮断
されることになる非常に大きな問題となる欠点があっ
た。
A plurality of semiconductor chips 21a, 21b, 21
Since c has different heights as shown in the figure, the softest solder material among the materials of this system is compressed as the multi-structure elastic body 25. The contact between the members due to the initial pressurization becomes good due to the deformation of the solder material. However, the semiconductor device is repeatedly used or stopped. That is, during use, the semiconductor chip generates heat and its temperature rises, and when stopped, the semiconductor chip is cooled and its temperature falls. That is, a semiconductor module in which heating and cooling are repeated repeats thermal expansion. In this case, the solder material of the step absorbing material repeats thermal expansion but does not have spring property. Since it does not have a spring property, a space is generated between the strain buffer plate 24 and the common electrode emitter 27 which are in pressure contact with each other, and there is a disadvantage that the electric and heat conduction is interrupted, which is a very serious problem. Was.

【0006】また、特開平5−211259 号公報にはIGB
Tモジュールの熱放散を良くするためにエミッタ端子板
に対して電気良導性を有する材料からなる鋼製のリング
状ばねを設けることが示されている。
[0006] Japanese Patent Application Laid-Open No. H5-211259 discloses an IGB
It is shown that a ring spring made of steel made of a material having good electrical conductivity is provided to the emitter terminal plate in order to improve heat dissipation of the T module.

【0007】[0007]

【発明が解決しようとする課題】上述のように半導体チ
ップの高さがばらばらな場合は、最も背の高いチップは
放熱フィンとの間の隙間が埋まるが、それよりも高さの
低いチップはフィンとの間で隙間の空いた状態となり、
その隙間の部分だけ著しく熱抵抗が上昇すると言う問題
を有していた。また、上述の公報では高い熱伝導性を得
ることができない。
As described above, when the heights of the semiconductor chips are different from each other, the tallest chip fills the gap between the semiconductor chip and the radiating fins. There is a gap between the fin and
There is a problem that the thermal resistance is significantly increased only in the gap. Further, in the above-mentioned publication, high thermal conductivity cannot be obtained.

【0008】本発明の目的は全ての半導体チップの高さ
を揃えることなく、高さの異なるチップを一括して、一
平板の放熱部材に確実に密着させて、放熱効果及び電気
的導通を上げるとともに機械的圧接のためチップリペア
をも簡便に行うことのできるマルチチップ型半導体装置
を提供するにある。
It is an object of the present invention to improve the heat radiation effect and electric conduction by making sure that the chips having different heights are collectively brought into close contact with a heat radiating member of one flat plate without adjusting the height of all the semiconductor chips. Another object of the present invention is to provide a multi-chip type semiconductor device capable of easily performing chip repair for mechanical pressure welding.

【0009】[0009]

【課題を解決するための手段】本発明は、半導体チップ
の熱を放熱部材を介して放熱する構造を有するマルチチ
ップ型半導体装置において、高さの異なる前記複数の半
導体チップと、これらの複数の半導体チップに対して放
熱部材との間に、半導体チップの高さのばらつきを吸収
する多重構造弾性体を介在させて加圧力により半導体チ
ップと放熱部材とを接続したことを特徴とするマルチチ
ップ型半導体装置にある。
According to the present invention, there is provided a multi-chip type semiconductor device having a structure in which heat of a semiconductor chip is radiated through a heat radiating member, wherein the plurality of semiconductor chips having different heights are provided. A multi-chip type wherein a semiconductor chip and a heat radiating member are connected by a pressing force with a multi-structure elastic body interposed between the semiconductor chip and a heat radiating member to absorb variations in the height of the semiconductor chip. In semiconductor devices.

【0010】また、共通電極部材間に設けられた複数の
半導体チップの上面と下面とに歪緩衝板を介して形成し
たマルチチップ型半導体装置において、高さの異なる前
記複数の半導体チップの他に、歪緩衝板の厚さのばらつ
き及び半導体チップと緩衝板をはんだ接合した場合のは
んだ層厚さのばらつき等、これらの複数の半導体チッ
プ、前記歪緩衝板及びはんだ層厚さのばらつき等に対し
て共通電極部材との間に、これらのばらつきを吸収する
多重構造弾性体を介在させて加圧力により放熱部材とを
接続したことを特徴とする。
Further, in a multi-chip type semiconductor device in which upper and lower surfaces of a plurality of semiconductor chips provided between common electrode members are formed via a strain buffer plate, in addition to the plurality of semiconductor chips having different heights, For a plurality of these semiconductor chips, such as the variation of the thickness of the strain buffer plate and the variation of the solder layer thickness when the semiconductor chip and the buffer plate are soldered, and the variation of the thickness of the strain buffer plate and the solder layer. And a heat dissipating member connected to the common electrode member by a pressurizing force with a multi-structure elastic body absorbing these variations interposed therebetween.

【0011】さらに高さの異なる複数の半導体チップが
共通電極部材間に設けられたマルチチップ型半導体装置
において、前記複数の半導体チップと共通電極部材との
間に、半導体チップの高さのばらつきを吸収する多重構
造弾性体を介在させて加圧力により半導体チップと電極
部材とを接続したマルチチップ型半導体装置にある。ま
た、本発明は、共通電極部材間に設けられた複数の半導
体チップの上面と下面とにはんだ接合された歪緩衝板を
介して形成されたマルチチップ型半導体装置において、
高さの異なる前記複数の半導体チップの他に、歪緩衝板
の厚さのばらつき及び半導体チップと緩衝板をはんだ接
合した場合のはんだ層厚さのばらつき等に対して共通電
極部材の一方と歪緩衝板との間に、これらのばらつきを
吸収する多重構造弾性体を介在させて加圧力により電極
部材とを接続していることを特徴とする。
In a multi-chip type semiconductor device having a plurality of semiconductor chips having different heights provided between common electrode members, a variation in height of the semiconductor chips is reduced between the plurality of semiconductor chips and the common electrode member. There is provided a multi-chip type semiconductor device in which a semiconductor chip and an electrode member are connected by a pressing force through a multi-structure elastic body that absorbs. Further, the present invention provides a multi-chip semiconductor device formed through a strain buffer plate soldered to upper and lower surfaces of a plurality of semiconductor chips provided between common electrode members,
In addition to the plurality of semiconductor chips having different heights, one of the common electrode members may be distorted due to variations in the thickness of the strain buffer plate and variations in the thickness of the solder layer when the semiconductor chip and the buffer plate are soldered. It is characterized in that a multi-structure elastic body for absorbing these variations is interposed between the buffer member and the electrode member by a pressing force.

【0012】更に本発明は複数の半導体チップがパワー
スイッチングデバイスや、絶縁ゲート型素子等に適用さ
れるマルチチップ型半導体装置でもある。
Further, the present invention is also a multi-chip type semiconductor device in which a plurality of semiconductor chips are applied to a power switching device, an insulated gate type element and the like.

【0013】半導体チップの製造後の高さを調査して見
ると、その高さが30〜60μm程の違いが測定され、
また、基板においても変形を有し、場所によっては50
〜100μm程度の段差が認められた。以上のことによ
り半導体モジュールとしての段差は、最小30μm,最
大160μm程あり、弾性体としては30〜160μm
程の段差を吸収できるものでなくてはならない。
Investigation of the height of the semiconductor chip after manufacture reveals that the height differs by about 30 to 60 μm.
In addition, the substrate also has a deformation.
A step of about 100 μm was observed. As described above, the step difference as a semiconductor module is about 30 μm at the minimum and about 160 μm at the maximum, and 30 to 160 μm as the elastic body.
It must be able to absorb the difference in level.

【0014】そこで、種々の金属について調査した結
果、弾性を持たせるにはパイプが良い。また、熱の放熱
作用の熱伝導性及び電気伝導性を考慮するとCu,A
g,Au又はこれらの合金が良いことが分かった。多重
構造体の中心部は中空であることが重要である。特に、
純Cuパイプが有効であり、同心円に、2重,3重パイ
プ構造,太径パイプ内に複数の小径パイプを並列に挿入
した構造の多重構造とすること、Cuに対してはNi,
Au,Ag等の耐酸化性,耐食性に優れた材料のめっき
等の皮膜を設けるのが好ましい。
Therefore, as a result of investigating various kinds of metals, a pipe is preferable to have elasticity. Considering the thermal conductivity and electric conductivity of the heat radiating action, Cu, A
g, Au or their alloys were found to be good. It is important that the center of the multi-layer structure is hollow. Especially,
A pure Cu pipe is effective, having a double or triple pipe structure in a concentric circle, a multiple pipe structure in which a plurality of small diameter pipes are inserted in parallel in a large diameter pipe, and Ni and Ni are used for Cu.
It is preferable to provide a coating such as plating of a material having excellent oxidation resistance and corrosion resistance such as Au and Ag.

【0015】特に、本発明に係る多重構造弾性体は段差
が50μmを弾性体に吸収できること、1〜1.5kg/m
m2の押圧でばね性を有すること、ばね性領域が50μm
以上あることが好ましい。
In particular, the multi-structure elastic body according to the present invention is capable of absorbing a step of 50 μm by the elastic body, and has a step of 1 to 1.5 kg / m.
Having spring property by pressing m 2 , spring area is 50 μm
It is preferable that there is the above.

【0016】[0016]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(実施例1)図1は本発明のマルチチップ型半導体装置
であり、加圧タイプのパッケージを示す断面図である。
高さの異なる複数の半導体チップ1a,1b,1cを熱
膨脹係数が半導体チップと同等であるMo,W,Cu−
C複合材等からなる歪緩衝板2の上に配置し、それらは
共通電極板のコレクタ3上に搭載する。半導体チップ1
の上には熱膨脹係数が半導体チップと同等であるMo,
W,Cu−C複合材等からなる歪緩衝板4が配置され、
その上に段差吸収の多重構造弾性体5が搭載される。こ
こでは多重構造弾性体はCuパイプの2重構造であり、
太径のパイプの中に小径のパイプを挿入し、次に扁平に
加工したものである。多重構造弾性体5の中心部分には
中空部分6を形成させることが重要である。そして共通
電極エミッタ7が上に接続される。
(Embodiment 1) FIG. 1 is a cross-sectional view showing a multi-chip type semiconductor device according to the present invention, showing a pressure-type package.
A plurality of semiconductor chips 1a, 1b, 1c having different heights are made of Mo, W, Cu- having the same thermal expansion coefficient as the semiconductor chips.
They are arranged on a strain buffer plate 2 made of a C composite material or the like, and they are mounted on a collector 3 of a common electrode plate. Semiconductor chip 1
On top of that, Mo, whose thermal expansion coefficient is equivalent to that of a semiconductor chip,
A strain buffer plate 4 made of W, Cu-C composite material or the like is arranged,
The step-absorbing multi-structure elastic body 5 is mounted thereon. Here, the multi-structure elastic body has a double structure of a Cu pipe,
A small-diameter pipe is inserted into a large-diameter pipe and then flattened. It is important to form a hollow portion 6 at the center of the multi-structure elastic body 5. Then, the common electrode emitter 7 is connected above.

【0017】また複数の半導体チップ1a,1cのよう
にその一部には、その端部にゲート電極8を配置し、共
通電極コレクタ3上の絶縁板9上にゲート配線網10を
配置する。ゲート電極8とゲート配線網10はワイヤリ
ード11で接続される。
A gate electrode 8 is disposed at an end of a part of the semiconductor chips 1a and 1c like a plurality of semiconductor chips 1a and 1c, and a gate wiring network 10 is disposed on an insulating plate 9 on the common electrode collector 3. The gate electrode 8 and the gate wiring network 10 are connected by wire leads 11.

【0018】この様に半導体チップ1を中心として各部
材が搭載され、共通電極コレクタ3と共通電極エミッタ
7は絶縁外筒12により固定されている。なお、半導体
チップ毎の配置は、絶縁位置決め板13により行われ
る。これが1単位モジュールの形状である。
As described above, each member is mounted around the semiconductor chip 1, and the common electrode collector 3 and the common electrode emitter 7 are fixed by the insulating outer tube 12. The arrangement of each semiconductor chip is performed by the insulating positioning plate 13. This is the shape of one unit module.

【0019】次に夫々の部材についての材質を記述す
る。半導体チップ1はSiであり、歪緩衝板2,4はS
iチップと熱膨脹係数が近いMo,W等が適用される。
共通電極コレクタ3及びエミッタ7は電気及び熱伝導性
に優れるCuを用いる。ゲート電極8,ゲート配線網1
0は電気的性質に優れるCuを当て、ワイヤリード11
はAl,Cu及びAu等が適用される。そして、段差吸
収の多重構造弾性体5は電気的及び熱伝導性に優れるC
uを用いる。
Next, the material of each member will be described. The semiconductor chip 1 is made of Si, and the strain buffer plates 2 and 4 are made of S
Mo, W, or the like having a thermal expansion coefficient close to that of the i-chip is applied.
The common electrode collector 3 and the emitter 7 use Cu which is excellent in electric and thermal conductivity. Gate electrode 8, gate wiring network 1
0 is Cu, which has excellent electrical properties,
Al, Cu, Au and the like are applied. The step-absorbing multi-structure elastic body 5 has excellent electrical and thermal conductivity.
u is used.

【0020】多重構造弾性体5はCuパイプを2種類用
いる。一つは外径φ8mm,内径φ6.8mmのCuパイプ
と他の一つは外径φ4mm,内径φ2.4mmのCuパイプ
を組み合わせ加圧して扁平加工する。その高さは半導体
チップの段差の大きさにより予め決定することができ
る。扁平に加工したパイプで重要な点は、2重構造パイ
プの中心部が中空部分6を存在させることである。即
ち、この中空部分が半導体チップ等の段差を吸収する作
用を持つのである。
The multi-structure elastic body 5 uses two types of Cu pipes. One is a combination of a Cu pipe having an outer diameter of φ8 mm and an inner diameter of 6.8 mm and the other is a Cu pipe having an outer diameter of φ4 mm and an inner diameter of 2.4 mm, and flattened by pressing. The height can be determined in advance by the size of the step of the semiconductor chip. An important point of the flat processed pipe is that the hollow portion 6 is present at the center of the double structure pipe. That is, this hollow portion has an action of absorbing a step of a semiconductor chip or the like.

【0021】この多重構造弾性体は上述した半導体チッ
プの厚さのばらつきの他に、歪緩衝板の厚さのばらつき
や半導体チップとコレクタ側緩衝板をはんだ接合した場
合のはんだ層厚さのばらつき等の段差をも吸収できるの
で、共通電極エミッタ7に接触されることになる。
In addition to the above-described variation in the thickness of the semiconductor chip, the variation in the thickness of the strain buffer plate and the variation in the thickness of the solder layer when the semiconductor chip and the collector-side buffer plate are joined by soldering are employed. Can be absorbed, so that it is brought into contact with the common electrode emitter 7.

【0022】また、半導体チップ1a,1b,1cが発
熱した際は、多重構造弾性体5に熱が伝わり、共通電極
エミッタ7へ熱が伝導されることにより、低熱抵抗を実
現することができる。
Further, when the semiconductor chips 1a, 1b, 1c generate heat, the heat is transmitted to the multi-structure elastic body 5 and is transmitted to the common electrode emitter 7, so that a low thermal resistance can be realized.

【0023】(実施例2)図2は本発明の他の実施例に
よるマルチチップ型半導体装置である。図1の実施例と
異なるのは、多重構造弾性体5の構造を変えたことであ
る。多重構造弾性体5はCuパイプを2種類用いる。一
つは外径φ8mm,内径φ6.0mm のCuパイプと他の一
つは外径φ2.2mm,内径φ1.6mmのCuパイプ3個を
組み合わせ加圧して扁平加工する。この場合小径のCu
パイプは3個であるため変形量が少なくなることがあ
る。実際は小径のCuパイプの3個共、扁平になる様に
加工することが望ましい。小径の中の中空部分6は3個
存在し、伸縮の作用の一端を担う。
(Embodiment 2) FIG. 2 shows a multi-chip type semiconductor device according to another embodiment of the present invention. The difference from the embodiment of FIG. 1 is that the structure of the multi-structure elastic body 5 is changed. The multi-structure elastic body 5 uses two types of Cu pipes. One is a combination of a Cu pipe having an outer diameter of φ8 mm and an inner diameter of 6.0 mm and the other is a combination of three Cu pipes having an outer diameter of 2.2 mm and an inner diameter of 1.6 mm. In this case, a small diameter Cu
Since there are three pipes, the amount of deformation may be reduced. Actually, it is desirable to process all three small diameter Cu pipes so as to be flat. There are three hollow portions 6 in the small diameter, which play one part in the action of expansion and contraction.

【0024】この多重構造弾性体は半導体チップの厚さ
のばらつきの他に、歪緩衝板の厚さのばらつきや半導体
チップとコレクタ側緩衝板をはんだ接合した場合のはん
だ層厚さのばらつき等の段差をも吸収できるので、共通
電極エミッタ7に接触されることになる。
This multi-structure elastic body has a thickness variation of the semiconductor chip, a variation of the thickness of the strain buffer plate, and a variation of the thickness of the solder layer when the semiconductor chip and the collector side buffer plate are soldered. Since the step can also be absorbed, it comes into contact with the common electrode emitter 7.

【0025】また、半導体チップ1a,1b,1cが発
熱した際は、多重構造弾性体5に熱が伝わり、共通電極
エミッタ7へ熱が伝導されることにより、低熱抵抗を実
現することができる。
Further, when the semiconductor chips 1a, 1b, 1c generate heat, the heat is transmitted to the multi-structure elastic body 5 and is transmitted to the common electrode emitter 7, so that a low thermal resistance can be realized.

【0026】即ち、大径のCuパイプにまず熱が伝わ
り、その熱が小径の3個のCuパイプのバイパスを介し
て共通電極エミッタ7へ熱が伝導されることにる。つま
り、Cuのバイパスが多い分熱の伝導性が良好となる。
That is, heat is first transmitted to the large-diameter Cu pipe, and the heat is transmitted to the common electrode emitter 7 through the bypass of the three small-diameter Cu pipes. That is, heat conductivity is improved by the amount of Cu bypass.

【0027】(実施例3)図3は1単位半導体モジュー
ルを積層して組み立てたマルチ型半導体装置を示す。半
導体チップの数及び積層の数は、電気的容量に合わせ決
められる。マルチ型半導体装置は、1単位半導体モジュ
ール毎に水冷電極14が配置される。そして積層された
半導体モジュールは全体を加圧15により加締められ
る。図から分かるように実施例1と同様に1単位半導体
モジュールの半導体チップ毎に多重構造弾性体が配置さ
れ、種々の段差に対応して伸縮する。それは最も段差の
大きい部材に合わせた加圧15を加え、全ての段差を多
重構造弾性体により吸収する。即ち、加圧15による加
締めと多重構造弾性体の作用により、半導体チップとの
電気的導通並びに半導体チップから発生する熱の伝導が
良好に行われる。
(Embodiment 3) FIG. 3 shows a multi-type semiconductor device assembled by stacking one unit semiconductor module. The number of semiconductor chips and the number of stacks are determined according to the electric capacity. In the multi-type semiconductor device, the water-cooled electrode 14 is provided for each unit semiconductor module. The whole of the stacked semiconductor modules is caulked by pressurization 15. As can be seen from the figure, similarly to the first embodiment, a multi-structure elastic body is arranged for each semiconductor chip of one unit semiconductor module, and expands and contracts according to various steps. It applies a pressure 15 to the member with the largest step, and absorbs all the steps with the multi-structure elastic body. That is, the electric conduction with the semiconductor chip and the conduction of the heat generated from the semiconductor chip are favorably performed by the caulking by the pressurization 15 and the action of the multi-structure elastic body.

【0028】なお、以上の実施例において半導体チップ
高さ,歪緩衝板の厚さ等の段差は、最小で50μm,最
大で250μmであった。また、マルチチップ型半導体
装置の使用,停止を繰り返した疲労試験においても2重
構造の弾性体を適用したものは、パイプにクラックも発
生せず長時間にわたり健全性を維持し、電気的及び熱伝
導性においても良好な特性を有した。
In the above embodiment, the steps such as the height of the semiconductor chip and the thickness of the strain buffer plate were 50 μm at the minimum and 250 μm at the maximum. In a fatigue test in which the use and shutdown of a multi-chip type semiconductor device were repeated, the use of a double-structured elastic body maintained the soundness for a long time without cracks in the pipe, and maintained electrical and thermal performance. It also had good properties in conductivity.

【0029】(実施例4)図4はIGBTモジュールの
断面図である。図においてシリコン(Si)からなるI
GBT用の半導体チップ1の上面にはゲート構造の上部
を避けてエミッタ集電電極31が設けられ、下面にはコ
レクタ電極32が設けられている。コレクタ電極32
は、Siとほぼ熱膨脹係数の等しいモリブデン(Mo)
からなる熱膨脹緩和のための支持板2がろう付けまたは
融着されている。そして、この支持板2は一面が容器外
面に露出している銅からなる共通電極コレクタが、ろう
30により取り付けられている。一方、エミッタ集電電
極31の上面にも熱膨脹緩和とヒートシンク用としてM
oからなる支持35が設けられる。この支持板35と容
器外面に露出する共通電極エミッタ7の間にリング状2
重ばね36が介在する。このばね36は各々0.6mm 厚
さの純銅パイプよりなるものである。外側の純銅パイプ
は外径8.0mm,内側の純銅パイプは外径6.0mmであ
り、両者は一体に接合されていないものである。また、
半導体チップ1と共通電極エミッタ7の間にエミッタ集
電電極31,支持板35およびばね36からなる電流お
よび熱の通路が構成される。この構造では、Moの支持
板35とエミッタ集電電極31との間に加圧接触が生ず
るが、Moの支持板35を例えばアルミニウム(Al)
からなる電極に融着させてもよい。その場合もばね36
は半導体チップ1とMoの支持板35あるいはMoの支
持板32との接続の信頼性を高めるのに役立つ。ゲート
電極は容器外面に出るゲート端子とAl導線のボンディ
ングで接続される。
(Embodiment 4) FIG. 4 is a sectional view of an IGBT module. In the figure, I made of silicon (Si)
An emitter collector electrode 31 is provided on the upper surface of the GBT semiconductor chip 1 so as to avoid the upper part of the gate structure, and a collector electrode 32 is provided on the lower surface. Collector electrode 32
Is molybdenum (Mo) whose thermal expansion coefficient is almost equal to that of Si
A support plate 2 for reducing thermal expansion is brazed or fused. The support plate 2 is provided with a common electrode collector made of copper, one surface of which is exposed to the outer surface of the container, and is attached by a solder 30. On the other hand, the upper surface of the emitter collector electrode 31 is also provided with M
A support 35 made of o is provided. A ring 2 is provided between the support plate 35 and the common electrode emitter 7 exposed on the outer surface of the container.
A heavy spring 36 is interposed. The springs 36 are each made of a pure copper pipe having a thickness of 0.6 mm. The outer pure copper pipe has an outer diameter of 8.0 mm and the inner pure copper pipe has an outer diameter of 6.0 mm, and the two are not integrally joined. Also,
Between the semiconductor chip 1 and the common electrode emitter 7, an electric current and heat path composed of the emitter collecting electrode 31, the support plate 35 and the spring 36 is formed. In this structure, pressure contact occurs between the Mo support plate 35 and the emitter collector electrode 31, but the Mo support plate 35 is made of, for example, aluminum (Al).
May be fused to the electrode made of. Also in that case, the spring 36
Helps to improve the reliability of the connection between the semiconductor chip 1 and the Mo support plate 35 or the Mo support plate 32. The gate electrode is connected to the gate terminal exposed on the outer surface of the container by bonding an Al conductor.

【0030】図5は本発明に係る純銅からなる2重パイ
プ(Cu2重パイプ)に対して比較の純銅1重パイプ
(Cu1重パイプ)及びSUS304ステンレス鋼からなる1
重パイプ(SUS1重パイプ)の室温での径方向への変
形量と加圧力との関係を示す線図である。図に示すよう
にCu1重パイプは加圧力が50kgfを越えると急激に
変形してしまいばね特性が低い。SUS1重パイプは十
分なばね特性を有する。本発明におけるCu2重パイプ
はSUS1重パイプと同等のばね特性を有するものであ
る。
FIG. 5 shows a comparison between a pure copper single pipe (Cu double pipe) and a pure copper single pipe (Cu single pipe) and a stainless steel 304 stainless steel pipe according to the present invention.
It is a diagram which shows the relationship between the amount of deformation of the heavy pipe (SUS single pipe) in the radial direction at room temperature and the pressing force. As shown in the figure, when the pressing force exceeds 50 kgf, the Cu single pipe is rapidly deformed and has low spring characteristics. SUS single pipe has sufficient spring properties. The Cu double pipe in the present invention has the same spring characteristics as the SUS single pipe.

【0031】図6は同じばね性領域と加圧力との関係を
示す線図である。図に示す如く、Cu1重パイプは50
kgfを越えるとばね性が得られないものであることから
も明らかであるが、本発明のCu2重パイプとすること
により高いばね性が得られる。本実施例において加圧力
50kgfは0.72kg/mm2,122kgは1.76kgf/mm
2 であり、加圧力70〜105kgfが1〜1.5kgf/m
m2に相当するので、この加圧力においてばね性領域が5
0μm以上有することが好ましい。本発明のCu2重パ
イプは十分満足できるものである。
FIG. 6 is a diagram showing the relationship between the same spring region and the pressing force. As shown in FIG.
Although it is clear from the fact that the spring property cannot be obtained when the weight exceeds kgf, a high spring property can be obtained by using the Cu double pipe of the present invention. In this embodiment, the pressure of 50 kgf is 0.72 kg / mm 2 , and the pressure of 122 kg is 1.76 kgf / mm 2 .
2 , and the applied pressure of 70 to 105 kgf is 1 to 1.5 kgf / m
Since corresponding to m 2, the spring region in the pressure 5
Preferably, it has a thickness of 0 μm or more. The Cu double pipe of the present invention is sufficiently satisfactory.

【0032】以下、Cu2重パイプについて次の実験を
行った。
The following experiment was conducted on a Cu double pipe.

【0033】Cuパイプは半導体チップの形状に合うよ
うに切断し、押圧して扁平に加工し、電極板,歪緩衝板
との熱的,電気的なコンタクト領域を確保する。まずC
uの1重パイプを扁平に加工したものについて加圧力と
変形量を調査した。その結果、加圧力50kg付与時20
0μm,120kg付与時1100μmを示した。加圧力
付与後、ばね性領域を調査したところ50kg付与時で1
40μmあり、120kg付与時で10μmを示した。こ
の結果は低加圧力では使用できるが、高加圧力ではばね
性が小さく使用不可であることが分かった。
The Cu pipe is cut so as to conform to the shape of the semiconductor chip, pressed to be flattened, and a thermal and electrical contact area with the electrode plate and the strain buffer plate is secured. First C
The pressing force and deformation amount of a single pipe made of u were processed flat. As a result, when a pressing force of 50 kg is applied, 20
0 μm and 1100 μm when 120 kg was applied. After applying the pressing force, the spring area was examined.
It was 40 μm, and showed 10 μm when 120 kg was applied. It was found that this result can be used at a low pressing force, but cannot be used at a high pressing force because of its low spring property.

【0034】そこで、Cuの2重パイプについて同様に
加圧力と変形量を調査した。その結果、加圧力50kg付
与時90μm,120kg付与時190μmを示した。加
圧力付与後、ばね性領域(弾性領域とも言う)を調査し
たところ50kg付与時で80μmあり、120kg付与時
で140μmを示した。
Therefore, the pressing force and the deformation amount of the Cu double pipe were similarly examined. As a result, the applied pressure was 90 μm when applied with 50 kg and 190 μm when applied with 120 kg. After the application of the pressing force, the spring region (also referred to as the elastic region) was examined, and found to be 80 μm when 50 kg was applied and 140 μm when 120 kg was applied.

【0035】この結果は半導体チップの段差が例えば1
90μmあったとすれば、放熱部材を120kg付与すれ
ば半導体チップと放熱部材が均一に密着し、その後は、
140μm範囲のばね性を維持することを示している。即
ち、半導体チップの段差に応じて加圧力を決めることが
でき、しかもその加圧力でばね性を維持すると言うこと
が明らかになった。つまり、Cuの2重パイプを扁平に
加工して利用することにより、弾性体としての作用を十
分発揮できることが分かった。
This result indicates that the step of the semiconductor chip is, for example, 1
Assuming that the thickness is 90 μm, the semiconductor chip and the heat radiating member uniformly adhere to each other when 120 kg of the heat radiating member is applied.
It shows that the spring property in the 140 μm range is maintained. That is, it has been found that the pressing force can be determined according to the step of the semiconductor chip, and that the spring force is maintained by the pressing force. In other words, it has been found that by working a Cu double pipe in a flat shape, the effect as an elastic body can be sufficiently exhibited.

【0036】2重パイプは夫々のパイプが拘束しあい、
加圧力に耐え、ばね性を有する。また、3重パイプ,2
重パイプでの種々の形状については、本発明の応用例の
項で詳しく述べる。また、Cuパイプ1重と2重の半導
体モジュールを作製し、電気的On,Off を繰り返した実
験を行った結果、Cu1重パイプは1000回の繰り返
しでCuパイプの端部からクラックが発生し、その時点
からばね性がなくなってしまった。
In the double pipe, the respective pipes restrain each other,
Withstands pressure and has spring properties. In addition, triple pipe, 2
Various shapes of the heavy pipe will be described in detail in the application section of the present invention. In addition, as a result of conducting an experiment in which a single-layer and a double-layer semiconductor module of a Cu pipe were manufactured and electrical on and off were repeated, a crack was generated from the end of the Cu pipe in the Cu single pipe by repeating 1000 times. From that point on, the spring has disappeared.

【0037】それに対し、Cu2重パイプは10000
回の繰り返しにおいてもクラックの発生は見られず、そ
の後も良好な弾性体としての特性を維持することが確認
された。
On the other hand, a Cu double pipe is 10,000
No cracks were observed even after the repetition, and it was confirmed that good elastic properties were maintained thereafter.

【0038】即ち、段差吸収材はパイプが非常に良好な
結果が得られ、パイプの中でも多重構造弾性体が種々の
段差に対応でき、且つ、長期使用に対しても信頼性に優
れることが明らかになった。
In other words, it is clear that the pipe with the step difference absorbing material has a very good result, and that the multi-layered elastic body can cope with various steps in the pipe and has excellent reliability even for long-term use. Became.

【0039】本発明の半導体装置は、発熱が問題となる
半導体チップ全般に有効で、特に半導体チップの第1及
び第2主面を主電極とするIGBT等の絶縁ゲート型素
子を含むパワースイッチングデバイスに好適である。
The semiconductor device according to the present invention is effective for all semiconductor chips in which heat generation is a problem, and in particular, a power switching device including an insulated gate element such as an IGBT having the first and second main surfaces of the semiconductor chip as main electrodes. It is suitable for.

【0040】図7はIGBTモジュールの外観を示す斜
視図である。
FIG. 7 is a perspective view showing the appearance of the IGBT module.

【0041】図4に示したようにモジュールの両面冷却
を可能にするため、体積が従来の約1/2と小さくなっ
たIGBTモジュールを造ることができる。さらに、モ
ジュールの内部空間に、アルミナ入りゲル樹脂のような
熱伝導性の高いゲルを充填すれば、さらに共通電極エミ
ッタ7の側への熱放散がよくなる。図7に示すようにIG
BTモジュールの外観は、絶縁性側壁40に囲まれた容器
の上面に共通電極エミッタ7が露出し、側面にゲート端
子33が突出している。共通電極エミッタ7には冷却体
取付穴72が明けられている。
As shown in FIG. 4, since the module can be cooled on both sides, it is possible to manufacture an IGBT module whose volume is reduced to about half that of the conventional IGBT module. Furthermore, if the interior space of the module is filled with a gel having high thermal conductivity such as a gel resin containing alumina, the heat dissipation to the common electrode emitter 7 side is further improved. As shown in FIG.
The appearance of the BT module is such that the common electrode emitter 7 is exposed on the upper surface of the container surrounded by the insulating side wall 40, and the gate terminal 33 protrudes on the side surface. The common electrode emitter 7 has a cooling body mounting hole 72 formed therein.

【0042】図8は半導体チップを10個搭載したマル
チチップ型半導体装置の断面図である。本実施例におけ
る構造の基本は図1の多重構造弾性体を除き全く同じで
ある。
FIG. 8 is a sectional view of a multi-chip type semiconductor device having ten semiconductor chips mounted thereon. The basic structure of this embodiment is exactly the same except for the multi-structure elastic body shown in FIG.

【0043】(比較例)比較として1重Cuパイプの弾
性体を用いてマルチチップ型半導体装置を、実施例と同
様に試験した。初期において、段差が50μmと小さい
ときには良好な段差吸収を示したが、段差が250μm
と大きいときには加圧力を外した時に非接触になった。
即ち、最初の加圧で変形はするがその後に加圧を取り除
いた場合、空間ができたことである。つまり、本発明の
目的とする弾性体がある範囲の段差では発揮できないこ
とであり、1重Cuパイプは適用できないことが分かっ
た。
(Comparative Example) As a comparison, a multi-chip type semiconductor device was tested in the same manner as in the example using an elastic body of a single Cu pipe. Initially, when the step was as small as 50 μm, good step absorption was exhibited, but the step was 250 μm.
When it was large, it was not in contact when the pressure was removed.
That is, the space is created when the deformation is caused by the initial pressurization but the pressurization is removed thereafter. In other words, it was found that the elastic body intended by the present invention cannot be exerted at a certain level difference, and that a single Cu pipe cannot be applied.

【0044】また、段差が小さい場合において、長期使
用の実験を行ったところパイプの端部からクラックが発
生し、信頼性に問題があることが分かった。
Further, when the step was small, an experiment of long-term use revealed that cracks occurred from the end of the pipe, and there was a problem in reliability.

【0045】(実施例5)図9に多重構造弾性体5及び
中空部分6の実施例以外でその他の応用例を示す。
(a)は大径の中に小径パイプを2個挿入した2重構
造、(b)は2重パイプの中に小径パイプを1個挿入し
た3重構造、(c)は2重パイプの中に小径パイプを2
個挿入した3重構造、(d)は2重パイプの中に小径パ
イプを多数個挿入した3重構造を示す。
(Embodiment 5) FIG. 9 shows another application example other than the embodiment of the multi-structure elastic body 5 and the hollow portion 6.
(A) is a double structure in which two small diameter pipes are inserted in a large diameter, (b) is a triple structure in which one small diameter pipe is inserted in a double pipe, and (c) is a double structure in which two small pipes are inserted. 2 small diameter pipes
(D) shows a triple structure in which a number of small diameter pipes are inserted in a double pipe.

【0046】いずれも、半導体チップ等の段差の大きさ
に対応してCuパイプの厚さや構造を選択する必要があ
る。特徴的にはいずれの多重構造にせよ、パイプの中心
上に空隙を存在させていることである。
In any case, it is necessary to select the thickness and structure of the Cu pipe in accordance with the size of the step of the semiconductor chip or the like. Characteristically, in any of the multiple structures, a gap exists on the center of the pipe.

【0047】多重構造弾性体としてCuパイプについて
述べたが、その他に電気及び熱伝導性の良好な材料、例
えばAg,Au,Alもしくはそれらの合金を適用して
も弾性体としての特性を十分発揮する。また、Cuパイ
プの酸化保護や特性維持のための表面処理、例えばN
i,Ag,Au等のめっき等を施して使用しても本発明
の電気的及び熱伝導性、並びに弾性体としての特性が得
られることを確認している。
Although the Cu pipe has been described as the multi-structure elastic body, even if a material having good electric and thermal conductivity, for example, Ag, Au, Al or an alloy thereof is applied, the characteristics as the elastic body can be sufficiently exhibited. I do. Further, surface treatment for protecting the oxidation of the Cu pipe and maintaining the characteristics, for example, N 2
It has been confirmed that the electrical and thermal conductivity of the present invention and the properties as an elastic body can be obtained even when plated with i, Ag, Au or the like and used.

【0048】[0048]

【発明の効果】以上に説明したように、本発明によれば
従来、複数の高さの異なる半導体チップや歪緩衝板の厚
さのばらつき等があるものを1個の共通電極に同時に接
続するのが困難とされていたものが、本発明の多重構造
弾性体を用いた半導体装置とすることにより容易に接続
することが可能となった。
As described above, according to the present invention, a plurality of semiconductor chips having different heights and variations in thickness of a strain buffer plate are connected to one common electrode at the same time. However, it has become difficult to connect the semiconductor device to the semiconductor device using the multi-structure elastic body of the present invention.

【0049】これにより、マルチチップモジュール等を
設計する際に、半導体チップのレイアウトや熱設計が容
易となり、且つ加圧型で半導体装置を作製することが容
易になった効果を発揮できる。
As a result, when designing a multi-chip module or the like, the layout and thermal design of the semiconductor chip can be easily performed, and the effect that the semiconductor device can be easily manufactured in a pressurized type can be exhibited.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例によるマルチチップ型の半導体
装置であって、加圧型のパッケージの断面図。
FIG. 1 is a cross-sectional view of a pressure-type package, which is a multi-chip type semiconductor device according to an embodiment of the present invention.

【図2】本発明の実施例によるマルチチップ型の半導体
装置であって、加圧型のパッケージの断面図。
FIG. 2 is a cross-sectional view of a multi-chip type semiconductor device according to an embodiment of the present invention, which is a pressurized type package.

【図3】本発明の実施例によるマルチチップ型の半導体
装置であって、加圧型のパッケージを組み立てた断面
図。
FIG. 3 is a cross-sectional view of a multi-chip type semiconductor device according to an embodiment of the present invention, in which a pressure-type package is assembled.

【図4】本発明の他の実施例に係るマルチチップ型半導
体装置。
FIG. 4 shows a multi-chip type semiconductor device according to another embodiment of the present invention.

【図5】変形量と加圧力との関係を示す線図。FIG. 5 is a diagram showing a relationship between a deformation amount and a pressing force.

【図6】ばね性領域と加圧力との関係を示す線図。FIG. 6 is a diagram showing a relationship between a spring region and a pressing force.

【図7】本発明に係るマルチチップ型半導体装置の全体
斜視図。
FIG. 7 is an overall perspective view of a multi-chip semiconductor device according to the present invention.

【図8】本発明の他の実施例に係るマルチチップ型半導
体装置。
FIG. 8 shows a multi-chip semiconductor device according to another embodiment of the present invention.

【図9】本発明のマルチチップ型半導体装置に適用する
多重構造弾性体の他の例を示す斜視図。
FIG. 9 is a perspective view showing another example of the multi-structure elastic body applied to the multi-chip semiconductor device of the present invention.

【図10】従来のマルチチップ型半導体装置の断面図。FIG. 10 is a cross-sectional view of a conventional multichip semiconductor device.

【符号の説明】[Explanation of symbols]

1a,1b,1c,21a,21b,21c…半導体チ
ップ、2,4,22,24…歪緩衝板、3,23…共通
電極コレクタ、5,25…多重構造弾性体、6…中空部
分、7,27…共通電極エミッタ、8,28…ゲート電
極、9,29…絶縁板、10,210…ゲート配線網、
11,211…ワイヤリード、12,212…絶縁外
筒、13,213…絶縁位置決め板、14…水冷電極、
15…加圧。
1a, 1b, 1c, 21a, 21b, 21c: semiconductor chip, 2, 4, 22, 24: strain buffer plate, 3, 23: common electrode collector, 5, 25: multi-structure elastic body, 6: hollow portion, 7 27, common electrode emitter, 8, 28 gate electrode, 9, 29 insulating plate, 10, 210 gate wiring network,
11, 211: wire lead, 12, 212: insulating outer cylinder, 13, 213: insulating positioning plate, 14: water-cooled electrode,
15 ... Pressure.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 児玉 弘則 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 井上 広一 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hironori Kodama 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Koichi Inoue 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Inside the Hitachi Research Laboratory, Hitachi, Ltd.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】半導体チップの熱を放熱部材を介して放熱
する構造を有するマルチチップ型半導体装置において、
前記半導体チップと放熱部材との間に、多重構造弾性体
を介在させて前記半導体チップと放熱部材とを接続した
ことを特徴とするマルチチップ型半導体装置。
1. A multi-chip type semiconductor device having a structure for radiating heat of a semiconductor chip through a heat radiating member.
A multi-chip type semiconductor device, wherein the semiconductor chip and the heat radiating member are connected between the semiconductor chip and the heat radiating member with a multi-structure elastic body interposed therebetween.
【請求項2】共通電極部材間に設けられた複数の半導体
チップの上面と下面とに歪緩衝板を介して形成したマル
チチップ型半導体装置において、前記歪緩衝板と前記共
通電極の一方との間に多重構造弾性体を介在させて加圧
接続したことを特徴とするマルチチップ型半導体装置。
2. A multi-chip type semiconductor device wherein upper and lower surfaces of a plurality of semiconductor chips provided between common electrode members are formed with a strain buffer interposed therebetween. A multi-chip type semiconductor device characterized by being connected under pressure with a multi-structure elastic body interposed therebetween.
【請求項3】高さの異なる複数の半導体チップが共通電
極部材間に設けられたマルチチップ型半導体装置におい
て、前記半導体チップと共通電極部材との間に、多重構
造弾性体を介在させて加圧力により前記半導体チップと
共通電極部材とを電気的に接続したことを特徴とするマ
ルチチップ型半導体装置。
3. A multi-chip type semiconductor device in which a plurality of semiconductor chips having different heights are provided between common electrode members, wherein a multi-structure elastic body is interposed between the semiconductor chip and the common electrode members. A multi-chip semiconductor device, wherein the semiconductor chip and the common electrode member are electrically connected by pressure.
【請求項4】共通電極部材間に設けられた複数の半導体
チップの上面と下面とにはんだ接合された歪緩衝板を介
して形成したマルチチップ型半導体装置において、前記
共通電極部材の一方と歪緩衝板との間に多重構造弾性体
を介在させて加圧力により電極部材とを接続したことを
特徴とするマルチチップ型半導体装置。
4. A multi-chip type semiconductor device formed through a strain buffer plate solder-bonded to upper and lower surfaces of a plurality of semiconductor chips provided between common electrode members. A multi-chip type semiconductor device characterized in that a multi-structure elastic body is interposed between a buffer plate and an electrode member connected by a pressing force.
【請求項5】前記多重構造弾性体はCu,Ag,Auも
しくはこれらを主にした合金材からなり、少なくとも多
重構造体の中心部は中空である請求項1〜4のいずれか
に記載のマルチチップ型半導体装置。
5. The multi-layer structure according to claim 1, wherein said multi-layer structure elastic body is made of Cu, Ag, Au or an alloy material mainly composed of Cu, Ag and Au, and at least the center of said multi-layer structure is hollow. Chip type semiconductor device.
【請求項6】前記多重構造弾性体は少なくとも2重のパ
イプ構造又は2層以上のパイプ構造であり、2重又は2
層以上の構造の中心部は中空である請求項1〜5のいず
れかに記載のマルチチップ型半導体装置。
6. The multi-structure elastic body has at least a double pipe structure or a pipe structure of two or more layers.
The multi-chip semiconductor device according to claim 1, wherein a central portion of the structure having more than one layer is hollow.
【請求項7】前記多重構造弾性体は純Cuからなり、そ
の表面がNi,Ag,Auより選ばれる耐酸化性の高い
材料で覆われている請求項5又は6に記載のマルチチッ
プ型半導体装置。
7. The multi-chip semiconductor according to claim 5, wherein said multi-structure elastic body is made of pure Cu, and the surface thereof is covered with a material having high oxidation resistance selected from Ni, Ag, and Au. apparatus.
【請求項8】前記半導体チップがパワースイッチングデ
バイスを含む請求項1〜7のいずれかに記載のマルチチ
ップ型半導体装置。
8. The multi-chip semiconductor device according to claim 1, wherein said semiconductor chip includes a power switching device.
【請求項9】前記半導体チップが絶縁ゲ−ト型素子を含
む請求項1〜7のいずれかに記載のマルチチップ型半導
体装置。
9. The multi-chip semiconductor device according to claim 1, wherein said semiconductor chip includes an insulated gate element.
JP25120296A 1996-09-24 1996-09-24 Multiple-chip type semiconductor device Pending JPH1098140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25120296A JPH1098140A (en) 1996-09-24 1996-09-24 Multiple-chip type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25120296A JPH1098140A (en) 1996-09-24 1996-09-24 Multiple-chip type semiconductor device

Publications (1)

Publication Number Publication Date
JPH1098140A true JPH1098140A (en) 1998-04-14

Family

ID=17219216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25120296A Pending JPH1098140A (en) 1996-09-24 1996-09-24 Multiple-chip type semiconductor device

Country Status (1)

Country Link
JP (1) JPH1098140A (en)

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