JPH1097219A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a double display without increasing a circuit scale, and outer dimension of a device when the number of display data are deficient for the number of pixels of one display line of liquid crystal panel by generating a control signal at the timing proportional to its deficit. SOLUTION: A difference value operation means is constituted of a counter 202, a register 205, a storage means 206 and a subtracter 208. When the display data transmitted from a main body computer side are deficient for the number of pixels of one display line of the liquid crystal display panel, its difference value is obtained by the subtracted 208. The timing of a rise of a clock signal G is accelerated, and the stop of the clock signal D2 is accelerated similarly based on the difference value, and further, the clock signal D1 is generated rapidly. In such a manner, even when the number of display data transmitted from the main body computer side are deficient, it becomes possible that the time from the rise of the clock signal G to the rise of the clock signal D1 is secured to a fixed level, and the invalid data is not latched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to a case where the number of display data is small relative to the total number of pixels of a liquid crystal display panel.

[0002]

2. Description of the Related Art Conventionally, as one of liquid crystal display devices, TF
2. Description of the Related Art There is known a T (Thin Film Transistor) type active matrix type liquid crystal display device.

FIG. 20 is a block diagram showing a schematic structure of a TFT type liquid crystal display module which is one of the conventional TFT type active matrix type liquid crystal display devices.

In the liquid crystal display module shown in FIG. 1, a drain driver 530 is disposed above a liquid crystal display panel (TFT-LCD).
A gate driver 540 and an interface unit 500 are arranged on a side surface of the CD).

The interface section 500 is mounted on an interface board, and the drain driver 530 and the gate driver 540 are also mounted on dedicated printed boards.

[0006] A liquid crystal display panel (TFT-LCD) is formed in a matrix and has a plurality of pixels arranged in an intersection region between a drain signal line (D) and a gate signal line (G).

Each pixel includes a thin film transistor (TFT),
Pixel electrode (not shown), common electrode, liquid crystal capacitance (CL
C) and additional capacity (CADD).

Hereinafter, in this specification, each pixel arranged in the row direction is called one display line.

FIG. 21 is a diagram showing an equivalent circuit of the liquid crystal display panel (TFT-LCD) shown in FIG.

As shown in FIG. 21, a thin film transistor (TFT) of each pixel includes two adjacent signal lines (a drain signal line (D) or a gate signal line (G)) and two adjacent signal lines. (A gate signal line (G) or a drain signal line (D)).

The source electrode of the thin film transistor (TFT) is connected to the pixel electrode, and a liquid crystal layer is provided between the pixel electrode and the common electrode.
The liquid crystal capacitance (CL)
C) are equivalently connected.

An additional capacitance (CADD) is connected between the source electrode of the thin film transistor (TFT) and the gate signal line (G) of the preceding display line.

The drain electrode of the thin film transistor (TFT) in each pixel arranged in the column direction is connected to a drain signal line (D), and each drain signal line (D)
Is a drain driver 5 for supplying an image voltage (display data voltage) for driving the liquid crystal to the drain signal line (D).
30.

The gate electrodes of the thin film transistors (TFTs) in the respective pixels arranged in the row direction are connected to gate signal lines (G), respectively.
Is connected to a gate driver 540 that supplies a positive bias voltage or a negative bias voltage to the gate of the thin film transistor (TFT) for one horizontal scanning time.

A thin film transistor (TFT) becomes conductive when a positive bias voltage is applied to the gate electrode, and becomes non-conductive when a negative bias voltage is applied to the gate electrode.

Here, a liquid crystal display panel (T) shown in FIG.
An FT-LCD is composed of 640 × 3 × 480 pixels.

In the liquid crystal display module shown in FIG.
The interface unit 500 includes a display control device 510 and a power supply circuit 520.

The display control device 510 is composed of one semiconductor integrated circuit (LSI), and displays control signals such as a clock signal, a display timing signal, a horizontal synchronizing signal, and a vertical synchronizing signal transmitted from the main computer.
The drain driver 530 and the gate driver 540 are controlled and driven based on the display data.

The power supply circuit 520 includes the positive voltage generation circuit 52
1, a negative voltage generation circuit 522, a common electrode (counter electrode) voltage generation circuit 523, a gate electrode voltage generation circuit 524, and a multiplexer 525.

The positive voltage generation circuit 521 and the negative voltage generation circuit 5
Each of the reference numerals 22 includes a series resistance voltage dividing circuit, and generates a gray scale reference voltage of a positive voltage or a gray scale reference voltage of a negative voltage.

The multiplexer 525 is connected to the display controller 5
10, the output voltage from the positive voltage generation circuit 521 or the output voltage from the negative voltage generation circuit 522 is switched according to the AC signal (AC signal) from the drain driver 5.
Output to 30.

The common electrode voltage generation circuit 523 applies a drive voltage applied to the common electrode to the gate electrode voltage generation circuit 52.
Reference numeral 4 generates a driving voltage (positive bias voltage and negative bias voltage) applied to the gate of the thin film transistor (TFT).

FIG. 22 is a block diagram showing a schematic configuration of the drain driver 530 shown in FIG.

As shown in FIG.
0 has one gray scale voltage generation circuit 557, and the gray scale voltage generation circuit 557 is a 9-level gray scale reference voltage (V0 to V0) input from the positive voltage generation circuit 521 or the negative voltage generation circuit 522. V8), a gradation voltage for 64 gradations is generated and output to the output circuit 556 via the voltage bus line 558.

The shift register circuit 552 in the control circuit 551 of the drain driver 530 receives a display data latch clock signal (D2) (hereinafter, referred to as a clock signal (D2)) input from the display control device 510. Based on the signal, a signal for capturing data of the input register circuit 553 is generated and output to the input register circuit 553.

The input register circuit 553 synchronizes with a display data latch clock signal (D 2) input from the display control device 510 based on a data capture signal output from the shift register circuit 552, and outputs 6 bits for each color. Is latched by the number of output lines.

The storage register circuits 554 display the signals in all the input register circuits 553 in response to the output timing control clock signal (D1) (hereinafter referred to as the clock signal (D1)) input from the display control device 510. Latch the data.

The display data captured by the storage register circuit 554 is input to the output circuit 556 via the level shift circuit 555.

The output circuit 556 includes a level shift circuit 55
Based on the display data from 5 and the AC signal, one of the 64 gray scale voltages input via the voltage bus line 558 is selected and output to the drain signal line (D).

Here, the input register circuit 553 and the storage register circuit 554 constitute a data latch unit.

FIG. 23 shows the gate driver 5 shown in FIG.
It is a block diagram which shows schematic structure of 40.

The gate driver 540 shown in FIG. 7 includes a logic circuit 561. When a frame start instruction signal (or a carry signal at the preceding stage) is input, the logic circuit 561 receives a clock signal (from the display control device 510). A shift signal is generated based on G1) and output to the shift register circuit 562.

The shift register circuit 562 operates based on the shift signal from the logic circuit 561 to display the display control device 51.
The shift clock signal (G1) input from 0 (hereinafter referred to as “G1”)
This is referred to as a clock signal (G1). ) Is sequentially output from each output terminal.

The gate selection signal from the shift register circuit 562 is input to the output circuit 564 via the level shift circuit 563.

In the output circuit 564, a thin film transistor is turned on to a gate signal line (G) to which a gate selection signal is output.
And a gate voltage (negative bias voltage) at which the thin film transistor is turned off is output to the other gate signal lines (G).

Thus, the gate driver 540 receives the clock signal (G1) input from the display control device 510.
, A plurality of thin film transistors (TFTs) connected to each gate signal line (G) of a liquid crystal display panel (TFT-LCD) are sequentially turned on every horizontal time.

FIG. 24 is a timing chart of a display control signal from the main computer shown in FIG. 20 and a control signal generated by the display control device 510.

When a display timing signal is input, the display control device 510 determines that the display timing signal is a display start position, and sends the received simple display data of one column to the drain driver 530 via the display data bus line 533. Output.

At this time, the display control device 510 supplies a clock signal (D) as a control signal for latching display data to the input register circuit 553 of the drain driver 530.
2) is output to the drain driver 530 via the signal line 531.

In this case, the display data from the main computer side is one pixel unit, that is, red (R), green (G),
Each set of blue (B) data is transferred as a set for each unit time.

Here, the display data is composed of 18 bits, 6 bits for each color.

Further, the carry output of the preceding stage of the drain driver 530 is directly used as the drain driver 53 of the next stage.
0 is input to the carry input, and the carry signal controls the data latch operation of the drain driver 530 to prevent erroneous display data from being written to the data latch unit.

The display control device 510 counts a predetermined number of clock signals after the input of the display timing signal, thereby completing the input of the display timing signal or after the input of the display timing signal. It is determined whether or not a predetermined time has elapsed, and as a result, the display data latched in the input register circuit 553 of the drain driver 530 is latched in the storage register circuit 554 assuming that the display data for one horizontal has been completed. , LCD panel (TF
A clock signal (D1), which is a control signal for outputting to the drain signal line (D) of the T-LCD, is output to the drain driver 530 via the signal line 532.

When the first display timing signal is input after the input of the vertical synchronization signal, the display control device 510 determines that this is the first display line, and determines the first display timing signal via the signal line 542. A frame start instruction signal is output to 540.

Further, the display control device 510 uses a shift clock signal for sequentially selecting each gate signal line (G) of the liquid crystal display panel (TFT-LCD) every horizontal scanning time based on the horizontal synchronization signal. Is a clock signal (G
1) is output to the gate driver 540 via the signal line 541.

As described above, the display timing signal, the horizontal synchronizing signal, and the vertical synchronizing signal are used for recognizing the display start position of the liquid crystal display panel (TFT-LCD).

The time (tGD) from the fall of the clock signal (G1) to the clock signal (D1) is determined by switching the gate signal line (G) to be selected (to which a positive bias voltage is applied), This is the time until the gate electrode of the thin film transistor (TFT) connected to the signal line (G) is sufficiently turned off.

The display control device 510 determines this time (tG
The clock signal (G1) and the clock signal (D1) are output in consideration of D).

If the time (tGD) is short, the display data of the next stage is applied to the drain signal line (D) before the gate electrode is not sufficiently turned off. This is applied to the liquid crystal layer, and as a result, the display quality of the TFT type liquid crystal display module is impaired.

In general, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, and as a result, an afterimage phenomenon is caused, and the life of the liquid crystal layer is shortened.

In order to prevent this, in a conventional TFT type liquid crystal display module, a driving voltage applied to a liquid crystal layer is changed to an alternating current at a certain time interval.
Therefore, the display control device 510 outputs, to the power supply circuit 520, an alternating signal (alternating timing signal) for alternating the drive voltage applied to the liquid crystal layer at certain time intervals.

Here, the term “alternating” means that the drain driver 530 is driven based on the drive voltage of the common electrode (counter electrode).
, That is, the drive voltage applied to the pixel electrodes of the liquid crystal layer is changed to the positive voltage side / negative voltage side at regular time intervals.

In the TFT type liquid crystal display module shown in FIG. 20, the cycle of the alternating is performed in units of one frame time.

[0054]

The TF shown in FIG.
2. Description of the Related Art In a conventional liquid crystal display device such as a T-type liquid crystal display module, a driving voltage based on display data is applied to all pixels in a row direction and a column direction for each frame, so that a liquid crystal display panel (TFT-LCD) is applied. ), An image is displayed on the display screen. In the conventional TFT type liquid crystal display device, it is necessary to drive all the pixels within one frame time.

Assume that a liquid crystal display panel (TFT-LCD)
If the number of display data transmitted from the main body computer is insufficient for all the pixels, the pixels for which the display data is insufficient are not driven in one frame, and the pixel displays some invalid data, or The control signal could not be generated.

For example, one pixel driven within one horizontal scanning period
The number of display data transmitted from the main computer is smaller than the number of pixels of the display line.
10 is configured to output a clock signal (D1) after counting a predetermined number of clock signals after a display timing signal is input, and to count a predetermined number of clock signals before the next display. The timing signal is input, and the clock signal (D1) is not output from the display control device 510.

As a result, a liquid crystal display panel (TFT)
-All the pixels of the LCD cannot be driven and the liquid crystal display panel (T
The image is not displayed on the FT-LCD.

In order to prevent this, the display control device 5
10 may be provided with a frame memory, and display data may be written to and read from the frame memory using different clock signals. However, it is necessary to provide the display control device 510 with a frame memory. In addition, there is a problem in that the scale of the display control device 510 is increased, and a compact liquid crystal display device cannot be configured.

When the display timing signal is Hi
When the clock signal (D2) changes from the gh level to the Low level, the output of the clock signal (D2) is forcibly stopped, and the clock signal (D
There is a method of outputting 1), but in this case, the time (tGD) shown in FIG. 24 cannot be guaranteed, and a high quality display image characteristic of the TFT liquid crystal display device cannot be obtained. was there.

A liquid crystal display panel (TFT-LCD)
If the number of display lines of the display data transmitted from the main computer is insufficient for the number of display lines, the conventional liquid crystal display device uses a simple shift scan driver as a gate driver. Therefore, it is impossible to drive the pixels of the display line for which the display data is insufficient in one frame.

Normally, in such a case, a drive voltage based on the display data of the next frame is applied to the display lines for which these display data are insufficient, and as a result, as shown in FIG. Display panel (TFT-L
The image displayed on the display screen of (CD) is a double display.

In the example shown in FIG. 25, the number of display lines of the display data transmitted from the main computer is clearly insufficient with respect to the number of display lines of the liquid crystal display panel (TFT-LCD). Liquid crystal display panel (TFT-
FIG. 3 is a diagram illustrating an example of a display screen of an LCD.

In order to prevent such double display,
As described above, the display control device 510 is provided with the frame memory, and the display data may be written into the frame memory and the display data may be read from the frame memory using different clock signals. 510 must have a frame memory,
There is a problem that the scale of the display control device 510 becomes large and a compact liquid crystal display device cannot be configured.

Further, in the conventional liquid crystal display device,
Since a simple shift scan driver is used as a gate driver, only one display line can be sequentially driven per display line within one frame time. For example, an interlace drive used in a television receiver or the like can be used. There is a problem that each display line cannot be driven by another driving method such as a driving method.

An object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a liquid crystal display device having a main body with respect to the number of pixels of one display line of a liquid crystal display panel. When the number of display data transmitted from the computer is insufficient, it is possible to generate a control signal at a timing proportional to the shortage without increasing the circuit scale and external dimensions of the display control device. To provide technology.

Another object of the present invention is to provide a liquid crystal display device in which the number of display data transmitted from the main computer is insufficient for the number of pixels of one display line driven within one horizontal scanning period. In this case, it is an object of the present invention to provide a technique capable of preventing double display without increasing a circuit scale and an outer dimension of a display control device.

Another object of the present invention is to provide a liquid crystal display device in which the number of display lines of display data within one frame time transmitted from the main computer is insufficient with respect to the number of display lines of the liquid crystal display panel. In this case, it is an object of the present invention to provide a technique capable of preventing double display without increasing a circuit scale and an outer dimension of a display control device.

Another object of the present invention is to provide a liquid crystal display device which can be employed in a television receiver or the like within one frame time without increasing the circuit scale and external dimensions of the display control device. It is an object of the present invention to provide a technology that can drive each display line by an arbitrary driving method such as an interlaced driving method.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0070]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A plurality of first signal lines, a plurality of second signal lines orthogonal to the plurality of first signal lines, a plurality of first signal lines, and a plurality of second signals A liquid crystal display panel having a plurality of pixels formed in a matrix to which a liquid crystal drive voltage is applied by lines, and taking in display data for one horizontal scanning period, and applying a video voltage based on the display data to the plurality of First driving means for outputting to one signal line, and second driving for outputting a scanning voltage for selecting a display line corresponding to display data for one horizontal scanning period to the plurality of second signal lines. Means for transmitting input display data to the first drive means, generating a control signal based on the input display control signal, and transmitting the control signal to the first drive means and the second drive means. And to the driving means, In the liquid crystal display device comprising a display control means for controlling driving the drive means and said second drive means, wherein the display control unit, of the liquid crystal display panel 1
A difference value calculating means for calculating a difference value between the number of pixels of the display line and the number of display data transmitted within one horizontal scanning period, and 1 for the number of pixels of one display line of the liquid crystal display panel.
When the number of display data items transmitted during the horizontal scanning period is small, based on the difference value obtained by the difference value calculation means,
It is characterized by comprising timing changing means for changing the timing of the control signal.

(2) In the means of (1), the display control signal generated by the display control means includes a clock signal for output timing control, a clock signal for display data latch, and a shift for every one horizontal scanning time. First counting means including at least one of clock signals, wherein the timing changing means counts the number of input clock signals from a start position at which the input display timing signal indicates a valid portion of display data; First change means for changing the timing of the output timing control clock signal based on the difference value obtained by the difference value calculation means and the number of clock signals counted by the first count means; Second changing means for changing the timing of the clock signal for use, and shifting for each horizontal scanning time. Characterized in that it comprises at least one of the third changing means for changing the timing of the clock signal.

(3) In the means of the above (2), the first changing means may be a start position at which the display timing signal indicates a valid portion of display data with respect to the number of pixels of one display line of the liquid crystal display panel. And a first storage unit for storing the number of clock signals until the output timing control clock signal is output, and the difference value calculation unit calculates the difference from the number of clock signals stored in the first storage unit. First calculating means for subtracting the difference value;
Comparing the number of clock signals counted by the first counting means with the value obtained by the first calculating means, and outputting an output timing control clock signal when the comparison result matches; A comparison circuit.

(4) In the means of the above (2), the second changing means may be a start position at which the display timing signal indicates a valid portion of display data with respect to the number of pixels of one display line of the liquid crystal display panel. Storing the number of clock signals for display data latch output from
Storage means, a second calculation means for subtracting the difference value obtained by the difference value calculation means from the number of clock signals stored in the second storage means, and a counter counted by the first counting means. A second comparison circuit for comparing the number of clock signals obtained with the value obtained by the second arithmetic means, and a second comparison circuit for determining whether the display timing signal indicates a valid portion of display data. Clock signal generating means (1) for outputting a clock signal as a display data latch clock signal until the comparison result in the circuit coincides.

(5) In the means of the above (2), the third changing means may be a start position at which the display timing signal indicates a valid portion of display data with respect to the number of pixels of one display line of the liquid crystal display panel. A third storage unit for storing the number of clock signals from when the shift clock signal is output to the shift clock signal, and a difference value obtained by the difference value calculation unit from the number of clock signals stored in the third storage unit. A third calculating means for subtracting, the number of clock signals counted by the first counting means,
And a clock signal generating means for outputting a shift clock signal whose voltage level changes when the result of comparison by the third comparing circuit matches the value obtained by the calculating means. (2).

(6) In the means of the above (1) to (5), the difference value calculating means sets the difference between the display timing signal and the effective portion of the display data within a period.
Second counting means for counting the number of input clock signals, fourth storage means for storing the number of pixels of one display line of the liquid crystal display panel, and a clock signal counted by the second counting means And a fourth calculating means for calculating a difference value between the number and the number of pixels of one display line of the liquid crystal display panel stored in the fourth storage means.

(7) In the means of (1) to (6), the display control device sends display data of a designated color to the first driving means before sending the display data, and The drive means stores display data of a designated color inputted from the display control device based on an output timing control clock signal inputted from the display control device, and thereafter inputted from the display control device. A display data latch unit for storing display data input from the display control device in synchronization with a display data latch clock signal;

(8) In the means of (1) to (7), the display control means outputs an initial value data of k bits in response to an input vertical synchronizing signal, and the display timing signal. And a k-bit register for latching the k-bit initial value data or the k-bit adder output data, and an addition for adding the k-bit register output data output from the register and the n-bit multi-line selection data. Generating means for generating display line selection data based on the k-bit register output data output from the register and the n-bit multiple line selection data; and generating a display line selection data latch clock signal. Generating a clock signal (3) to generate the display line selection data. A display line selection data latch unit for latching the display line selection data in synchronization with a switching clock signal; and a scan voltage based on the display line selection data latched by the display line selection data latch unit. 1 horizontal scanning time based on
And a voltage supply unit for supplying the voltage to the second signal line.

(9) In the means of the above (8), the generation means may convert the n-bit plural line selection data into n
M differs depending on the combination of bits (m is 2
(N + 1) -bit encoded data, and m bits output from the bit encoder by a shift amount determined by lower n bits of k-bit register output data output from the register. A right shifter that shifts the encoded data to the right and outputs shift encoded data, and k bits output from the register when N (N is 2 n) second signal lines are defined as one block. Assigning m-bit shift encode data output from the right shifter to a second signal line corresponding to the next two blocks of the block determined by the upper (kn) bits of the register output data of And allocating means for allocating “0” data to second signal lines corresponding to other blocks. That.

(10) In the means of (1) to (7), the display control means is configured to output k-bit first initial value data or k-bit first value data in accordance with a combination of an input vertical synchronizing signal and a field synchronizing signal. , 1 for the first initial value data
An initial value setting circuit for outputting k-bit second initial value data to which k is added, and the k-bit first initial value data, k-bit second initial value data or k-bit adder according to the display timing signal. A k-bit register for latching output data, k-bit register output data output from the register, and upper (l-2)
An adder for adding l-bit interlace drive line selection data in which the bit is '0' and the lower two bits are '1, 0'; a k-bit register output data output from the register; (1) generating means for generating display line selection data based on m-bit line selection data whose bits are “1” and lower (m−1) bits are “0”, and a display line selection data latch A clock signal generator (3) for generating a clock signal for display, wherein the second driving means latches the display line selection data in synchronization with the clock signal for display line selection data latch. A scanning voltage based on the display line selection data latched by the display line selection data latching means for one horizontal scanning time based on the shift clock signal; Characterized in that it comprises a voltage supply means for supplying to the serial second signal line.

(11) In the means of the above (10), the generation means may generate the m-bit line selection data by the shift amount determined by the lower n bits of the k-bit register output data output from the register. Shifter to the right to output shift line selection data, and a k-bit register output from the register when N (N is 2 n) second signal lines as one block. The m-bit shift line selection data output from the right shifter is assigned to a second signal line corresponding to a block next to a block determined by upper (kn) bits of the output data. Allocating means for allocating data of “0” to the second signal line corresponding to the block of (i).

According to the means (1), in the liquid crystal display device, the display control means sends the number of pixels of one display line of the liquid crystal display panel and one horizontal scanning period by the difference value calculating means. A difference value between the number of display data and the number of display data transmitted in one horizontal scanning period is smaller than the number of pixels of one display line of the liquid crystal display panel. Since the timing of the control signal is changed based on the difference value, even if the number of display data is insufficient with respect to the number of pixels of one display line of the liquid crystal display panel, the control signal is generated at a timing proportional to the shortage. Can be generated.

According to the means (2) to (6),
In the liquid crystal display device, the display control means obtains a difference value between the number of pixels of one display line of the liquid crystal display panel and the number of display data transmitted within one horizontal scanning period by the difference value calculating means. The counting means counts the number of input clock signals from a start position at which the input display timing signal indicates a valid portion of the display data, and calculates the difference value obtained by the difference value calculation means and the first value.
, At least one of the first changing means, the second changing means, and the third changing means, the timing of the output timing control clock signal, the timing of the display data latch Since at least one of the timing of the clock signal and the timing of the shift clock signal for each horizontal scanning time is changed, the number of display data is insufficient for the number of pixels of one display line of the liquid crystal display panel. In this case, the output timing control clock signal, the display data latch clock signal, and the shift clock signal for each horizontal scanning time can be generated at a timing proportional to the shortage. It is possible to make the time interval constant.

According to the means (7), in the liquid crystal display device, the display control means sends the display data of the designated color to the first drive means before sending the display data, and the first drive means Stores the display data of the designated color in the display data latch means, and then stores the display data input from the display control device. Therefore, among the pixels of one display line of the liquid crystal display panel, The designated color can be displayed on the pixels having insufficient display data, and the display quality of the display image displayed on the liquid crystal display panel can be improved.

According to the above (8) or (9),
In the liquid crystal display device, the display control means further includes an initial value setting circuit for outputting initial value data, a register, an adder, and a generating means for generating display line selection data. The initial value data is output from the initial value setting circuit, the initial value data or the adder output data is latched in the register by the input display timing signal, and the register output data output from the register and the multiple line selection data are added to the adder. And generating means for generating display line selection data based on the register output data output from the register and the plurality of line selection data, and transmitting the display line selection data from the display control means to the second driving means. Outgoing, second
The display line selection data is latched in synchronization with the clock signal for display line selection data latch, and the scanning voltage based on the latched display line selection data is changed from the second driving means for one horizontal scanning time. Since the signals are supplied to all the second signal lines, a plurality of display lines of the liquid crystal display panel can be driven within one horizontal scanning time.

According to the means (10) or (11), in the liquid crystal display device, the display control means further comprises:
A combination of a vertical synchronizing signal and a field synchronizing signal inputted from the initial value setting circuit, comprising: an initial value setting circuit for outputting initial value data; a register; an adder; and a generating means for generating display line selection data. And outputs k-bit first initial value data or k-bit second initial value data obtained by adding 1 to the first initial value data, and registers the first initial value in a register according to an input display timing signal. The data, the second initial value data or the output data of the adder are latched, and the register output data output from the register by the adder and the upper (l-2) bits are "0" and the lower 2 bits are "1, 0" And n-bit line selection data at the time of interlace driving, and the register output data output from the register by the generation means and the upper (1) bit being “1” and lower (M-1) The display line selection data is generated based on the m-bit line selection data whose bit is "0", and the display line selection data is transmitted from the display control means to the second drive means. The second driving means latches the display line selection data in synchronization with the display line selection data latch clock signal, and changes the scanning voltage based on the latched display line selection data for one horizontal scanning time for the second horizontal scanning time. Since the driving means supplies all the second signal lines, each display line of the liquid crystal display panel can be driven by the interlace driving method within one frame time.

[0087]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention in which the present invention is applied to a TFT type liquid crystal display module will be described in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[Embodiment 1] The TFT type liquid crystal display module of the embodiment of the present invention transmits the number of pixels of one display line of a liquid crystal display panel (TFT-LCD) from the main computer side. When the number of pieces of display data to be displayed is insufficient, the timing of the display control signal output from the display control device 510 is changed using the shortage as a correction value.
This is different from the T-mode liquid crystal display module.

The TFT-type liquid crystal display module according to the embodiment of the present invention has an interface section 500 like the conventional TFT-type liquid crystal display module shown in FIG.
The interface unit 500 includes a liquid crystal display panel (TFT-LCD), a drain driver 530, and a gate driver, and includes a display control device 510 and a power supply circuit 520.

FIG. 1 shows a liquid crystal display panel (TFT) in a TFT type liquid crystal display module according to an embodiment of the present invention.
FIG. 2 is a diagram showing an equivalent circuit of the LCD.

In FIG. 21, which is an equivalent circuit of the conventional example, an additional capacitance (CADD) is formed between the gate signal lines (G) and the source electrodes in all stages, but the equivalent circuit shown in FIG. The difference is that a storage capacitor (CSTG) is formed between the common signal line (COM) and the source electrode.

The present invention can be applied to both,
In the former method, the pulse of the gate signal line (G) in all stages jumps into the pixel electrode via the additional capacitance (CADD), whereas in the latter method, there is no jump, so that a better display is possible. .

Next, a method of generating clock signal (D1), clock signal (D2) and clock signal (D1) in display control device 510 according to the embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a schematic configuration of a clock signal (D1), a clock signal (D2) and a circuit portion for generating clock signal (D1) in display control device 510 according to the embodiment of the present invention. is there.

In the figure, a counter 202, a register 205, a storage means (4) 206, and a subtractor 208
The difference value calculation means of the present invention is configured.

The storage means (1) 211 and the adder 21
4. Multiplexer 217 and first comparison circuit 220
Constitutes a first changing means of the present invention.

Similarly, storage means (2) 210, adder 2
13, the multiplexer 216, the second comparison circuit 219, and the JK flip-flop circuit 222 constitute second modification means of the present invention, and the JK flip-flop circuit 222 composes the second modification circuit. The clock signal generating means (1) in the means is constituted.

Similarly, storage means (3) 209, adder 2
12, the multiplexer 215, the third comparison circuit 218, and the JK flip-flop circuit 221 constitute a third changing means of the present invention, and the JK flip-flop circuit 221 performs the third changing operation. And a clock signal generating means (2).

The AND circuit 201 shown in FIG. 2 outputs a clock signal when the display timing signal is at a high level.

The counter 202 counts the number of clock signals output from the AND circuit 201 and is cleared by the horizontal synchronizing signal.

The rising detection circuit 203 outputs a rising detection pulse when detecting the rising of the display timing signal.

The number of clock signals counted by the counter 202 is latched in the register 205 by the rising detection pulse from the rising detecting circuit 203.

Therefore, the register 205 latches the number of clock signals while the display timing signal maintains the High level.

The storage means (4) 206 such as a register includes
A liquid crystal display panel (TFT) driven within one horizontal scanning period
The number of pixels of one display line of the LCD (hereinafter, referred to as a horizontal pixel number constant) is stored.

The horizontal pixel number constant stored in the storage means (4) 206 is subtracted by a subtracter 208 from the number of clock signals latched in the register 205.

When the number of display data transmitted from the main body computer is insufficient for the horizontal pixel number constant of the liquid crystal display panel (TFT-LCD), the subtraction result in the subtracter 208 becomes negative, The upper bit (MSB) of is “1”.

The result of the subtraction by the subtracter 208 is input to the adders (212, 213, 213).

The storage means (1) 211 such as a register includes:
The original number of clock signals (1) from the input of the display timing signal to the output of the clock signal (D1) corresponding to the horizontal pixel number constant of the liquid crystal display panel (TFT-LCD) is stored.

If the result of the subtraction by the subtracter 208 is negative, the result of the subtraction by the subtractor 208 is subtracted from the original number of clock signals (1) by the adder 214.

The result of addition by the adder 214 and the original number of clocks (1) are input to the multiplexer 217.

The multiplexer 217 outputs the result of the addition performed by the adder 214 when the result of the subtraction by the subtracter 208 is negative (the MSB of the result of the subtraction is “1”).

The falling detection circuit 204 outputs a detection pulse when detecting the falling of the display timing signal.

The counter 207 uses the clock signal as a count and is cleared by a detection pulse from the falling detection circuit 204.

The count value of the counter 207 is the first
The comparison circuit 220 outputs a clock signal (D1) when the count value of the counter 207 matches the output from the multiplexer 217.

The storage means (2) 210 such as a register includes:
The original number (2) of clock signals output after the display timing signal is input, corresponding to the horizontal pixel number constant of the liquid crystal display panel (TFT-LCD) is stored.

If the result of the subtraction by the subtracter 208 is negative, the result of the subtraction by the subtractor 208 is subtracted from the original number of clock signals (2) by the adder 213.

The result of addition by the adder 213 and the original number of clocks (2) are input to the multiplexer 216.

Multiplexer 216 outputs the result of addition by adder 213 when the result of subtraction in subtractor 208 is negative (the MSB of the result of subtraction is “1”).

The second comparison circuit 219 is provided by the counter 2
When the count value of 07 and the output from the multiplexer 216 match, a pulse is output.

The pulse from the comparison circuit 219 is J-
The signal is input to the J input terminal of the K-type flip-flop circuit 222.

The JK flip-flop circuit 2
A rise detection pulse from the rise detection circuit 214 is input to the K input terminal 22.

In the JK type flip-flop circuit, when "High level" is input to the J input terminal, its output (Q) becomes High level, and "High level" is input to the K input terminal. Then, the output (Q) becomes Low level, and if "Low level" is input to the J input terminal and the K input terminal, the previous state is maintained.

Therefore, the output terminal (Q) of the JK type flip-flop circuit 222 outputs a high level when the display signal becomes high level, and outputs a pulse signal which becomes low level by a pulse from the comparison circuit 219. .

This JK type flip-flop circuit 22
2 from the output terminal (Q) of the AND circuit 22
3, the clock signal (D2) is output while the output terminal (Q) of the JK flip-flop circuit 222 maintains the High level.

The storage means (3) 209 such as a register includes:
The original number (3) of clock signals from the input of the display timing signal to the output of the clock signal (G1) corresponding to the horizontal pixel number constant of the liquid crystal display panel (TFT-LCD) is stored.

If the subtraction result in the subtractor 208 is negative, the adder 212 subtracts the subtraction result in the subtractor 208 from the original number of clock signals (3).

The result of addition by the adder 212 and the original number of clocks (3) are input to the multiplexer 215.

The multiplexer 215 outputs the addition result of the adder 212 when the result of the subtraction in the subtractor 208 is negative (the upper bit (MSB) of the subtraction result is “1”).

The third comparison circuit 218 is provided with the counter 2
When the count value of 07 and the output from the multiplexer 215 match, a pulse is output.

The pulse from the comparison circuit 218 is J-
The signal is input to the J input terminal of the K-type flip-flop circuit 221.

The JK flip-flop circuit 2
A rise detection pulse from the rise detection circuit 204 is input to the K input terminal 21.

Therefore, from the output terminal (Q) of the JK flip-flop circuit 221, the clock signal (G 1) which becomes High level when the display signal becomes High level and which becomes Low level by a pulse from the comparison circuit 218. Is output.

FIG. 3 is a timing chart showing the clock signal (D1), the clock signal (D2) and the clock signal (D1) generated by the circuit configuration of FIG. 2, and the display control signal from the main computer. It is.

As shown in FIG. 3, according to the circuit configuration shown in FIG. 2, the number of display data transmitted from the main body computer is smaller than the number of pixels of one display line of the liquid crystal display panel (TFT-LCD). When the difference is insufficient, the difference value is obtained by the subtractor 208, and based on the difference value, the clock signal (G
The fall timing of 1) is made faster, and similarly, the stop of the clock signal (D2) is made faster, and the clock signal (D1) is generated faster.

Thus, the liquid crystal display panel (TFT-L
Even when the number of display data transmitted from the main computer is insufficient with respect to the number of pixels of one display line of CD), the time (from the fall of the clock signal (G1) to the rise of the clock signal (D1)) tGD) can be kept constant.

In the circuit configuration shown in FIG. 2, when the number of display data transmitted from the main computer is insufficient for the number of pixels of one display line of the liquid crystal display panel (TFT-LCD), one horizontal line is provided. Display data is not transmitted to the data latch units of all the drain drivers 530 during the scanning period.

In the data latch section of the drain driver 530 where the display data is insufficient, display data in the next horizontal scanning period or invalid data is latched.

Therefore, in the circuit configuration shown in FIG. 2, the right end of the display screen of the liquid crystal display panel (TFT-LCD) is
For example, as shown in FIG. 4, the same image as that on the left side of the display screen is displayed twice, or an invalid image is displayed.

Thus, the liquid crystal display panel (TFT-L
The display quality of the display screen displayed on the CD) is impaired.

In the example shown in FIG. 4, the number of pixels in one display line of a liquid crystal display panel (TFT-LCD) is
It is a figure showing an example of a display screen of a liquid crystal display panel when the number of display data transmitted from the main part computer side is clearly insufficient.

FIG. 5 is a schematic block diagram showing an example of the drain driver 530 for preventing the double display image shown in FIG. 3, and FIG. 6 shows the clock signal (D1) and the clock signal shown in FIG. (D2) and a diagram showing a timing chart of display data.

FIG. 5 is a diagram showing a circuit configuration of a data latch unit for the R color of the data latch unit of the drain driver 530 shown in FIG. 22. The shift register circuit 232 shown in FIG. A signal for inputting data of the input register circuit 554 is generated based on the clock signal (D2) input from the CPU.

The data fetch signal is supplied to the OR circuit 2
The input register circuit 553 inputs the 6-bit display data in synchronization with the clock signal (D2) input from the display control device 510 based on the data capture signal. Latch.

The storage register circuit 554 latches the display data in the input register circuit 553 according to the clock signal (D1) input from the display control device 510.

The operation so far is the same as the conventional data fetch operation.

However, in the circuit configuration shown in FIG.
The shift register circuit 232 is reset when the clock signal (D1) is input.

The inverted clock signal (bar D 1) inverted by the inverter 241 is input to the input register circuit 553 via the OR circuit 242.

Therefore, the inverted clock signal (bar D
As shown in FIG. 6, by transmitting display data of a designated color, for example, black display data to the data bus 533 in synchronization with the rising edge of 1), all input register circuits 553 initially receive black data. Is latched.

After that, the input register circuit 553 replaces the black display data with the display control device 5 based on the data fetch signal output from the shift register circuit 232.
In synchronization with the clock signal (D2) input from 10,
6-bit display data is latched.

Thus, the liquid crystal display panel (TFT-L
When the number of display data transmitted from the main computer is insufficient for the number of pixels of one display line of CD),
Black display data is latched in the data latch section of the drain driver 530 where the display data is insufficient.

Then, during the next horizontal scanning period, the liquid crystal display panel (TFT-LC) is displayed based on the display data latched by the data latch section of the drain driver 530.
An image is displayed in D).

Therefore, the drain driver 5 shown in FIG.
The use of the liquid crystal display panel (TFT-
At the right end of the display screen of the LCD, a black image is displayed.

Thus, the liquid crystal display panel (TFT-L
The display quality of the display screen displayed on the CD) can be improved.

The display timing signal is 1
This is a signal indicating which position has valid display data within the frame time. Since this display timing signal is an existing signal, no special interface is required.

[Embodiment 2] FIG. 7 is a block diagram showing a schematic configuration of a TFT type liquid crystal display module according to another embodiment of the present invention.

In the TFT type liquid crystal display module of the present embodiment, the interface section 500 includes a display control device 510 and a power supply circuit 520, similarly to the conventional TFT type liquid crystal display module shown in FIG.

The liquid crystal display module according to the embodiment of the present invention includes a liquid crystal display panel (TFT-LCD) of the equalizing circuit shown in FIG. 1 or FIG.

The TFT type liquid crystal display module according to the embodiment of the present invention uses a conventional TFT as a gate driver.
Instead of using a simple shift scan driver that can drive only one display line per one display line sequentially used in a liquid crystal display module of a system, a column driver used in a simple matrix type liquid crystal display device is used. This is different from the conventional TFT type liquid crystal display module shown in FIG.

Therefore, in the TFT type liquid crystal display module according to the embodiment of the present invention, the display control device 51 is used.
0 to a column driver (gate driver), a gate selection data and a gate selection data latch clock signal (G2) which is a display control signal for latching the gate selection data (hereinafter referred to as a clock signal (G2)).
Is sent.

FIG. 8 is a block diagram showing a schematic configuration of a column driver used in a simple matrix type liquid crystal display device.

In the figure, reference numeral 140 denotes a column driver.
51, bit latch circuit 152, line latch circuit 15
3, a level shift circuit 514 and an output circuit 155.

The shift register circuit 151 has a display data latch clock signal (C) input from the display control device.
Based on L2), a signal for capturing data of the bit latch circuit 152 is generated and output to the bit latch circuit 152.

The bit latch circuit 152 latches 8-bit display data (Din) input from the display control device based on the data fetch signal input from the shift register circuit 151.

The line latch circuit 153 latches the display data captured by all the bit latch circuits 152 based on the output timing control clock signal (CL1), and outputs the display data to the level shift circuit 154.

The level shift circuit 154 converts the voltage level of the display data input from the line latch circuit 153 into a high voltage level for driving the liquid crystal, and outputs it to the output circuit 155.

Output circuit 155 is supplied with a four-level data signal line drive voltage from a power supply circuit. Output circuit 155 outputs one of the four-level data signal line drive voltages supplied from power supply circuit 502. One is the level shift circuit 1
The selection is performed based on the display data and the AC signal input from 54 and output to each segment electrode (data signal line).

As described above, in the column driver shown in FIG. 8, data signal lines (segment electrodes or video signal lines)
It is possible to output a drive voltage for driving the liquid crystal to all output terminals connected to.

Therefore, as a gate driver, FIG.
, The gate selection data considering the number of display lines to be driven and the number of simultaneously driven display lines is latched in the bit latch circuit 152, and the bit latch circuit 152 is switched at the timing when the conventional display line is switched. Is latched in the line latch circuit 153, and the scanning voltage, that is, the driving voltage (positive bias voltage and negative voltage) input from the gate electrode voltage generation circuit 524 is latched based on the gate selection data. By outputting the bias voltage to the gate signal line (G), a plurality of display lines can be driven simultaneously.

[0170] Similarly, it is possible to drive the display lines by the interlaced driving method adopted in a television receiver or the like.

FIG. 9 is a circuit diagram of a circuit portion for generating gate selection data to be sent to column driver 140 and clock signals (G1, G2) as display control signals in display control device 510 according to the embodiment of the present invention. It is a block diagram showing a schematic structure.

In the figure, bit encoder (2) 3
04, the right shifter 305, and the gate selection data write sequencer 306 constitute a generation unit for generating display line selection data, and the gate selection data write sequencer 306 constitutes an allocation unit in the generation unit.

The initial value setting circuit 300 generates 10-bit initial value setting data based on each control signal (vertical synchronization signal, field synchronization signal, interlace driving instruction signal and display timing signal) input from the main computer. , And the 10-bit adder output data output from the adder 303 are selected and output.

A 10-bit register 301 latches 10-bit output data output from the initial value setting circuit 300 based on a display timing signal.

The adder 303 adds the selector output data output from the selector 302 and the register output data output from the register 301.

FIG. 10 is a truth table showing the truth values of selector 302 shown in FIG.

As shown in FIG. 10, the selector 302
When the interlace drive instruction signal is at a low level (hereinafter, referred to as
Called "0". ), As selector output data,
Adder 30 selects 3-bit multiple line selection data and
3 when the interlace drive instruction signal is at a high level (hereinafter, referred to as “1”), as selector output data, a 3-bit interlace of '0, 1, 0' (2 in decimal number) is output. The line selection data at the time of driving is selected and output to the adder 303.

9 to 3 bits of the register output data output from the register 301, that is, the upper 7 bits (PR
[6: 0]) is the gate selection data write sequencer 3
06.

[0179] Bits 2 to 0 of the register output data output from the register 301, that is, lower three bits are input to the right shifter 305, and determine the shift amount of the right shifter 305.

The 3-bit multiple-line selection data can be changed for each display timing signal (one horizontal scanning time). The 3-bit multiple-line selection data is input to the bit encoder (2) 304 and 2) 304 converts the 3-bit multi-line selection data into 16-bit encoded data (B2 [15:
0]).

FIG. 11 is a truth table showing the truth values of bit encoder (2) 304 shown in FIG.

As shown in FIG. 11, the bit encoder (2) 304 converts the 3-bit multi-line selection data from '0, 0, 0' to '1, 1, 1' into lower 8 bits (B2 [ 7: 0]) is' 0,0,0,0,0,0,0,
0 ', the upper 8 bits (B2 [15: 8]) are' 0,
0,0,0,0,0,0,0 'to' 1,1,1,
1,1,1,1,0 'encoded data (B2
[15: 0]).

Here, the encoded data (B2 [15:
0]), the upper 8 bits (B2 [15: 8]) are '0,
When the number is 0,0,0,0,0,0,0 ', the number of display lines to be driven (selected) is 0, and' 1,0,0,0 '.
When the number is 0,0,0,0,0 ', the number of display lines to be driven is 1, and likewise,' 1,1,1,1,1,1,1,
When it is 1, 0 ', it indicates that the number of display lines to be driven is seven.

The 16-bit encoded data (B2
[15: 0]) is input to the right shifter 305, and the right shifter 305 shifts the shift right by a shift amount determined by the lower three bits of the register output data output from the register 301, and shifts the data by 16 bits. It is converted into encoded data (OR [15: 0]).

The shift encoded data (OR [1
5: 0]) is the gate select data write sequencer 30.
6 is input.

FIG. 12 shows an initial value setting circuit 30 shown in FIG.
FIG. 2 is a block diagram showing a schematic configuration of a block 0.

A bit encoder (1) 310 shown in FIG.
Outputs 10-bit initial value data based on a combination of input control signals (vertical synchronization signal, field synchronization signal, and interlace drive instruction signal).

FIG. 13 is a truth table showing the truth values of bit encoder (1) 310 shown in FIG.

As shown in FIG. 13, bit encoder (1) 310 outputs an interlace drive instruction signal [1].
When both the vertical synchronizing signal and the field synchronizing signal are [1], '0,0,0,0,0,0,0,
When 10-bit initial value data of 0, 0, 0 'is output, and the interlace drive instruction signal is [1], the vertical synchronization signal is [0], and the field synchronization signal is [1], 1 of '0,0,0,0,0,0,0,0,0,1'
Outputs 0-bit initial value data.

Further, the bit encoder (1) 310
When the interlace driving instruction signal is [0] and the vertical synchronizing signal is [1], '0, 0, 0, 0, 0, 0, 0, 0, 0 regardless of the value of the field synchronizing signal. , 0'1
When 0-bit initial value data is output, and when both the vertical synchronizing signal and the field synchronizing signal are [0], the initial value data is not output regardless of the value of the interlace driving instruction signal.

The initial value data output from the bit encoder (1) 310 is input to the data input terminal (D) of the D-type flip-flop circuit 312.

The vertical synchronizing signal and the field synchronizing signal are input to the OR circuit 311, and the output of the OR circuit 311 is delayed for a predetermined time by the delay circuit 313, that is, the logical value of the bit encoder (1) 310 is determined. Is input to the clock terminal (CK) of the D-type flip-flop circuit 312.

Therefore, bit encoder (1) 31
The initial value data output from 0 is output to the delay circuit 313
Is synchronized with the output of the OR circuit 311 delayed by a predetermined time, and is taken into the D-type flip-flop circuit 312 and output from the output terminal (Q) of the D-type flip-flop circuit 312.

The initial value data output from the output terminal (Q) of the D-type flip-flop circuit 312 is input to one input terminal of the multiplexer 316, and the other input terminal of the multiplexer 316 is connected to the adder 303. , And the 10-bit adder output data output from.

When the value of the output terminal (Q) of the RS flip-flop circuit 315 is "0", the multiplexer 316 selects the adder output data from the adder 303 and outputs it to the register 301. When the value of the output terminal (Q) of the RS flip-flop circuit 315 is "1", the initial value data output from the output terminal (Q) of the D flip-flop circuit 312 is selected. And outputs it to the register 301.

RS flip-flop circuit 315
Means that when the input terminal (S) is "1", its output terminal (Q) is "1", and when the input terminal (R) is "1", its output terminal (Q) is " 0 ".

Here, a vertical synchronizing signal or a field synchronizing signal delayed by a predetermined time by the delay circuit 313 is input to the input terminal (S) of the RS flip-flop circuit 315.
The initial value data output from the output terminal (Q) of the D-type flip-flop circuit 312 is selected based on the vertical synchronizing signal or the field synchronizing signal delayed by the delay circuit 313 for a predetermined time, and is output to the register 301.

Further, the RS flip-flop circuit 3
Since a display timing signal delayed by a predetermined time by the delay circuit 314 is input to the input terminal (R) of the multiplexer 15, the multiplexer 316
The output data from the adder 303 is selected and output to the register 301 based on the display timing signal delayed by a predetermined time in 14.

FIG. 14 is a block diagram showing a schematic configuration of gate selection data write sequencer 306 shown in FIG.

Gate selection data write sequencer 306
Are the control means 320 and the gate selection data generation means 32
3. It comprises a clock signal generation means (3) 321 and a clock signal generation means (4) 322.

The control means 320 controls the upper 7 bits (PR) of the display timing signal and the register output data.
[6: 0]) is input and the gate selection data generating means 3
23, and controls the clock signal generation means (3) 321 and the clock signal generation means (4) 322.

The shift select data (OR [15: 0]) is input to the gate selection data generating means 323,
In accordance with an instruction from the control unit 320, gate selection data for each display line is generated every horizontal scanning time, and transmitted to the column driver 140 via the bus line 143.

The clock signal generating means (4) 322, in accordance with an instruction from the control means 320,
Bit latch circuit (the bit latch circuit 15 shown in FIG. 8)
In 2), a clock signal (G2) for latching gate selection data is generated and sent to the column driver 140 via the signal line 142.

The clock signal generating means (3) 321 responds to the instruction from the control means 320 and
The gate selection data captured by the bit latch circuit of FIG.
53) to generate a clock signal (G1) which is a display control signal for outputting a scanning voltage based on the gate selection data to the gate signal line (G).
1 to the column driver 140.

FIG. 15 is a flowchart showing a processing procedure of the gate selection data write sequencer 306 shown in FIG.

Next, the processing procedure of the gate selection data write sequencer 306 will be described with reference to FIG.

Gate select data write sequencer 306
Operates by inputting the display timing signal,
First, the variable (GCONT) in the control means 320 is set to the value of the upper 7 bits (PR [6: 0]) of the register output data (step 351).

Next, the control means 320 sets the upper 7 bits (PR [6: 0]) of the register output data to '0,0,
0, 0, 0, 0, 0 ′ (step 3
52).

At step 352, the upper 7 bits (PR [6: 0]) of the register output data are set to '0, 0, 0, 0,
If it is not 0,0,0 ', the gate selection data generating means 323 generates'0,0,0,0' as gate selection data for eight display lines based on an instruction from the control means 320.
0, 0, 0, 0, 0 'data is generated and the bus line 1
The data is sent to the column driver 140 via 43 (step 356).

At this time, the clock signal generating means (4) 32
2 generates a clock signal (G2) based on an instruction from the control unit 320 and sends it to the column driver 140 via the signal line 142.

As a result, "0" is written to the bit latch circuits corresponding to the predetermined eight display lines of the column driver 140.

Next, the control means 320 subtracts 1 from the upper 7 bits (PR [6: 0]) of the register output data (step 357).

Steps 356 and 357 are performed by
Upper 7 bits of register output data (PR [6: 0])
Is repeated until '0,0,0,0,0,0,0'.

At step 352, the upper 7 bits (PR [6: 0]) of the register output data are set to '0,0,0,0,
In the case of 0, 0, 0 ', the gate selection data generation means 323 converts the shift encode data (OR [15: 0]) as gate selection data for eight display lines based on an instruction from the control means 320. Upper 8 bits (OR [1
5: 8]) and sends it to the column driver 140 via the bus line 143 (step 35).
3).

Similarly, clock signal generating means (4) 32
2 generates a clock signal (G2) based on an instruction from the control unit 320 and sends it to the column driver 140 via the signal line 142.

As a result, the data of the upper 8 bits (OR [15: 8]) of the shift encode data (OR [15: 0]) is written to the bit latch circuits corresponding to the predetermined 8 display lines of the column driver 140. .

Next, the gate selection data generating means 323
However, based on the instruction from the control means 320, the lower 8 bits (OR [7:]) of the shift encode data (OR [15: 0]) are used as gate selection data for 8 display lines.
0]) and sends it to the column driver 140 via the bus line 143 (step 354).

Similarly, clock signal generating means (4) 32
2 generates a clock signal (G2) based on an instruction from the control unit 320 and sends it to the column driver 140 via the signal line 142.

As a result, the lower 8 bits (OR [7: 0]) of the shift encode data (OR [15: 0]) are written to the bit latch circuits corresponding to the predetermined 8 display lines of the column driver 140. .

Next, the control means 320 controls the variable (GCON
T) is added with 2 (step 355), and the variable (GCON
T) and the value obtained by dividing the number of display lines by 8 is determined (step 358).

At step 358, the variable (GCONT) is smaller than the value obtained by dividing the number of display lines by 8, or
If the variable (GCONT) is the same as the value obtained by dividing the number of display lines by 8, the gate selection data generation means 323
However, based on an instruction from the control means 320, '0,0,0,0,0,
The data of 0,0,0 'is generated and sent to the column driver 140 via the bus line 143 (step 36).
0).

Similarly, clock signal generating means (4) 32
2 generates a clock signal (G2) based on an instruction from the control unit 320 and sends it to the column driver 140 via the signal line 142.

As a result, "0" is written to the bit latch circuits of the column driver 140 corresponding to the predetermined eight display lines.

Next, the control means 320 controls the variable (GCON
T) is incremented by 1 (step 361).

Steps 360 and 361 are performed by
Repeat until the variable (GCONT) becomes larger than the value obtained by dividing the number of display lines by eight.

Thus, the display line to be driven (selected) can be set to “1”, and the other display lines can be set to “0”.

At step 359, if the variable (GCONT) is larger than the value obtained by dividing the number of display lines by 8, 1
Assuming that the horizontal gate selection data has been completed, the clock signal generation means (3) 321 changes the clock signal (G1) to the signal line 141 at the timing of switching the conventional gate based on an instruction from the control means 320. The data is sent to the column driver 140 via the interface (step 360).

In the flowchart showing the processing procedure of the gate selection data write sequencer 306 shown in FIG. 15, the variable (GCONT) is set to 0 in step 351, and GCONT = GCONT +
The first process may be added.

Next, a driving method at the time of driving a plurality of display lines in the embodiment of the present invention will be described.

In the embodiment of the present invention, when a plurality of display lines are driven, the interlace drive instruction signal is “0”, so that when the vertical synchronization signal is “1”, the bit encoder (1) 310 0,0,0,0,0,0,
It outputs 10-bit initial value data of 0, 0, 0 '.

Here, the initial value data output from the bit encoder (1) 310 is taken into the D-type flip-flop circuit 312 in synchronization with the vertical synchronization signal delayed by the delay circuit 313 for a predetermined time, and It is output from the output terminal (Q) of the flip-flop circuit 312.

The vertical synchronizing signal delayed by the delay circuit 313 for a predetermined time is input to the input terminal (S) of the RS flip-flop circuit 315, and the output terminal of the RS flip-flop circuit 315 Since (Q) becomes “1”, the multiplexer 316 selects the initial value data output from the output terminal (Q) of the D-type flip-flop circuit 312 and outputs it to the register 301.

Thereafter, when the display timing signal is input, the initial value data output from the multiplexer 316 is latched in the register 301.

That is, at the time of driving a plurality of display lines, the register 301 is cleared by the vertical synchronizing signal.

When the interlace drive instruction signal is "0"
Therefore, the selector 302 selects the 3-bit multi-line selection data and outputs it to the adder 303,
03 adds the register output data output from the register 301 and the 3-bit multi-line selection data.

Further, a display timing signal delayed by a predetermined time by the delay circuit 314 is sequentially input to the input terminal (R) of the RS flip-flop circuit 315. Since the output terminal (Q) becomes “0”, the multiplexer 316
Selects the output data output from the adder 303 and outputs it to the register 301.

Thus, each time a display timing signal is sequentially input to the register 301, a plurality of initial value data output from the output terminal (Q) of the D-type flip-flop circuit 312 are added to the register 301 for each display timing signal. The data to which the line selection data is added is held.

Therefore, the 10-bit register output data output from register 301 indicates the number of display lines driven up to the present time, and the upper 7 bits (P
R [6: 0]) indicates the number of blocks driven up to the present time when one block is set to 8 display lines.

[0239] The lower three bits indicate the number of the display line in one block which has been driven up to the present time.

Therefore, the right shifter 305 converts the encoded data (B2 [15: 0]) into the lower 3 bits of the 10-bit register output data output from the register 301.
By shifting by the shift amount determined by the bit data, the number of display lines determined by the multiple line selection data from the display line next to the display line driven so far in the block to be driven this time It can be driven (selected).

In this case, depending on a plurality of line selection data, there is a case where “1” (selection) data continues over the block next to the block to be driven this time, so that the encoded data is 16-bit data. ing.

Now, a vertical synchronizing signal is input, and then the first
When the third display timing signal is input, the register output data output from the register 301 becomes D
Value data '0,0,0,0,0,0,0' output from the output terminal (Q) of the flip-flop circuit 312
0, 0, 0, 0 'and the lower 3 bits of the register output data.
The bit becomes '0,0,0'.

Here, when the plural line selection data is' 0,
At the time of 0, 1 ', the encoded data (B2 [15:
0]), the upper 8 bits (B2 [15: 8]) are '1,
0,0,0,0,0,0,0 '.

In this case, since the shift amount of the right shifter 305 is 0, the upper 8 bits (OR [15: 8]) of the shift encode data are '1, 0, 0, 0, 0, 0,
0,0 '.

The upper 7 bits (PR [6: 0]) of the register output data are '0,0,0,0,0,0,0'.
Therefore, the gate selection data write sequencer 306
Writes “1” into the bit latch circuit of the column driver 140 corresponding to the first display line in the first block, and writes “0” into the bit latch circuit of the column driver 140 corresponding to the other display lines. Is written.

When the next display timing signal is input, the register output data output from register 301 is the adder output data '0,0,0,0,0,0,0 output from adder 303. , 0,0,1 ',
The lower three bits of the register output data are '0, 0, 1'.

Here, when the plural line selection data is' 0,
0, 1 ', the encoded data (B2 [1
5: 0]), the upper 8 bits (B2 [15: 8]) are '1,0,0,0,0,0,0,0'.

In this case, since the shift amount of the right shifter 305 is 1, the upper 8 bits (OR [15: 8]) of the shift encode data are '0, 1, 0, 0, 0,
0,0,0 '.

The upper 7 bits (PR [6: 0]) of the register output data are '0,0,0,0,0,0,0'.
Therefore, the gate selection data write sequencer 306
Writes “1” in the bit latch circuit of the column driver 140 corresponding to the second display line in the first block, and writes “0” in the bit latch circuit of the column driver 140 corresponding to the other display lines. Is written.

When the next display timing signal is input, the register output data output from register 301 is the adder output data '0,0,0,0,0,0,0 output from adder 303. , 0,1,0 ',
The lower three bits of the register output data are '0, 1, 0'.

Here, the plural line selection data is' 0,
1, 0 ′, the encoded data (B2 [1
5: 0]), the upper eight bits (B2 [15: 8]) are '1,1,0,0,0,0,0,0'.

In this case, since the shift amount of the right shifter 305 is 2, the upper 8 bits (OR [15: 8]) of the shift encode data are '0, 0, 1, 1, 0,
0,0,0 '.

The upper 7 bits (PR [6: 0]) of the register output data are '0,0,0,0,0,0,0'.
Therefore, the gate selection data write sequencer 306
Writes "1" into the bit latch circuits of the column drivers 140 corresponding to the third and fourth display lines in the first block, and writes the bit latches of the column drivers 140 corresponding to the other display lines. Write "0" to the circuit.

Similarly, "1" is written to the bit latch circuit of the column driver 140 corresponding to the display line to be driven (selected), and the bit latch circuit of the column driver 140 corresponding to the other display lines is written. "0"
To write.

FIG. 16 is a timing chart of a display control signal from the main computer shown in FIG. 7 and a display control signal generated by the display control device 510 when driving a plurality of display lines according to the embodiment of the present invention. It is.

In the TFT type liquid crystal display module according to the embodiment of the present invention, similarly to the conventional TFT type liquid crystal display module, the horizontal direction, that is, the display control device 51 is used.
From 0, display data and clock signals (D1, D2) as display control signals are sent to the drain driver 530.

In this case, the display data sent from the display control device 510 to the drain driver 530 and the timing of each display control signal are the same as those of the conventional TFT type liquid crystal display module.

However, 8-bit gate selection data and clock signals (G1 and G2) as display control signals are sent to the drain driver 530 in the vertical direction, that is, from the display control device 510.

In the TFT type liquid crystal display module according to the embodiment of the present invention, as described above, when the first display timing signal is input after the input of the vertical synchronizing signal, the display control device 510 changes this. Judge as the display start position, and output 8-bit gate selection data to the column driver 140 via the bus line 143.

At this time, a clock signal (G2) for latching gate selection data in a bit latch circuit (bit latch circuit 152 shown in FIG. 8) of column driver 140.
Is output via a signal line 142.

The display control device 510 determines whether the variable (GC
ONT) becomes larger than the value obtained by dividing the number of display lines by 8, it is determined that the gate selection data for one horizontal is completed, and the gate selection data taken into the bit latch circuit of the column driver 140 is line-latch-ed. A circuit (a line latch circuit 153 shown in FIG. 8) latches and generates a clock signal (G1) as a display control signal for outputting a scan voltage based on the gate selection data to a gate signal line (G). The signal is sent to the column driver 140 via the signal line 141.

With the output of the clock signal (G1),
The data stored in the column driver 140 is reflected on each gate signal line (G).

Since these processes are performed every horizontal scanning time, if the data of the number of display lines to be driven plurally is changed in units of display lines as a result, a process based on the changed data is performed. Become.

FIG. 17 shows an embodiment of the present invention.
Liquid crystal display panel (TFT) when driving multiple display lines
FIG. 2 is a diagram illustrating an example of a display screen of (LCD).

A liquid crystal display panel (TFT-L) shown in FIG.
The display screen of (CD) is a display screen in which a portion displayed in black during the vertical retrace period in the display screen of the liquid crystal display panel (TFT-LCD) shown in FIG.

As described above, in the TFT liquid crystal display module according to the embodiment of the present invention, a plurality of display lines are simultaneously driven in one horizontal scanning time, and are driven in the next one horizontal scanning time. It is possible to drive from the next display line after all the display lines.

As a result, it becomes possible to drive the pixels of the display line for which the display data is insufficient in one frame.

Next, a driving method at the time of interlace driving in the embodiment of the present invention will be described.

In the embodiment of the present invention, at the time of interlaced driving, a field synchronization signal is added to distinguish between the first field and the second field.

At the time of interlace driving, the interlace driving instruction signal input from the outside is "1", so that when the vertical synchronizing signal is "1" and the field synchronizing signal is "1", the bit encoder (1 ) 310 is
It outputs 10-bit initial value data of '0,0,0,0,0,0,0,0,0,0'.

In this case, the bit encoder (1) 31
The initial value data output from 0 is output to the delay circuit 313
And a D-type flip-flop circuit 3 in synchronization with a vertical synchronization signal (or a field synchronization signal) delayed by a predetermined time.
12 and the D-type flip-flop circuit 312
Is output from the output terminal (Q).

The multiplexer 316 selects the initial value data output from the output terminal (Q) of the D-type flip-flop circuit 312 and outputs it to the register 301.

Now, a vertical synchronizing signal is input, and then the first
When the third display timing signal is input, the register output data output from the register 301 becomes D
Value data '0,0,0,0,0,0,0' output from the output terminal (Q) of the flip-flop circuit 312
0, 0, 0, 0 'and the lower 3 bits of the register output data.
The bit becomes '0,0,0'.

Since the interlace drive instruction signal is "1", the selector 302 sets the 3-bit line selection data ('0, 1, 0') for interlace drive.
Is selected and output to the adder 303. The adder 303 adds the register output data output from the register 301 and the line selection data ('0, 1, 0').

Thus, each time the display timing signal is sequentially input to the register 301, the initial value data output from the output terminal (Q) of the D-type flip-flop circuit 312 is added to the line selection data ('0'). , 1,
0 ') is retained.

Since the 3-bit multiple-line selection data is '0, 0, 1' for selecting one display line, the upper 8 bits (B2 [15: 0: 1]) of the encoded data (B2 [15: 0]) are selected. 8]) is' 1,0,0,0,0,
0,0,0 '.

In this case, since the shift amount of the right shifter 305 is 0, the upper 8 bits (OR [15: 8]) of the shift encode data are '1, 0, 0, 0, 0, 0,
0,0 '.

The upper 7 bits (PR [6: 0]) of the register output data are '0,0,0,0,0,0,0'.
Therefore, the gate selection data write sequencer 306
Writes “1” into the bit latch circuit of the column driver 140 corresponding to the first display line in the first block, and writes “0” into the bit latch circuit of the column driver 140 corresponding to the other display lines. Is written.

When the next display timing signal is input, the register output data output from register 301 is the adder output data '0,0,0,0,0,0,0 output from adder 303. , 0,1,0 ',
The lower three bits of the register output data are '0, 1, 0'.

Since the 3-bit multi-line selection data is '0, 0, 1' for selecting one display line, the upper 8 bits (B2 [15:15]) of the encoded data (B2 [15: 0]) are selected. 8]) is' 1,0,0,0,0,
0,0,0 '.

In this case, since the shift amount of the right shifter 305 is 2, the upper 8 bits (OR [15: 8]) of the shift encode data are '0, 0, 1, 0, 0,
0,0,0 '.

The upper 7 bits (PR [6: 0]) of the register output data are '0,0,0,0,0,0,0'
Therefore, the gate selection data write sequencer 306
Writes “1” to the bit latch circuit of the column driver 140 corresponding to the third display line in the first block, and writes “0” to the bit latch circuit of the column driver 140 corresponding to the other display lines. Is written.

When the next display timing signal is input, the register output data output from register 301 is the adder output data '0,0,0,0,0,0,0 output from adder 303. , 1,0,0 ',
The lower three bits of the register output data are '1, 0, 0'.

[0284] Also, when the plural line selection data is' 0, 1,
0 ', the encoded data (B2 [15:
0]), the upper 8 bits (B2 [15: 8]) are '1,
0,0,0,0,0,0,0 '.

In this case, since the shift amount of the right shifter 305 is 4, the upper 8 bits (OR [15: 8]) of the shift encode data are '0, 0, 0, 0, 1, 1,.
0,0,0 '.

The upper 7 bits (PR [6: 0]) of the register output data are '0,0,0,0,0,0,0'.
Therefore, the gate selection data write sequencer 306
Writes “1” to the bit latch circuit of the column driver 140 corresponding to the fifth display line in the first block, and writes “0” to the bit latch circuits of the column driver 140 corresponding to the other display lines. Is written.

Similarly, each time a display timing signal is input, "1" is written to the bit latch circuit of the corresponding column driver 140 so that the next lower display line is selected. "0" is written to the bit latch circuit of the column driver 140 corresponding to the display line of "1".

In the case of interlaced driving, “1” (selection) is applied from the block to be driven this time to the next block.
Since there is no case in which the data of (1) and (2) are continuous, the encoded data is 8-bit data.

Further, instead of converting the input 3-bit multi-line selection data of '0, 0, 1' to 8-bit encoded data by the bit encoder (2) 304, '1, 0, 0, 8-bit data of 0, 0, 0, 0, 0 'may be input to the right shifter 305.

FIG. 19 is a flowchart showing a processing procedure of the gate selection data write sequencer 306 shown in FIG. 9 during interlaced driving according to the embodiment of the present invention.

As shown in FIG. 19, at the time of interlaced driving, step 3 in the flowchart shown in FIG.
54 is omitted, and the processing of step 355 is
What is necessary is to set CONT = GCONT + 1.

As in the case of driving a plurality of display lines, the bit encoder (2) 304 inputs' 0, 0,
The three-bit multi-line selection data of 1 'is divided into lower-order 8 bits of' 0,0,0,0,0,0,0,0 'and upper 8 bits of' 1,0,0,0,0 ' , 0, 0, 0 ′, may be converted to 16-bit encoded data. In this case, the processing procedure of the gate selection data write sequencer 306 is the same as the flowchart shown in FIG.

Also, the bit encoder (1) 310 operates when the vertical synchronizing signal is “0” and the field synchronizing signal is “1” so that the display line to be driven is different between the previous field and the next field. , '0,0,0,0,
Output the initial value data of 0, 0, 0, 0, 0, 1 '.

FIG. 18 shows an embodiment of the present invention.
FIG. 8 is a diagram showing a timing chart of a vertical display control signal from the main body computer shown in FIG. 7 during interlace driving.

As shown in FIG. 18, a field synchronization signal for distinguishing the first field from the second field is added.

As described above, in the TFT type liquid crystal display module according to the embodiment of the present invention, a certain
In the field, every other (two lower) display lines are driven, and in the next one field, every other display line that is not driven in the field is driven (two lower).
Interlaced driving is possible.

As a result, it is possible to drive the display lines by the interlace driving method adopted in the television receiver or the like.

In the embodiment of the present invention, FIG.
The gate selection data write sequencer 306 shown in FIG.
The horizontal synchronizing signal and the clock signal are input, and the clock signal generating means (3) 321 transmits the clock signal (G
It is also possible to adopt a circuit configuration for generating 1).

In this case, the liquid crystal display panel (TFT-
LCD), the number of display data transmitted from the main body computer side with respect to the number of pixels of one display line, and the number of display lines of a liquid crystal display panel (TFT-LCD)
When the number of display lines of the display data transmitted from the main body computer is insufficient, a liquid crystal display panel (TFT-L
It is possible to improve the display quality displayed on a CD).

Further, in the TFT type liquid crystal display module according to the embodiment of the present invention, the column driver used in the simple matrix type liquid crystal display device is used as the gate driver. However, the present invention is not limited to this. Needless to say, the drain driver shown in FIG. 7 or FIG. 20 can be used.

Further, in each of the embodiments of the present invention, the case where the present invention is applied to a TFT type liquid crystal display module has been described. However, the present invention is not limited to this, and the present invention is not limited to this.
Needless to say, the present invention can be applied to all liquid crystal display devices such as a liquid crystal display module of the tic type.

Although the present invention has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and various modifications may be made without departing from the gist of the present invention. It goes without saying that you get it.

[0303]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, in a liquid crystal display device, when the number of display data is insufficient with respect to the number of pixels of one display line of the liquid crystal display panel, the circuit scale and the outer shape of the display control device It is possible to generate a control signal at a timing proportional to the shortage without increasing the size.

(2) According to the present invention, in the liquid crystal display device, when the number of display data is insufficient for the number of pixels of one display line of the liquid crystal display panel, the time interval between the control signals is kept constant. It is possible to generate a control signal at a timing proportional to the shortage while maintaining the control signal.

(3) According to the present invention, in a liquid crystal display device, a designated color can be displayed on a pixel of one display line of a liquid crystal display panel having insufficient display data, and double display can be prevented. It is possible to improve the display quality of the display image displayed on the display panel.

(4) According to the present invention, in the liquid crystal display device, it is possible to drive the display lines of the liquid crystal display panel by an arbitrary driving method, whereby each display line can be interfaced within one frame time. It is possible to drive in a race drive system.

(5) According to the present invention, in a liquid crystal display device, it is possible to drive a plurality of display lines of a liquid crystal display panel within one horizontal scanning time. In the case where the number of display lines of display data within one frame time input from the main computer is insufficient, double display is prevented without increasing the circuit scale and external dimensions of the display control device, It is possible to improve the display quality of a display image displayed on the liquid crystal display panel.

[Brief description of the drawings]

FIG. 1 is a liquid crystal display panel (TFT-LCD) in a TFT liquid crystal display module according to a first embodiment of the present invention.
3 is a diagram showing an equivalent circuit of FIG.

FIG. 2 shows a clock signal (D1) and a clock signal (D2) in the display control device 510 according to the first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a circuit portion that generates a clock signal (D1).

3 is a diagram showing a timing chart of a clock signal (D1), a clock signal (D2) and a clock signal (D1) generated by the circuit configuration of FIG. 2, and a display control signal from a main computer.

FIG. 4 is a diagram illustrating an example of a display screen of the liquid crystal display panel when the number of display lines of display data transmitted from the main body computer is clearly insufficient with respect to the number of display lines of the liquid crystal display panel. .

5 is a schematic block diagram showing an example of a drain driver 530 configured to prevent the double display image shown in FIG.

6 is a diagram showing a timing chart of a clock signal (D1), a clock signal (D2) and display data shown in FIG.

FIG. 7 is a block diagram showing a schematic configuration of a TFT type liquid crystal display module according to another embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic configuration of a column driver used in a simple matrix type liquid crystal display device.

FIG. 9 shows gate selection data to be sent to column driver 140 and clocks (G1, G) as display control signals in display control device 510 according to the second embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a circuit portion that generates 2).

10 is a truth table showing the truth values of the selector 302 shown in FIG. 9;

11 is a truth table showing the truth values of the bit encoder (2) 304 shown in FIG. 9;

12 is a block diagram showing a schematic configuration of an initial value setting circuit 300 shown in FIG.

13 is a bit encoder (1) 310 shown in FIG.
5 is a truth table showing the truth values of.

FIG. 14 is a block diagram showing a schematic configuration of a gate selection data write sequencer 306 shown in FIG.

15 is a flowchart showing a processing procedure of a gate selection data write sequencer 306 shown in FIG.

16 is a diagram showing a timing chart of a display control signal from the main computer shown in FIG. 7 and a display control signal generated by the display control device 510 during driving of a plurality of display lines according to the embodiment of the present invention.

FIG. 17 is a diagram illustrating an example of a display screen of a liquid crystal display panel when a plurality of display lines are driven according to an embodiment of the present invention.

FIG. 18 is a flowchart showing a processing procedure of the gate selection data write sequencer 306 shown in FIG. 9 at the time of interlaced driving according to the embodiment of the present invention.

19 is a diagram showing a timing chart of a display control signal in the vertical direction from the main computer shown in FIG. 7 during interlaced driving according to the embodiment of the present invention.

FIG. 20 shows a conventional TFT (Thin Film Tra).
FIG. 3 is a block diagram illustrating a schematic configuration of a liquid crystal display module of an nsistor type.

FIG. 21 shows a liquid crystal display panel (TFT-LC) shown in FIG.
It is a figure which shows the equivalent circuit of D).

FIG. 22 is a block diagram showing a schematic configuration of a drain driver 530 shown in FIG.

FIG. 23 is a block diagram showing a schematic configuration of a gate driver 540 shown in FIG.

24 is a diagram showing a timing chart of a display control signal from the main computer shown in FIG. 20 and a display control signal generated by the display control device.

FIG. 25 is a diagram showing an example of a display screen of a conventional liquid crystal display panel when the number of display lines transmitted from the main body computer is clearly insufficient with respect to the number of display lines of the liquid crystal display panel. .

[Explanation of symbols]

TFT-LCD: liquid crystal display panel, 140: column driver, 141, 142, 531, 532, 541, 54
2 ... signal lines, 143, 533 ... bus lines, 151, 2
32, 552, 562: shift register, 152: bit latch circuit, 153: line latch circuit, 154, 5
55, 563... Level shift circuit, 155, 556, 5
64: output circuit, 201: AND circuit, 202, 207
... Counter, 203 ... Rise detection circuit, 204 ... Fall detection circuit, 205 ... Register, 206, 20
9, 210, 211 ... storage means, 208 ... subtractor, 21
2,213,214 ... adders, 215,216,21
7, 316, 525... Multiplexer, 218, 21
9, 220 ... comparison circuit, 221, 222 ... JK type flip-flop circuit, 241 ... inverter, 242 ... OR circuit, 300 ... initial value setting circuit, 301 ... register,
302 selector, 303 adder, 304 bit encoder (2), 305 right shifter, 306 gate selection data write sequencer, 310 bit encoder (1), 311 OR circuit, 312 D-type flip-flop Circuit, 313, 314 ... delay circuit, 315 ...
RS type flip-flop circuit, 320 ... control means,
321, clock signal generation means (3), 322, clock signal generation means (4), 323, gate selection data generation means, 500, interface unit, 510, display control device, 520, power supply circuit, 521, positive voltage generation circuit , 52
2: Negative voltage generation circuit, 523: Counter electrode (common electrode)
Voltage generation circuit, 524: gate electrode voltage generation circuit, 53
0: drain driver, 540: gate driver, 55
DESCRIPTION OF SYMBOLS 1 ... Control circuit, 553 ... Input register circuit, 554 ... Storage register circuit, 557 ... Grayscale voltage generation circuit, 5
58: voltage bus line, 561: logic circuit.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 31, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

Next, a method for generating clock signal (D1), clock signal (D2) and clock signal ( G1 ) in display control device 510 according to the embodiment of the present invention will be described.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0095

[Correction method] Change

[Correction contents]

FIG. 2 is a block diagram showing a schematic configuration of a circuit portion for generating clock signal (D1), clock signal (D2) and clock signal ( G1 ) in display control device 510 according to the embodiment of the present invention. It is.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0102

[Correction method] Change

[Correction contents]

[0102] falling detection circuit 203, upon detecting the falling of the display timing signal, and outputs a falling <br/> rising detection pulse.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0103

[Correction method] Change

[Correction contents]

[0103] Standing from the detection circuit 203 rising under this Standing
The lower rising detection pulse, the number of clock signals counted by the counter 202 is latched into register 205.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

[0113] on the rising detection circuit 204, upon detecting the on the rising edge of the display timing signal, and outputs a detection pulse.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

[0114] Counter 207, and counts the clock signals is cleared by the detection pulse from the the rising detection circuit 204.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0121

[Correction method] Change

[Correction contents]

The pulse from the comparison circuit 219 is J-
The signal is input to the K input terminal of the K-type flip-flop circuit 222.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0122

[Correction method] Change

[Correction contents]

The JK flip-flop circuit 2
The 22 of the J input terminal, the rising edge detection pulse from the rising edge detection circuit 2 0 4 is input.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

The pulse from the comparison circuit 218 is J-
The signal is input to the K input terminal of the K-type flip-flop circuit 221.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

The JK flip-flop circuit 2
The rising edge detection pulse from the rising edge detection circuit 204 is input to the J input terminal 21.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

FIG. 3 shows a timing chart of the clock signal (D1), the clock signal (D2) and the clock signal ( G1 ) generated by the circuit configuration of FIG. 2, and the display control signal from the main computer. FIG.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0147

[Correction method] Change

[Correction contents]

However, in the circuit configuration shown in FIG.
The shift register circuit 232 is reset to zero when the clock signal (D1) is input.

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0148

[Correction method] Change

[Correction contents]

[0148] Also, the input register circuit 553, via the OR circuit 242, clock signal (D 1) is input.

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0149

[Correction method] Change

[Correction contents]

[0149] Thus, in synchronization with the rising edge of the clock signal (D 1), as shown in FIG. 6, the data bus 53
By sending display data of a designated color, for example, black display data, to all the input register circuits 553, black display data is first latched.

[Procedure amendment 15]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a liquid crystal display panel (TFT-LCD) in a TFT liquid crystal display module according to a first embodiment of the present invention.
3 is a diagram showing an equivalent circuit of FIG.

FIG. 2 shows a clock signal (D1) and a clock signal (D2) in the display control device 510 according to the first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a circuit portion that generates a clock signal (D1).

3 is a diagram showing a timing chart of a clock signal (D1), a clock signal (D2) and a clock signal (D1) generated by the circuit configuration of FIG. 2, and a display control signal from a main computer.

FIG. 4 is a diagram illustrating an example of a display screen of the liquid crystal display panel when the number of display lines of display data transmitted from the main body computer is clearly insufficient with respect to the number of display lines of the liquid crystal display panel. .

5 is a schematic block diagram showing an example of a drain driver 530 configured to prevent the double display image shown in FIG.

6 is a diagram showing a timing chart of a clock signal (D1), a clock signal (D2) and display data shown in FIG.

FIG. 7 is a block diagram showing a schematic configuration of a TFT type liquid crystal display module according to another embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic configuration of a column driver used in a simple matrix type liquid crystal display device.

FIG. 9 shows gate selection data to be sent to column driver 140 and clocks (G1, G) as display control signals in display control device 510 according to the second embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a circuit portion that generates 2).

10 is a truth table showing the truth values of the selector 302 shown in FIG. 9;

11 is a truth table showing the truth values of the bit encoder (2) 304 shown in FIG. 9;

12 is a block diagram showing a schematic configuration of an initial value setting circuit 300 shown in FIG.

13 is a bit encoder (1) 310 shown in FIG.
5 is a truth table showing the truth values of.

FIG. 14 is a block diagram showing a schematic configuration of a gate selection data write sequencer 306 shown in FIG.

15 is a flowchart showing a processing procedure of a gate selection data write sequencer 306 shown in FIG.

16 is a diagram showing a timing chart of a display control signal from the main computer shown in FIG. 7 and a display control signal generated by the display control device 510 during driving of a plurality of display lines according to the embodiment of the present invention.

FIG. 17 is a diagram illustrating an example of a display screen of a liquid crystal display panel when a plurality of display lines are driven according to an embodiment of the present invention.

FIG. 18 is a flowchart showing a processing procedure of the gate selection data write sequencer 306 shown in FIG. 9 at the time of interlaced driving according to the embodiment of the present invention.

19 is a diagram showing a timing chart of a display control signal in the vertical direction from the main computer shown in FIG. 7 during interlaced driving according to the embodiment of the present invention.

FIG. 20 shows a conventional TFT (Thin Film Tra).
FIG. 3 is a block diagram illustrating a schematic configuration of a liquid crystal display module of an nsistor type.

FIG. 21 shows a liquid crystal display panel (TFT-LC) shown in FIG.
It is a figure which shows the equivalent circuit of D).

FIG. 22 is a block diagram showing a schematic configuration of a drain driver 530 shown in FIG.

FIG. 23 is a block diagram showing a schematic configuration of a gate driver 540 shown in FIG.

24 is a diagram showing a timing chart of a display control signal from the main computer shown in FIG. 20 and a display control signal generated by the display control device.

FIG. 25 is a diagram showing an example of a display screen of a conventional liquid crystal display panel when the number of display lines transmitted from the main body computer is clearly insufficient with respect to the number of display lines of the liquid crystal display panel. .

[Description of Signs] TFT-LCD: liquid crystal display panel, 140: column driver, 141, 142, 531, 532, 541, 54
2 ... signal lines, 143, 533 ... bus lines, 151, 2
32, 552, 562: shift register, 152: bit latch circuit, 153: line latch circuit, 154, 5
55, 563... Level shift circuit, 155, 556, 5
64: output circuit, 201: AND circuit, 202, 207
... Counter, 203 ... Rise detection circuit, 204 ... Fall detection circuit, 205 ... Register, 206, 20
9, 210, 211 ... storage means, 208 ... subtractor, 21
2,213,214 ... adders, 215,216,21
7, 316, 525... Multiplexer, 218, 21
9, 220: comparison circuit, 221, 222: JK flip-flop circuit , 242: OR circuit, 300: initial value setting circuit, 301: register, 302: selector, 3
03: adder, 304: bit encoder (2), 30
5 right shifter 306 gate select data write sequencer 310 bit encoder (1) 311 OR
Circuit, 312 ... D-type flip-flop circuit, 313,
314 delay circuit, 315 RS flip-flop circuit, 320 control means, 321 clock signal generation means (3), 322 clock signal generation means (4), 323 gate selection data generation means, 500 …
Interface unit, 510: display control device, 520: power supply circuit, 521: positive voltage generation circuit, 522: negative voltage generation circuit, 523: counter electrode (common electrode) voltage generation circuit
524: gate electrode voltage generation circuit, 530: drain driver, 540: gate driver, 551: control circuit,
553: input register circuit, 554: storage register circuit, 557: gradation voltage generation circuit, 558: voltage bus line, 561: logic circuit.

[Procedure amendment 16]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

[Procedure amendment 17]

[Document name to be amended] Drawing

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

FIG. 6

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshio Futami 3300 Hayano, Mobara-shi, Chiba Electronic Device Division, Hitachi, Ltd.

Claims (13)

[Claims] A plurality of first signal lines; a plurality of first signal lines;
And a plurality of pixels formed in a matrix to which a liquid crystal drive voltage is applied by the plurality of first signal lines and the plurality of second signal lines. A liquid crystal display panel, a first driving unit that captures display data for one horizontal scanning period, and outputs a video voltage based on the display data to the plurality of first signal lines; A second driving unit for outputting a scanning voltage for selecting a display line corresponding to the display data to the plurality of second signal lines; and transmitting input display data to the first driving unit. A control signal is generated based on an input display control signal to be input, and the control signal is transmitted to the first driving means and the second driving means, so that the first driving means and the second driving means are transmitted. Display system for controlling and driving means Means for calculating a difference between the number of pixels of one display line of the liquid crystal display panel and the number of display data transmitted within one horizontal scanning period. Means for controlling, based on the difference value obtained by the difference value calculating means, when the number of display data transmitted within one horizontal scanning period is smaller than the number of pixels of one display line of the liquid crystal display panel. A liquid crystal display device comprising timing changing means for changing the timing of a signal. 2. The display control signal generated by the display control means includes at least one of an output timing control clock signal, a display data latch clock signal, and a shift clock signal for each horizontal scanning time. The timing changing means counts the number of input clock signals from a start position at which the input display timing signal indicates a valid portion of display data.
And a first change for changing the timing of the output timing control clock signal based on the difference value obtained by the difference value calculation means and the number of clock signals counted by the first count means. Means for changing the timing of the display data latch clock signal, and at least one of third changing means for changing the timing of the shift clock signal for each horizontal scanning time. The liquid crystal display device according to claim 1. 3. The liquid crystal display panel according to claim 1, wherein the display timing signal indicates the effective portion of the display data with respect to the number of pixels in one display line of the liquid crystal display panel. First storage means for storing the number of clock signals until output, and first calculation for subtracting the difference value obtained by the difference value calculation means from the number of clock signals stored in the first storage means Means for comparing the number of clock signals counted by the first counting means with a value obtained by the first calculating means, and outputting a clock signal for output timing control when the comparison result matches. The liquid crystal display device according to claim 2, further comprising a first comparison circuit. 4. The display data latch according to claim 2, wherein the display timing signal is output from a start position indicating a valid portion of display data with respect to the number of pixels of one display line of the liquid crystal display panel. Second storage means for storing the number of clock signals, second calculation means for subtracting the difference value obtained by the difference value calculation means from the number of clock signals stored in the second storage means,
A second comparing circuit for comparing the number of clock signals counted by the first counting means with a value obtained by the second calculating means; and the display timing signal indicating a valid portion of display data. From the starting position, the second
3. A liquid crystal display according to claim 2, further comprising clock signal generating means (1) for outputting a clock signal as a display data latch clock signal until the result of comparison by said comparison circuit matches. Display device. 5. The liquid crystal display panel according to claim 5, wherein the display timing signal corresponds to the number of pixels of one display line of the liquid crystal display panel from a start position indicating a valid portion of display data to outputting the shift clock signal. A third storage unit that stores the number of clock signals, and a third calculation unit that subtracts the difference value obtained by the difference value calculation unit from the number of clock signals stored in the third storage unit. The third comparison circuit that compares the number of clock signals counted by the first counting means with the value obtained by the third calculation means matches the comparison result by the third comparison circuit. 3. The liquid crystal display device according to claim 2, further comprising a clock signal generating means (2) for outputting a shift clock signal whose voltage level changes. 6. The second difference value calculating means counts the number of clock signals input during a period in which the display timing signal indicates a valid portion of display data.
Counting means, a fourth storage means for storing the number of pixels of one display line of the liquid crystal display panel, a clock signal number counted by the second counting means, and stored in the fourth storage means. 6. The liquid crystal display device according to claim 1, further comprising: fourth calculation means for calculating a difference value between the number of pixels of one display line of the liquid crystal display panel. . 7. The display control device sends display data of a designated color to the first drive unit before sending display data, and the first drive unit is input from the display control device. Based on an output timing control clock signal, display data of a specified color input from the display control device is stored, and then, the display data is synchronized with a display data latch clock signal input from the display control device. 7. The display device according to claim 1, further comprising display data latch means for storing display data input from the control device.
A liquid crystal display device described in any one of the above. 8. An initial value setting circuit for outputting k-bit initial value data according to an input vertical synchronizing signal, and the display control means adds the k-bit initial value data or k bits according to the display timing signal. K-bit register for latching the output data of the device, k-bit register output data output from the register and n
An adder for adding the multiple line selection data of bits,
Generating means for generating display line selection data based on the k-bit register output data output from the register and the n-bit plural line selection data, and a clock signal for generating a display line selection data latch clock signal Generation means (3), the second driving means comprises: display line selection data latch means for latching the display line selection data in synchronization with the display line selection data latch clock signal; and display line selection data. 2. A voltage supply means for supplying a scanning voltage based on display line selection data latched by a latch means to the second signal line for one horizontal scanning time based on the shift clock signal. A liquid crystal display device according to claim 7. 9. A bit encoder for converting the n-bit plurality of line selection data into encoded data of m (m is 2 to the power of (n + 1)) bits according to a combination of n bits. A right shift unit that shifts the m-bit encoded data output from the bit encoder to the right by a shift amount determined by the lower n bits of the k-bit register output data output from the register, and outputs shift encoded data. When the shifter and N (N is 2 to the power of n) second signal lines form one block, the shifter is determined by the upper (kn) bits of k-bit register output data output from the register. An m-bit shift encode data output from the right shifter is applied to a second signal line corresponding to the next two blocks of the block. 9. The liquid crystal display device according to claim 8, further comprising an allocating means for allocating data and allocating "0" data to second signal lines corresponding to other blocks. 10. The liquid crystal display device according to claim 8, wherein the n bits are 3 bits, the m bits are 16 bits, and the k bits are 10 bits. 11. The display control means according to a combination of an input vertical synchronizing signal and a field synchronizing signal, k-bit first initial value data, or k obtained by adding 1 to the first initial value data. An initial value setting circuit for outputting bit second initial value data, and latching the k-bit first initial value data, k-bit second initial value data or k-bit adder output data according to the display timing signal. k-bit register, k-bit register output data output from the register, upper (l-2) bits are "0", lower 2 bits are "1, 0"
And an adder for adding 1-bit interlaced line selection data during interlace driving, and k output from the register.
Generating display line selection data based on bit register output data and m-bit line selection data in which the upper (1) bit is “1” and the lower (m−1) bit is “0” And a clock signal generator (3) for generating a clock signal for a display line selection data latch, wherein the second drive means synchronizes with the display line selection data latch clock signal. Display line selection data latching means for latching the display line selection data latched by the display line selection data latching means, and applying a scanning voltage based on the shift clock signal to the second signal line for one horizontal scanning time. The liquid crystal display device according to any one of claims 1 to 7, further comprising a voltage supply unit for supplying the voltage. 12. A shift line selection method comprising: shifting the m-bit line selection data to the right by a shift amount determined by lower n bits of k-bit register output data output from the register; When a right shifter for outputting data and N (N is 2 to the power of n) second signal lines are defined as one block, k bits of register output data output from the register are higher (kn). The m-bit shift line selection data output from the right shifter is allocated to a second signal line corresponding to a block next to the block determined by the bit, and a second signal corresponding to the other blocks is allocated. The liquid crystal display device according to claim 11, further comprising an assigning unit that assigns data of "0" to the line. 13. The method according to claim 11, wherein the 1 bit is 3 bits, the n bits is 3 bits, the m bits is 8 bits, and the k bits are 10 bits. Liquid crystal display.