JPH1097203A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable testing easily disconnection and short circuit of a scanning line and a signal line or output of driving circuits of these lines without using a probe and the like to cope with improving accuracy and increasing capacity of a liquid crystal display. SOLUTION: This device comprises scanning lines G1, G2, G3, G4 and signal lines D1, D2, D3, D4 arranged crossing mutually. One end of each scanning line G1-G4 is connected to gates of TFTTq1, TFTTq2, TFTTq3, TFTTq4 through capacitors Cp1, Cq2, Cq3, Cq4. Sources of TFTTq1-Tq4 are connected commonly to a terminal SEN 1. When a signal applied to a scanning line is inputted to gates of the TFTTq1-Tq4, a value of a current or voltage detected from the SEN 1 is varied. It is discriminated whether scanning lines G1-G4 are electrically abnormal or not by measuring quantity of this variation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display device represented by a liquid crystal display, and more particularly to a scanning line,
The present invention relates to a means for inspecting a signal line or an output of a driving circuit of these lines.

[0002]

2. Description of the Related Art In a conventional liquid crystal display, a defect inspection method of a scanning line, a signal line, or a drive circuit output of these wirings has been performed by directly bringing a test probe into contact with each wiring or a drive circuit output.

[0003] However, the display has become higher definition,
As the capacity has been increased, the pitch between wirings or between drive circuit output terminals has become finer, and it has been difficult to perform inspections by conventional methods.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide an inspection means suitable for inspecting wiring of a high-definition, large-capacity display and output of a driving circuit. Aim.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a matrix type display device in which a gate is connected to each of the scanning lines or the signal lines, and a source and a drain are connected to a common line to which an external voltage is supplied. This is achieved by a display device including a plurality of connected test transistors, a capacitor inserted between each of the scanning lines or the signal lines, and at least one of the common wirings.

The inspection transistor is switched according to switching of a voltage applied to a scanning line or a signal line to which the gate is connected. Then, by detecting a voltage change between an external voltage connected to the source and the drain of the inspection transistor, a voltage and a current applied to the wiring connected to the gate can be detected. At this time, if the wiring has a short-circuit or open defect, the detected voltage and current value change, so that it is possible to determine whether there is a defect.

A capacitor is arranged between a wiring to be inspected and a wiring for supplying an external voltage. In other words, this capacitance element is inserted between the wiring and the gate of the inspection transistor, or between the wiring for supplying an external voltage and the source or drain of the inspection transistor. According to this configuration, when a short-circuit defect occurs in the inspection transistor, the wiring to be inspected and the wiring for supplying an external voltage are insulated by the capacitance element, so that a normal repair process is not required. A display operation can be performed.

Further, the present invention can be applied to a matrix type display device in which a driving circuit is formed monolithically. For example, a driving circuit for driving a signal line has a serial-parallel conversion circuit including a timing control circuit such as a shift register and a sampling circuit. In order to check the output of the timing control circuit, each parallel circuit of the timing control circuit is tested. A gate is connected to the output, and a plurality of inspection transistors are connected to a common line whose source and drain are each supplied with an external voltage, and a capacitive element is inserted between each signal line and at least one of the common lines. I do.

According to this configuration, the output of the drive circuit can be easily inspected, and even if a defect occurs in the inspection transistor, a normal display operation can be performed without requiring any special repair.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 Hereinafter, a liquid crystal display according to a first embodiment of the present invention will be described with reference to the drawings. This embodiment is an example in which the present invention is applied to a disconnection / short circuit inspection of a scanning line.

This liquid crystal display includes a matrix display section 103 shown in FIG. The matrix display unit includes a plurality of scanning lines (G1 to G4) and a plurality of signal lines (D1 to D4) arranged crossing each other, and thin film transistors (T11 to T44) connected to respective intersections of the scanning lines and the signal lines. And a pixel electrode (P1) connected to each thin film transistor.
1 to P44). Pixel electrodes (P11-P
44) is capacitively coupled to a counter electrode (not shown) via a liquid crystal layer to form a pixel capacitance.

The scanning line driving circuit 101 is constituted by a so-called shift register, generates scanning pulses in synchronization with a clock CK, and outputs the scanning pulses to the scanning lines G1 to G4 in a line-sequential manner. The other ends of the scanning lines are connected to capacitors Cq1 to Cq, respectively.
4 are connected to the gates of the n-type TFTs Tq1 to Tq2. The sources of the TFTs Tq1 and Tq2 are commonly connected to a reference voltage line GND (for example, a ground potential). On the other hand, T
The drains of the FTTq1 and Tq2 are commonly connected to a power supply VCC via a terminal SEN1 and a resistor Rqs. Also T
The gates of FTTq1 to Tq2 are connected to resistors Rq1 to Rq
Connected to the source via q4.

Next, a description will be given of a method for inspecting a disconnection / short-circuit of a scanning line using the above configuration. First, when a predetermined signal is input to the scanning line driving circuit 101 via the control line ST,
The scanning line driving circuit 101 is set to the inspection mode. At this time, scanning pulses are sequentially output from the scanning line driving circuit 101 to the scanning lines G1 to G4. When a scan pulse is applied to G1 and there is no defect such as disconnection or short circuit in scan line G1, this pulse is applied to TFT Tq via capacitor Cq1.
1 gate. As a result, TFTTq1 is ON
, And the voltage at the terminal SEN1 becomes a value LOW which is a voltage drop from the power supply voltage VCC by a loss due to the resistance Rqs.

At this time, if the scanning line is broken,
The scanning pulse does not reach the TFT Tq1, the TFT Tq1 remains OFF, and the voltage of the terminal SEN1 becomes HIGH. On the other hand, if the scanning line is short-circuited with another wiring, an incomplete scanning pulse may reach the TFT q1. In this case, the detection of the short-circuit defect is determined by the SE when the incomplete scan pulse arrives.
This is done by comparing the output of N1 with the voltage or current detected by SEN1 when a normal scan pulse arrives. Alternatively, the same object can be achieved by adjusting the value of the resistor Rqs to adjust the output sensitivity of the SEN1. Subsequently, by sequentially applying scanning pulses also to the scanning lines G2 to G4, the inspection of all the scanning lines is completed.

(Embodiment 2) FIG. 2 shows a liquid crystal display according to a second embodiment of the present invention. This embodiment is an example in which the inspection circuit having the same configuration as that of the first embodiment is applied to the output inspection of the scanning line driving circuit. A switching circuit 106 including TFTs TW1 to TW4 is inserted between the output of the scanning line driving circuit and the scanning line of the matrix display unit. The switch circuit 106 plays a role of disconnecting the scan line from the drive circuit when checking the output of the drive circuit. Thus, even when a part of the scanning line has a defect, the output of the driving circuit can be inspected without being affected by the defect. If it is known beforehand that there is no defect in the scanning line before checking the output of the driving circuit, the switching circuit 106 is not particularly required.

Inspection of the output of the driving circuit of this embodiment is performed by sequentially applying the output of the scanning line driving circuit 101 to the gates of the TFTs Ts1 to Ts2 and measuring the output of SEN2.

(Embodiment 3) FIG. 3 shows a liquid crystal display according to a third embodiment of the present invention. This embodiment is an example in which the inspection circuit having the same configuration as that of the first embodiment is applied to disconnection / short circuit inspection of a signal line. The signal line driving circuit 102 includes a pulse generation circuit 107 including a shift register and a sampling circuit 1.
08. The pulse generation circuit 107 sequentially outputs pulses to the outputs S1 to S4. The TFTs Tv <b> 1 to Tv <b> 4 included in the sampling circuit 108 output a video signal Video input from outside according to the output of the pulse generation circuit 107.
Is sampled and output to the signal lines D1 to D4. An inspection circuit unit having a circuit configuration similar to that of the first embodiment is connected to the other ends of the signal lines D1 to D4.

Also in this embodiment, by inputting the voltages of the signal lines D1 to D4 to the gates of the TFTs Tt1 to Tt4, it is possible to detect a defect caused by a disconnection or short-circuit defect of the signal line.

(Embodiment 4) FIG. 4 shows a liquid crystal display according to a fourth embodiment of the present invention. This embodiment is an example in which a test circuit having the same configuration as that of the first embodiment is applied to the output test of the signal line drive circuit. The test circuit includes a pulse generation circuit 107 and a sampling circuit 108 included in the signal line drive circuit. Placed between. The output of the pulse generation circuit 107 is TFTTt
1 to TFTTt4, the operating state of the pulse generation circuit can be inspected by training the output of SEN4. In the present embodiment, since the signal lines of the matrix display unit and the inspection circuit can be separated by the TFTs Tv1 to Tv4 included in the sampling circuit 108, it is necessary to newly add a circuit corresponding to the switch circuit 106 of the second embodiment. There is no.

(Embodiment 5) FIG. 5 shows a liquid crystal display according to a fifth embodiment of the present invention. In this embodiment, the present invention is applied to inspection for disconnection / short circuit of a scanning line.

As shown in FIG. 5, the inspection TFTs Ty1
The gate of Ty4 (all n-type TFTs) is connected to one end of each of the scanning lines G1 to G4, and the sources are connected to the capacitors Cy1 to Cy4, respectively. The other ends of these capacitors Cy1 to Cy4 are connected to a reference voltage GND via a terminal SEN5. The drains of the TFTs Ty1 to Ty4 are commonly connected to a reference voltage VCC.

Next, a method for inspecting a disconnection / short circuit of a scanning line using the above configuration will be described. First, when a predetermined signal is input to the scanning line driving circuit 101 via the control line ST,
The scanning line driving circuit 101 is set to the inspection mode. At this time, scanning pulses are sequentially output from the scanning line driving circuit 101 to the scanning lines G1 to G4. When a scanning pulse is applied to G1 and there is no disconnection or short circuit in scanning line G1, TFT
A scanning pulse is applied to the gate of Ty1 and TFT Ty1
Becomes conductive. Therefore, the reference voltage VCC is applied to SEN5 via the capacitor Cy1, and the voltage detected from the terminal SEN5 becomes HIGH.

On the other hand, when the scanning line G1 is disconnected or short-circuited with another wiring and the scanning pulse does not reach the gate of the TFT Ty1, the voltage detected from the terminal SEN5 remains LOW.

When the scanning line G1 is short-circuited with another wiring and an incomplete scanning pulse is applied to the gate of the TFT Ty1, a pulse having an amplitude corresponding to the amplitude is output to the terminal SEN5. Therefore, by measuring the output voltage or output current of the terminal SEN5, disconnection and short circuit of the scanning line can be inspected.

Similarly, by sequentially applying scanning pulses to the scanning lines G2 to G4, the defect inspection of all the scanning lines is completed. Further, the inspection circuit described above can also be applied to disconnection / short circuit inspection of signal lines as in the third embodiment.

(Embodiment 6) FIG. 6 shows a liquid crystal display according to a sixth embodiment of the present invention. This embodiment is an example in which the same inspection circuit as that of the fifth embodiment is applied to the output inspection of the scanning line driving circuit.

That is, an n-type TFT constituting an inspection circuit
Between the Tr1 to Tr4 and the scanning line of the matrix display unit, a TFT Tw forming a switch unit as in the second embodiment.
1 to Tw4 are arranged. With this switch,
At the time of inspection of the drive circuit output, the scanning lines of the matrix display section are electrically separated from the drive circuit output. Therefore, it is possible to accurately inspect the output of the driving circuit without being affected by the defect of the scanning line.

By providing a similar inspection circuit in the signal line drive circuit, the output of the signal line drive circuit can be inspected. In the configuration shown in FIGS. 5 and 6, the capacitors Cy1 to Cy4 function as a source follower. Therefore, the outputs of the terminals SEN5 and SEN6 change sensitively according to the change in the gate potential of the TFTs Ty1 to Ty4. Therefore, by measuring the outputs of the terminals SEN5 and SEN6, it is possible to determine not only a fatal defect of the drive circuit but also a small defect that can be rescued or a part that is damaged.

(Embodiment 7) FIG. 7 shows a liquid crystal display according to a seventh embodiment of the present invention. In the present embodiment, the present invention is applied to a disconnection / short circuit inspection of a scanning line, and particularly, a scanning line is inspected by using an n-type TFT and a p-type TFT as a pair of inspection TFTs. .

In this embodiment, the scanning line driving circuit 10
1 outputs a pulse of positive polarity or a pulse of negative polarity by switching the signal of the control line CH. n-type TFT
The gates of Tn1 to Tn4 and the p-type TFTs Tp1 to Tp4 are connected to one ends of the scanning lines G1 to G4 via capacitors as in the first embodiment, respectively, as shown in the drawing. n
Sources of the type TFTs Tn1 to Tn4 are commonly connected to a reference voltage GND. The drain is connected to the reference voltage VCC via the terminal SENa and the resistor Rn. On the other hand, the sources of the p-type TFTs Tp1 to Tp4 are connected to the reference voltage VCC, and the drains are connected to the reference voltage GND via the terminal SENb and the resistor Rp.

Next, a method for inspecting a disconnection or short circuit of a scanning line using the above configuration will be described. The scanning line driving circuit 101 is set to the inspection mode according to an input signal from the control line ST. At this time, the scanning line driving circuit 101 scans the scanning lines G1 to G
4 sequentially outputs scanning pulses. As described above, the polarity of the scanning pulse can be switched by the input signal from the control line CH.

(1) When Scanning Line is Normal FIG. 8 is a timing chart of the test circuit input and output signals when the display panel is normal. First, when no pulse is applied to the scanning line G1, the TFT Tn
1 to Tn4 are off, and the output of the terminal SENa is HIG
H. On the other hand, in this state, since the TFTs Tp1 to Tp4 are off, the output of the terminal SENb becomes LOW.

Next, when a positive pulse is applied to the scanning line G1, the TFT Tn1 is turned on, and the output of the terminal SENa becomes LOW. On the other hand, since the TFT Tp1 remains off, the terminal SENb remains LOW. Hereinafter, when positive polarity pulses are sequentially applied to the scanning lines G2 to G4,
The TFTs Tn2 to Tn4 are sequentially turned on, and the terminals S
The output of ENa becomes LOW.

Next, when a pulse of negative polarity is applied to the scanning line G1, the TFT Tp1 is turned on, and the output of the terminal SENb becomes HIGH. On the other hand, the TFT Tn1 remains off, and the output of the terminal SENa remains HIGH.
Thereafter, when a negative pulse is sequentially applied to the scanning lines G2 to G4, the TFTs Tp2 to Tp4 are sequentially turned on, and at that time, the output of the terminal SENb becomes LOW.

(2) When the scanning line is abnormal FIG. 9 shows that the potential of the scanning line G3 is the potential HIG due to a short-circuit defect.
The input / output of the inspection circuit in the state where it is fixed at H is shown.
In this state, the TFT Tn3 is always turned on, so that the terminal SENa maintains LOW. Therefore, the scanning lines G1 to G4
Even if a positive-polarity scan pulse is applied, the output of the terminal SENa becomes the same as that in the normal state shown in FIG. 8, so that no abnormality can be detected.

Next, when a scanning pulse of a negative polarity is applied to the scanning lines G1 to G4, G3 is fixed at the potential HIGH during the period in which the scanning pulse is applied to the scanning line G3.
FTTp3 remains off. Therefore, the output of the terminal SENb becomes LOW, and it can be detected that the scanning line G3 has an abnormality such as a short-circuit defect.

When one of the scanning lines is fixed at the potential LOW due to a disconnection or the like, when a positive scanning pulse is applied to the scanning lines G1 to G4, the terminal SENa becomes LOW.
In this state, the presence or absence of a defect can be detected.
In addition, an incomplete pulse or a pulse with a small amplitude is T
When applied to FTTn1 to Tn4 and Tp1 to Tp4, the presence or absence of a defect can be detected by measuring the output voltage or current at the terminals SENa and SENb.

(3) TFT Tn1 to Tn4 or TFT
When Tp1 to Tp4 are Abnormal First, if any of the TFTs Tn1 to Tn4 is damaged and short-circuited, the damaged TFT is always on, and the output of the terminal SENa is always LOW. Therefore,
An abnormality of the scanning line can be detected from the output of the terminal SENb. When any one of the TFTs Tp1 to Tp4 is short-circuited, an abnormality of the scanning line can be detected from the output of the terminal SENa.

Next, it is assumed that an open defect has occurred in any of the TFTs Tn1 to Tn4. For example, TFT
When Tn1 has a defect, the terminal SENa is at the potential HIGH.
, And the same abnormality as when the scanning line G1 is disconnected is detected. At this time, if the terminal SENb detects that the scanning line G1 is normal, it is determined that the TFT Tn1 is damaged.

Similarly, if any of the TFTs Tp1 to Tp4 has an open defect, the terminals SENa and SE
By examining the output of Nb, it is possible to invert the portion where the abnormality has occurred. In addition, by providing the above inspection circuit for the signal line, disconnection / short circuit inspection of the signal line can be performed.

(Embodiment 8) FIG. 10 shows a liquid crystal display according to an eighth embodiment of the present invention. FIG. 10 is an example in which the inspection circuit having the same configuration as that of the seventh embodiment is applied to the output inspection of the scanning line driving circuit and the signal line driving circuit. That is, the inspection circuit unit 1
A switching circuit 1 composed of TFTs Tw1 to Tw4 is provided between 14G and the scanning lines GG1 to GG4 of the matrix display unit.
06 is arranged. The switch circuit 106 plays a role of disconnecting the electrical connection between the inspection circuit unit and the scanning line at the time of inspecting the output of the scanning line driving circuit, similarly to the switching circuit of the second embodiment. An inspection circuit having the same circuit configuration as that of the seventh embodiment is inserted between the pulse generation circuit 107 of the signal line driving circuit and the sampling circuits Tv1 to Tv4.

In this embodiment, similarly to the scanning line inspection method in the seventh embodiment, the outputs G1 to G4 of the scanning line driving circuit 101 are switched between positive and negative polarities, and the inspection transistors TFTTn1 to Tn4 and TFTs Tp1 to Tp1 are sequentially switched.
4, the output of the terminal SENa and the output of the terminal SENb are detected, so that the output of the scanning line driver circuit and the defect of the inspection circuit portion can be determined.

(Embodiment 9) FIG. 11 shows a liquid crystal display according to a ninth embodiment of the present invention. This embodiment is a combination of the inspection circuits of the first embodiment and the second embodiment. As shown in the drawing, the inspection circuits are arranged on the output side of the scanning line driving circuit and the scanning line end opposite to the output side. Things. At the time of output inspection of the scanning line driving circuit, the signal HIG is applied to the control line SW1.
By inputting H, the driving circuit and the scanning line are separated, and the output of the driving circuit 101 is inspected according to the method of the second embodiment. At the time of scanning line inspection, a signal LOW is input to the control line SW1, the output of the driving circuit is connected to the scanning lines G1 to G4, and the scanning lines are inspected according to the method of the first embodiment.

(Embodiment 10) FIG. 12 shows a tenth embodiment of the present invention.
1 shows a liquid crystal display of an embodiment. This embodiment uses a combination of the inspection circuit of the fifth embodiment and the inspection circuit of the sixth embodiment. Also in this circuit configuration, as in the ninth embodiment, the switching of the switch circuit 106 allows the inspection of the driving circuit output and the scanning line inspection.

(Embodiment 11) FIG. 13 shows an eleventh embodiment of the present invention.
1 shows a liquid crystal display of an embodiment. In the present embodiment, the position of the terminal SENa is changed in the inspection circuit of the fifth embodiment. The terminal SENa is connected to the plurality of capacitors Cy1 to Cy4 connected to the inspection TFT by the potential VCC.
Is arranged on a power supply line connected to the power supply. Using this configuration, it is possible to detect an abnormality in the scanning line as in the fifth embodiment. FIG. 14 shows the inspection circuit of the sixth embodiment.
The position of the terminal SENa is changed. Using this configuration, it is possible to detect an abnormality in the output of the scanning line driving circuit as in the sixth embodiment.

(Embodiment 12) FIG. 15 shows a twelfth embodiment of the present invention.
An example will be described. In the present embodiment, the present invention is applied particularly to the inspection of the output of the signal line driving circuit. FIG. 15 is a partial circuit diagram of the signal line driving circuit. In this embodiment, the outputs S1 to S4 output from the pulse generation circuit 107
Each of them drives two signal lines. For example,
The output S1 is input to the gates of the sampling switches Tv11 and Tv12 forming the sample and hold circuit 108. On the other hand, the drains of TFTTv11 and TFTTv12 are respectively connected to different video signal buses. Therefore, the TFTs Tv1 and Tv2 sample the video signal at the same timing, but the signal lines D1, D2
Is written with independent information.

Inspection TFTs Tt1 to Tt4 are arranged for the outputs S1 to S4 of the pulse generation circuit as in the second embodiment, and inspection TFTs Tt11 to Tt42 are arranged for the output of the sampling circuit 108. I have. In this configuration, the sampling switch Tv11
When the signal is output from .about.Tv42, the output of the sampling switch is checked according to the method of the first embodiment. At this time, if signals are input to the two video signal buses with different phases, it is possible to detect the output of each sampling switch in a time-division manner.

FIG. 16 shows a modification of the inspection circuit configuration of the sampling switch output. That is, in the configuration of FIG. 15, the inspection TFTs Tt11 to Tt42 are arranged in parallel corresponding to the respective sampling switch outputs, but in the configuration of FIG.
(For example, Tt11 and Tt12) are connected to each other in series. According to this configuration, the sampling switch Tv
11 and Tv12 are collectively detected by the inspection TFT.

Although the above-described configuration exemplifies a case in which there are two sampling switches that perform a sampling operation at the same timing, the present invention is not limited to this. It may be driven. At this time, the number of video signal buses is increased corresponding to the number of sampling switches driven simultaneously.

In each of the above embodiments, a 4 × 4 matrix liquid crystal display has been described as an example. However, the application range of the present invention is not limited to this, and an N × M matrix type display device may be used. It is needless to say that the present invention is applicable. Further, the inspection circuits of the respective embodiments can be used in appropriate combinations. Further, a plurality of inspection circuits having the same function may be provided.

Elements such as a TFT constituting a test circuit, a resistance element, a shift register constituting a driving circuit, and a sampling switch are to be formed by polysilicon TFTs on the same substrate as pixel TFTs of a matrix display section in a common process. Can be.

[0052]

According to the present invention, it is possible to easily inspect the wiring or the output of the driving circuit in response to the increase in the capacity and definition of the liquid crystal display.

[Brief description of the drawings]

FIG. 1 shows an equivalent circuit diagram of a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 shows an equivalent circuit diagram of a liquid crystal display according to a second embodiment of the present invention.

FIG. 3 shows an equivalent circuit diagram of a liquid crystal display according to a third embodiment of the present invention.

FIG. 4 shows an equivalent circuit diagram of a liquid crystal display according to a fourth embodiment of the present invention.

FIG. 5 shows an equivalent circuit diagram of a liquid crystal display according to a fifth embodiment of the present invention.

FIG. 6 shows an equivalent circuit diagram of a liquid crystal display according to a sixth embodiment of the present invention.

FIG. 7 shows an equivalent circuit diagram of a liquid crystal display according to a seventh embodiment of the present invention.

FIG. 8 is a timing chart of input and output of a test circuit according to a seventh embodiment of the present invention.

FIG. 9 shows an input / output timing chart of a test circuit according to a seventh embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of a liquid crystal display according to an eighth embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram of a liquid crystal display according to a ninth embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of a liquid crystal display according to a tenth embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram of a liquid crystal display according to an eleventh embodiment of the present invention.

FIG. 14 shows a modification of the liquid crystal display of FIG.

FIG. 15 is an equivalent circuit diagram of a liquid crystal display according to a twelfth embodiment of the present invention.

FIG. 16 shows a modification of the liquid crystal display of FIG.

[Explanation of symbols]

 Reference Signs List 101 scanning line driving circuit 102 signal line driving circuit 103 matrix display unit 104 scanning line inspection unit 105 scanning line driving circuit inspection unit 106 switch unit 107 pulse generation circuit 108 sampling unit 109 signal line inspection unit 110 ... Signal line drive circuit inspection unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI G09F 9/35 305 G09F 9/35 305

Claims (17)

[Claims] A plurality of scanning lines and a plurality of signal lines formed on a substrate and having one end to which a driving signal is supplied; and a driving transistor disposed at an intersection of the scanning lines and the signal lines. A matrix display unit that includes a pixel electrode connected to the signal line and performs image display; and a gate is connected to each of the scanning lines or the signal lines.
A plurality of inspection transistors each having a source and a drain connected to a common wiring to which an external voltage is supplied; and a capacitor inserted between each of the scanning lines or the signal lines and at least one of the common wirings. A display device, comprising: 2. The display device according to claim 1, wherein the capacitance element is inserted between the scanning line or the signal line and a gate of the inspection transistor. 3. The display device according to claim 1, wherein the capacitance element is inserted between the source or the drain and the common wiring. 4. The display device according to claim 1, wherein the inspection transistor and the capacitor are formed on the substrate in the same step as the driving transistor. 5. The display device according to claim 1, wherein a variable resistance element is inserted between one end of the common wiring and the external voltage source. 6. A scanning line driving circuit formed on a substrate and including a timing control circuit, a plurality of scanning lines to which a scanning signal output from the scanning line driving circuit is supplied, a plurality of signal lines, A matrix display unit that includes a pixel electrode connected to the signal line via a driving transistor disposed at an intersection of the scanning line and the signal line, and that performs image display; a scanning line driving circuit and the matrix display unit A plurality of test transistors, each having a gate connected to each of the scanning lines, and a source and a drain connected to a common wiring to which an external voltage is supplied, respectively; and A display device, comprising: a capacitor inserted between at least one of wirings. 7. The display device according to claim 6, wherein a switching element is disposed between a connection portion between the scanning line and the gate of the inspection transistor and the matrix display portion. 8. A signal line drive circuit formed on a substrate, comprising: a timing control circuit; and a sampling circuit having a plurality of sampling switches for sampling an image signal based on output signals output in parallel from the timing control circuit. A plurality of signal lines to which an image signal mainly supplied from the signal line driving circuit is supplied, a plurality of scanning lines,
A matrix display unit that includes a pixel electrode connected to the signal line via a driving transistor disposed at an intersection of the scanning line and the signal line, and that performs image display; and a timing control circuit and a sampling circuit. A plurality of test transistors arranged between the gates, a gate connected to each parallel output of the timing control circuit, and a source and a drain each connected to a common line to which an external voltage is supplied; and A display device comprising a capacitor element inserted between at least one of the common wirings. 9. A plurality of second inspection circuits each having a common output of the timing control circuit connected to a switch block including a plurality of adjacent sampling switches, and having a gate connected to the output of each of the sampling switches. 9. The display device according to claim 8, further comprising a first transistor, wherein the second inspection transistor is connected in series in the switch block. 10. 10. A switch block comprising a plurality of adjacent sampling switches, a common output of the timing control circuit is connected, a gate is connected to an output of each of the sampling switches, and a source and a drain are connected to an external voltage. The display device according to claim 8, further comprising a plurality of second inspection transistors connected to a common line to which is supplied. 11. A plurality of scanning lines and a plurality of signal lines formed on a substrate, one end of which is supplied with a driving signal, and the driving transistor disposed at an intersection of the scanning lines and the signal lines. Including a pixel electrode connected to the signal line,
A matrix display unit for displaying an image, a gate connected to each of the scanning lines or the signal lines,
A plurality of first conductivity type testing transistors each having a source and a drain connected to a common wiring to which an external voltage is supplied, and a gate connected to each of the scanning lines or the signal lines;
A display device comprising: a plurality of second conductivity type testing transistors each having a source and a drain connected to a common wiring to which an external voltage is supplied. 12. A capacitor inserted between each of the scanning lines or the signal lines and at least one of the common lines connected to the first conductivity type testing transistor or the second conductivity type testing transistor. The display device according to claim 11, further comprising an element. 13. The display according to claim 11, wherein the first conductivity type testing transistor and the second conductivity type testing transistor are formed on the substrate during the same step as the driving transistor. apparatus. 14. A variable resistance element is inserted between one end of the common wiring connected to the first conductivity type testing transistor or the second conductivity type testing transistor and the external voltage source. 2. The method according to claim 1, wherein
The display device according to 1. 15. A scanning line driving circuit formed on a substrate and including a timing control circuit, a plurality of scanning lines to which a scanning signal output from the scanning line driving circuit is supplied, a plurality of signal lines, A matrix display unit that includes a pixel electrode connected to the signal line via a driving transistor disposed at each intersection of the scanning line and the signal line, and performs an image display; the scanning line driving circuit and the matrix display A plurality of first-conductivity-type testing transistors, each of which has a gate connected to each of the scanning lines, and a source and a drain each connected to a common line to which an external voltage is supplied; and A gate is connected to each of the scanning lines, and a source and a drain are respectively connected to a common line to which an external voltage is supplied, which is disposed between a driving circuit and the matrix display unit. Display device characterized by comprising a plurality of second conductivity type test transistor. 16. A switching element is provided between a connection portion between the scanning line and a gate of the first conductivity type inspection transistor and the gate of the second conductivity type inspection transistor and the matrix display portion. Claim 1.
5. The display device according to 5. 17. A signal line driving circuit formed on a substrate, comprising a timing control circuit and a sampling circuit for sampling an image signal based on output signals output in parallel from the timing control circuit, and the signal line driving circuit A plurality of signal lines to which an image signal output from is supplied,
A matrix display unit that includes a plurality of scanning lines, a pixel electrode connected to the signal line via a driving transistor disposed at an intersection of the scanning line and the signal line, and that performs image display; and the timing control circuit. And a plurality of first conductivity type tests, wherein a gate is connected to each parallel output of the timing control circuit, and a source and a drain are respectively connected to a common line to which an external voltage is supplied. Transistor, a timing control circuit, and a sampling circuit, a gate is connected to each parallel output of the timing control circuit, and a source and a drain are connected to a common line to which an external voltage is supplied, respectively. And a plurality of second conductivity type testing transistors.