JPH1091603A - Start-up synchronism establishing method and abnormality monitoring method for dual-cpu system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To complete the start-up synchronism in a short time and shorten a system start-up time by making a 1st CPU reads initialization data by a 2nd CPU out and writes 1st response data, and the 2nd CPU read the 1st response data out and write 2nd response data. SOLUTION: The 1st and 2nd CPUs 11 and 21 write 1st and 2nd initialization data in a DPROM 30 respectively to initialize the system. The 1st CPU 11 reads out the 2nd initialization data out and rewrites the contents of the RAM 30 into the 1st response data. The 2nd CPU 21 reads out the 1st response data out and rewrites the contents of the RAM 30 into the 2nd response data. The 1st CPU 11 reads the 2nd response data out and considers that the start-up synchronism with the 2nd CPU 21 is established. The 2nd CPU 21 waits for a certain time and considers that the start-up synchronism with the 1st CPU 11 is established.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual CPU system, and more particularly, to a startup synchronization establishing method and an abnormality monitoring method.

[0002] In recent years, the use range of a dual CPU system has been widened and complicated. Accordingly, higher speed, higher accuracy and simplification of the dual CPU system are required.

[0003]

2. Description of the Related Art Conventionally, an industrial robot, a transfer device, and the like are provided with a plurality of arms for gripping, pressing, and rotating a workpiece. The workpiece is processed or transported to a predetermined location by performing a predetermined cooperative operation with each of the other arms. That is, a control device for controlling the drive of each arm is provided for each arm. Then, the arm performs a predetermined operation by the control device.
Further, each control device exchanges data with another control device to enable smooth cooperative operation between its own arm and another arm.

FIG. 1 shows a system configuration for explaining data transfer between two control devices. This system configuration is a dual CPU system. The first control device 10 includes a first central processing unit (CPU) 11, a first specific memory 12 including a RAM and a ROM, and a first peripheral interface 13. Further, the second control device 20 includes a second central processing unit (CPU) 21, a RAM,
And a second specific interface 22 composed of a ROM and the like, and a second peripheral interface 23.
A dual-port RAM (hereinafter, referred to as DPRAM) 30 readable and writable by both the control devices 10 and 20 is provided between the first and second control devices 10 and 20.

A first CPU 11 and a second CPU 11
Reference numeral 21 transmits and receives transmission data via the DPRAM 30 and controls the driving of each arm. An interrupt circuit (not shown) or a bus arbitration circuit (not shown) is provided in order to avoid a collision in which the CPUs 11 and 21 write data at the same time when transmitting and receiving the transmission data.

That is, for example, when the first CPU 11 writes transmission data for the second CPU 21 to the DPRAM 30, an interrupt signal is output from the first CPU 11 to the second CPU 21 via an interrupt circuit or a bus arbitration circuit. . Then, the second CPU 21 suspends the operation of reading the data or writing the data to the DPRAM 30 until the first CPU 11 finishes writing the transmission data. As a result, a collision due to writing or reading of transmission data between the two CPUs 11 and 21 is avoided.

Further, Japanese Patent Application Laid-Open No. Hei 5-346908 discloses that
A system for exchanging data via the DPRAM 30 without using an interrupt circuit has been proposed. This system has a dedicated storage area composed of a status area and a data area used for data transfer from the sub CPU to the main CPU in the DPRAM, and a sub C
A status area used for data transfer to the PU and a dedicated storage area composed of a data area are provided. Therefore, data from the sub CPU to the main CPU and data from the main CPU to the sub CPU are written and read in separate storage areas, respectively.
Collisions due to data writing or reading of both CPUs are avoided.

In the system shown in FIG. 1, the first and second controllers 10 and 20 are provided with hardware such as a watchdog timer (not shown). The watchdog timer includes a first and a second C
This is a circuit for monitoring whether the PU 11 or 21 has runaway for some reason. This is, for example, the first CPU 11
Despite the runaway and abnormal condition, the second CP
Unusual first U21 written to DPRAM 30
This is to avoid executing the processing operation based on the transmission data from the CPU 11.

[0009]

By the way, the first and second control devices 10 and 20 are simultaneously turned on the system power supply, or the first and second CPUs 1 and 20 are reset.
1 and 21 start simultaneously, the first and second C
The PUs 11 and 21 independently execute processing operations for system initialization. At this time, the first and second CPs
The operation processing for initialization of the system of U11 and U21 differs depending on the load and the like. That is, the first and second CPUs 1
1 and 21 have different initialization completion times.
As a result, after completing the initialization, the first and second CPs
If U11 and 21 independently execute the processing for operating the arms, the operation timing of each arm is shifted, and the predetermined cooperative operation cannot be performed. Therefore, the CPU that has been initialized quickly waits until the other CPU completes the initialization (after the start-up is synchronized), and then the CPUs 11 and 21 start the program processing of the cooperative operation of the arms. Is desirable.

However, since the time for the CPUs 11 and 21 to complete the system initialization is not known, the time required for the initialization to be completed after power-on or reset (start-synchronization completion time) is sufficiently long in view of safety. A time is set, and when the time elapses, both CPUs 11 and 21 assume that initialization has been completed and startup synchronization has been achieved, and then proceed to the next processing operation. Therefore, since the start-up synchronization time is a sufficiently long time in consideration of safety, there has been a problem that the system startup time is prolonged.

When monitoring the above-mentioned abnormality of the CPU, it is time-consuming to judge the abnormality due to the use of a watchdog timer.
The PU has a problem that it malfunctions. further,
Provision of a circuit such as a watchdog timer also has a problem that the circuit scale of each of the control devices 10 and 20 becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. It is an object of the present invention to shorten the start-up synchronization in a short time to shorten the system start-up time, and to detect a CPU abnormality. It is an object of the present invention to provide a dual CPU system which can judge abnormality detection without using the detection circuit and can simplify the circuit scale.

[0013]

According to a first aspect of the present invention, both CPUs are provided between a first CPU and a second CPU.
In a dual-CPU system that provides a dual-port RAM accessible from the CPU and transmits and receives data between the two CPUs via the dual-port RAM, the dual-port RAM writes data to the first CPU and stores data in the second CPU. A first storage area for reading data from the first CPU and a second storage area for writing data to the second CPU and reading data from the first CPU; The first CPU writes the first initialization data in the first storage area at power-on, initializes the system, and writes the second initialization data of the second CPU in the second storage area. After waiting until the initialization data is read, first response data indicating that the second initialization data has been read is written to the first storage area, and the second response data is written to the first storage area. PU is after waiting until reading the second response data based on the reading of the first response data with reading the first response data, both C
It is determined that the initialization of the PU has been completed, and the second CPU
Writes the second initialization data into the second storage area when the power is turned on, initializes the system, and sends the first response data indicating that the second initialization data has been read. A dual CPU system configured to wait for reading and then determine that initialization of both CPUs has been completed after writing the second response data indicating that the first response data has been read into a second storage area The gist is the method of establishing startup synchronization in.

According to a second aspect of the present invention, there is provided a dual port RAM between the first CPU and the second CPU, the dual port RAM being accessible from both CPUs.
A dual CPU system for transmitting and receiving data between both CPUs via the
Performs data writing of a plurality of predetermined types of monitoring data on the first CPU and performs the second CP
A first storage area for reading the data from U, and a second storage area for writing the plurality of types of monitoring data to the second CPU and reading the data to the first CPU. The first CPU compares the monitoring data written in the first storage area with the monitoring data read from the second storage area, and the two monitoring data are determined in advance. The monitoring data in the first storage area is rewritten in a predetermined order each time the relationship is established, and the first
The second CPU compares the monitoring data written in the second storage area with the monitoring data read from the first storage area so that the monitoring data in the storage area is not rewritten. Each time the monitoring data has a predetermined relationship, the monitoring data in the second storage area is rewritten in a predetermined order.
The first and second CPUs respectively count the number of times when a predetermined relationship is not established, and clear the count value when the relationship is established when the relationship is not established. At the same time, when the count value exceeds a predetermined value, at least one of the CPUs is determined to be abnormal, and the first and second CPs are determined.
The initial writing of the monitoring data by U is performed by the first CPU
In one of the second CPU and the second CPU, the monitoring data is written such that the predetermined relationship is established between the two monitoring data, and the other is not written so that the predetermined relationship is not established between the two monitoring data. The rewriting order of the monitoring data by the second CPU is such that the monitoring data is rewritten so that the predetermined relationship is established between the two monitoring data for which the predetermined relationship is not established, and the first and second monitoring data are rewritten. The gist is an abnormality monitoring method in a dual CPU system in which both monitoring data alternately establish a predetermined relationship in the CPU.

According to a third aspect of the present invention, there is provided a dual port RAM accessible between the first CPU and the second CPU from both CPUs.
A dual CPU system for transmitting and receiving data between both CPUs via the
Are a first storage area for writing data to the first CPU and reading data to the second CPU, and a first storage area for writing data to the second CPU.
A second storage area for reading data from the first CPU, the first CPU writes first initialization data to the first storage area when the power is turned on, and then initializes the system. And waits until the second initialization data of the second CPU written to the second storage area is read, and then sends the first response data indicating that the second initialization data has been read to the first CPU. In the storage area of the second CP
U reads the first response data and
After waiting for reading of the second response data written to the second storage area based on the reading of the response data, it is determined that the initialization of both CPUs has been completed.
The first CPU writes the second initialization data in the second storage area at power-on, initializes the system, and reads the first initialization data written in the first storage area. After waiting for reading of the first response data indicating that the first response data has been read, the initialization of both CPUs has been completed after writing the second response data indicating that the first response data has been read to the second storage area. After the initialization of both CPUs is completed, the first CPU writes a plurality of types of predetermined monitoring data in the first storage area, and the second CPU The first CPU writes the plurality of types of monitoring data in the area and compares the monitoring data written in the first storage area with the monitoring data read from the second storage area. Data is in a predetermined relationship. Each time, the monitoring data in the first storage area is rewritten in a predetermined order, and when the data is not in a predetermined relationship, the monitoring data in the first storage area is not rewritten. Comparing the monitoring data written in the second storage area with the monitoring data read from the first storage area, and monitoring the second storage area each time the two monitoring data have a predetermined relationship. The first and second CPUs rewrite the monitoring data in the predetermined order and do not rewrite the monitoring data in the second storage area when the monitoring data is not in the predetermined relationship. When the relationship is not established, the number of times is counted, and when the relationship is established, the count value is cleared.When the count value exceeds a predetermined value, at least one of the CPUs is abnormal. In the initial writing of the monitoring data by the first and second CPUs, a predetermined relationship between the two monitoring data is established in one of the first CPU and the second CPU, On the other hand, the monitoring data is written so that the predetermined relationship is not established between the two monitoring data, and the rewriting order of the monitoring data by the first and second CPUs is the same as the order in which the predetermined relationship is not established. In a dual CPU system, the monitoring data is rewritten so that a predetermined relationship is established between the monitoring data, and the first and second CPUs alternately establish a predetermined relationship between the two monitoring data. The gist is an abnormality monitoring method.

(Operation) According to the first aspect of the present invention,
The first CPU writes first initialization data in a first storage area when the power is turned on. The second CPU writes the second initialization data in the second storage area when the power is turned on. Next, the first CPU waits until the second initialization data is written to the second storage area. When the first CPU reads the second initialization data, the first CPU writes the first response data in the first storage area and waits.

When the second CPU reads the first response data written in the first storage area, the second CPU writes the second response data in the second storage area, and then the initialization of both CPUs is completed. to decide. On the other hand, when the first CPU reads the second response data written in the second storage area,
It is determined that the initialization of the PU has been completed.

Therefore, even if the time for completing the initialization of each system in both CPUs is different, it is determined that the initialization is not completed until both CPUs are initialized. Moreover, this determination can be made only by the processing operations of both CPUs.

According to the second aspect of the present invention, the first storage area and the second storage area are first monitored by either one of the first CPU and the second CPU, for example, the first CPU. Data has a predetermined relationship, and the second CPU
, The monitoring data is written such that the predetermined relationship between the two monitoring data does not hold. Then, after the comparison, the first CPU for which the relationship is established is not established for the second CPU.
Is rewritten so that the following holds true. At this time, the relationship between the two monitoring data in the first CPU is not established by this rewriting. On the other hand, the second CP
By rewriting in U, the two monitoring data have a predetermined relationship. Then, similarly, the first CPU rewrites the monitoring data so that the predetermined relationship is established between the two monitoring data.

Therefore, when both CPUs are operating normally, the first CPU and the second CPU alternately write data in the first and second storage areas so that a predetermined relationship is established. The monitoring data will be rewritten. Conversely, when one of them is not operating normally, the rewriting is not performed any more, and the number of times that the rewriting is not satisfied is measured by the counter, and it is determined that the rewriting is abnormal. Moreover, this determination can be made only by the processing operations of both CPUs.

According to the third aspect of the present invention, when the power supply is turned on, both CPs are activated in the same manner as in the first aspect of the present invention.
It is determined that U has been initialized, and as soon as both CPUs are initialized, it is determined whether one of the two CPUs is operating normally in the same manner as in the second aspect of the invention.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, in the dual CPU system shown in FIG. 1, transmission / reception of transmission data is performed without using an interrupt circuit or a bus arbitration circuit, and abnormality is detected without using a watchdog timer. For this reason, the present embodiment is characterized by the configuration of the storage area of the DPRAM 30 and the processing operations of the CPUs 11 and 21. For convenience of explanation, the same components are denoted by the same reference numerals, and the details are omitted.

FIG. 2 is a schematic diagram for explaining the configuration of the storage area of the DPRAM 30. In FIG.
The AM 30 is provided with first to sixth data areas 31 to 36, and each of the data areas 31 to 36 is used for exchanging data with the first and second CPUs 11 and 21.

The first data area 31 as a first storage area is a 1-byte storage area, and the first CPU 1
1 is a storage area where only the identification data can be written by the first CPU 21 and only the data can be read by the second CPU 21. The second data area 32 as a second data area is a 1-byte storage area, in which only the identification data can be written by the second CPU 21 and the data can only be read by the first CPU 11. Area. The first and second data areas 31 and 32 are used for processing operations for establishing startup synchronization of the first and second CPUs 11 and 21, an abnormality monitoring processing operation, and a transmission data transfer processing operation. .

The third data area 33 is a 1-byte storage area in which only the identification data can be written by the first CPU 11 and only the identification data can be read by the second CPU 21. . The fourth data area 34 is a 1-byte storage area,
This is a storage area where only the identification data can be written by the second CPU 21 and only the data can be read by the first CPU 11. And the third and fourth
Data areas 33 and 34 are the first and second CPU 1
It is used for transmission data transfer processing operations of 1, 21.

The fifth data area 35 is a storage area composed of many bytes, in which only the transmission data can be written by the first CPU 11 and the second C area.
This is a storage area in which the PU 21 can only read data. The sixth data area 34 is a storage area composed of a large number of bytes, in which only the transmission data can be written by the second CPU 21 and the first CPU 11
Is a storage area from which data can only be read. The fifth and sixth data areas 35 and 36 are used for the transmission data transfer operation of the first and second CPUs 11 and 21.

Next, the start-up synchronization establishing operation, the abnormality monitoring operation, and the transmission data transfer operation performed by the first and second CPUs 11 and 21 based on the configuration of the DPRAM 30 will be described. (Start-up synchronization establishment processing operation) The start-up synchronization establishment processing operation is performed when the common power switch of the first and second control devices 10 and 20 is turned on and started or when the CPU 11 is reset. Reference numeral 21 denotes processing operations from completion of initialization of the system to determination of whether data transmission / reception is possible with each other. FIG. 3 shows the first and second CPUs 1.
9 is a flowchart for explaining the startup synchronization establishment processing operation of the first and second embodiments.

When the common power switch is turned on and activated or when a reset is applied, the first CPU 11 initializes the first and second data areas 31 and 32 of the DPRAM 30 in step 100, that is, initializes. After writing “00h (h means hexadecimal notation)” as the coded data, the system is initialized. On the other hand, the second CPU 2
In step 200, similarly, after writing "00h" as initialization data in the second and fourth data areas 32 and 34 in step 200, the system is initialized.

When the first CPU 11 completes the initialization of the system, it reads the contents of the second data area 32 in step 101 and proceeds to step 102 where the second data area 32 is read.
It is determined whether or not the content of the data area 32 is “00h” as the second initialization data. That is, in steps 101 and 102, the second CPU 21
It is determined whether the initialization of the system by 00 has been completed. Therefore, the first CPU 11 performs steps 101 and 10 until the second CPU 21 completes the initialization of the system.
The operation of Step 2 is repeated and the operation waits.

When the content of the second data area 32 is "00h", the first CPU 11
Then, the process proceeds to step 104, where the contents of the first data area 31 are rewritten from “00h” as the first initialization data to “FFh” as the first response data, and then the process proceeds to step 104.
In step 104, the first CPU 11 reads the contents of the second data area 32, and in step 105, the read contents are "FF" as the second response data.
h ”.

On the other hand, the second CPU 21
In step 1, the content of the first data area 31 is read, and the process proceeds to step 202 to determine whether the content of the first data area 31 is "FFh" as first response data. That is, the second CPU 21 itself (the second CP)
The first CPU 11 determines that U) has been initialized, and determines whether the processing based on the determination result (rewriting the contents of the first data area 31 from “00h” to “FFh”) has been completed. .

When the content of the first data area 31 is "FF
h, the second CPU 21 in step 203 changes the contents of the second data area 32 from “00h” as the second initialization data to “FF” as the second response data.
After that, the process proceeds to step 204. On the other hand, the first CPU 11 reads the rewritten content of the second data area 32 in step 104, determines that the read content is “FFh” in step 105, It is determined that the startup synchronization has been established during the period, and the mode shifts to the mode of the abnormality monitoring processing operation.

On the other hand, after rewriting the contents of the second data area 32 from "00h" to "FFh", the second CPU 21 proceeds to step 204 and waits for a certain time. During this fixed time, the first CPU 11 sets the second data area 3
2 is the time required to read the contents written in and determine the contents. And after waiting for a certain time,
The second CPU 21 determines that the startup synchronization has been established with the first CPU 11, and shifts to the mode of the abnormality monitoring processing operation.

In the startup synchronous processing operation, the load on the first CPU 11 is large and the second CPU 21
When the system initialization is further delayed, the second CPU 21
Waits until the first CPU 11 completes the initialization of the system in steps 201 and 202 and rewrites the contents of the first data area 31 to “FFh” in step 103. When the contents of the first data area 31 are rewritten, the second CPU 21
Is rewritten to “FFh”. That is, at this point, the first CPU 11 completes the initialization, and notifies the second CPU 21 that is waiting. And the first CP
U11 waits in steps 104 and 105 until the second CPU 21 confirms that.

The second CPU 21 executes steps 201 and 20
After confirming that the first CPU 11 has been initialized in Step 2, it is rewritten to "FFh" of the second data area 32 and waits for a certain time. Therefore, the first CPU 1
1 is the time required to read the contents written in the second data area 32 and determine the contents, so that the first CPU 11
The processing operation of 105 is completed. As a result, when the common power switch is turned on and activated or when a reset is applied, the second CPU 21 completes the system initialization of the first CPU 11 even if the system initialization of the first CPU 11 is late. Until the next processing operation.

On the other hand, when the load on the first CPU 11 is small and faster than the system initialization than the second CPU 21, the first CPU 11
CPU 21 completes the initialization of the system and
At 1, the process waits until the content of the second data area 32 is rewritten to “00h”. When the contents of the second data area 32 are rewritten, the first CPU 11 rewrites the contents of the first data area 31 to “FFh”. That is, at this point, the first CPU 11
Confirms that the initialization of the system has been completed, and notifies the second CPU 21 to that effect. And the first CP
U11 waits in steps 104 and 105 until the second CPU 21 confirms that.

Therefore, when the common power switch is turned on and turned on, or when a reset is applied, the first CPU 11 is initialized faster than the second CPU 21 even if the system is initialized earlier.
CPU 11 does not proceed to the next processing operation until the second CPU 21 completes the system initialization.

Moreover, when judging whether or not the initialization of the system has been completed, it is only necessary to rewrite the contents of the first and second data areas 31, 32, and the rewritten contents are read and recognized by each other. To determine that startup synchronization has been established.
Therefore, it is necessary to use a timer as compared with the conventional case where the start-up synchronization time is set to a sufficiently long time for safety and it is determined that the start-up synchronization has been established after the set time has elapsed. Thus, it is possible to surely recognize that the start-up synchronization has been established, and to shorten the system startup time. (Abnormality monitoring processing operation)
This refers to a processing operation for detecting whether or not 11 and 21 are abnormal.
FIG. 4 is a flowchart for explaining the abnormality monitoring processing operation of the first and second CPUs 11 and 21.

When the startup synchronization processing operation is completed, the first and second CPUs 11 and 21 execute operations according to the flowchart shown in FIG. First CPU 1
1 clears the contents of the counter provided in the first unique memory 12 in step 300, and then proceeds to step 301 to store “1F” as monitoring data in the first data area 31.
h) is written.

After writing the contents of “1Fh”, the first CPU 11 in step 302
2. Read the contents of the communication flag provided in
3 whether the content of the communication flag is set, that is, "1"
Is determined. That is, the first CPU 11 determines whether or not to shift to a transmission data transfer mode for exchanging data with the second CPU 21.
When the content of the communication flag is “1”, the first CP
U11 proceeds to step 304, executes a data transfer routine for performing a transmission data transfer processing operation described later, and then proceeds to step 305.

On the other hand, when the content of the communication flag is "0",
The first CPU 11 immediately proceeds to step 305 and reads the contents of the second data area 32. Then, the first C
The PU 11 proceeds to step 306 and compares the content written in the first data area 31 with the content of the second data area 32 read in step 305 to determine whether or not a predetermined relationship exists. The relationship between the content of the first data area 31 and the content of the second data area 32 is predetermined, and in the present embodiment, “1Fh” vs. “27h”, “27h” vs. “3Ch”, or “3Fh”. 3C
h ”and“ 1Fh ”.

For example, when the content of the monitoring data in the first data area 31 is "1Fh" and the content of the monitoring data in the second data area 32 is "27h", the process proceeds to step 307 as corresponding. Conversely, the content of the monitoring data in the first data area 31 is “1Fh”.
On the other hand, the content as monitoring data in the second data area 32 is “3Ch” other than “27h” or “1F”.
At the time of "h", it is determined that it does not correspond and the process proceeds to step 309.

In step 307, the first CPU 1
1 rewrites the contents of the first data area 31 based on the contents of the second data area 32 at that time. In the present embodiment, it is determined in advance, and if the content of the second data area 32 at that time is “1Fh”, the first data area 3
1 is “27h”, if the content of the second data area 32 is “27h”, the content of the first data area 31 is “3Ch”, and the content of the second data area 32 is “3C”.
If "h", the contents of the first data area 31 are rewritten to "1Fh".

When the contents of the first data area 31 have been rewritten, the first CPU 11 proceeds to step 308 to clear the contents of the counter provided in the first unique memory 12 and then proceeds to step 302 described above. Return and execute the same operation.

On the other hand, if it is determined in step 306 that the condition does not apply and the process proceeds to step 309, the first CPU
11 adds 1 to the content of the counter. After the addition, the first CPU 11 determines in step 310 whether or not the content of the counter has exceeded a predetermined reference value Y. That is, the previously performed step 306
Y times (for example, 10 times)
It is determined whether the number of times has exceeded the number of times. If the number does not exceed the number of times of Y, the flow returns to step 302 to execute the same operation as described above.
If the number of times has exceeded Y times, the first CPU 11 determines that the second CPU 21 is abnormal and ends the abnormality monitoring processing operation.

On the other hand, when the second CPU 21 proceeds to the abnormality monitoring processing operation, it clears the contents of the counter provided in the second specific memory 22 in step 400 and then proceeds to step 401
Then, the contents of "27h" are written in the second data area 32.

After writing the contents of "27h", the second CPU 21 reads the contents of the first data area 31 in step 402, and determines whether or not the contents are "00h" in step 403. That is, the first CPU 1
It is determined whether or not 1 has written "00h" in the first data area 31 in order to execute a transmission data transfer processing operation for transmitting and receiving data to and from a second CPU 21 described later.

When the content of the first data area 31 is "00h", the second CPU 21 proceeds to step 404.
Then, "00h" is written in the second data area 32, and subsequently, the process proceeds to step 405, and after executing a data transfer routine for performing a transmission data transfer processing operation described later, proceeds to step 406.

On the other hand, when the contents of the first data area 31 are not "00h", the second CPU 21 immediately proceeds to step 406 and writes the contents written in the first data area 31 and the second data area 32. Then, it is determined whether or not the contents are in a predetermined relationship by comparing the contents. Second data area 3 for the contents of first data area 31
The relationship in the content of No. 2 is predetermined, and in the present embodiment, “27h” vs. “1Fh”, “3Ch” vs. “27
h ”or one of“ 1Fh ”vs.“ 3Ch ”.

For example, the content of the first data area 31 is "27h" and the content of the second data area 32 is "1F".
In the case of "h", it is determined to be applicable, and the process proceeds to step 407.
Conversely, when the content of the first data area 31 is "27h" and the content of the second data area 32 is "27h" other than "1Fh" or "3Ch", it is determined that the content does not correspond to step 409. Move on to In step 407, the second CPU 21 rewrites the contents of the second data area 32 based on the contents of the first data area 31 at that time. In this embodiment, the content of the first data area 31 is "27h" if the content of the first data area 31 is "1Fh" at that time, and the content of the first data area 31 is "27h". ", The content of the second data area 32 is set to" 3Ch "and the first data area 3
If the content of 1 is "3Ch", the content of the second data area 32 is rewritten to "1Fh".

After rewriting the contents of the second data area 32, the second CPU 21 proceeds to step 408, clears the contents of the counter provided in the second specific memory 22, and then proceeds to step 402 described above. Return and execute the same operation.

On the other hand, if it is determined in step 406 that the condition does not apply and the process proceeds to step 409, the second CPU
21 adds 1 to the content of the counter. After the addition, the second CPU 21 determines in step 410 whether or not the content of the counter has exceeded a predetermined reference value Z. That is, step 406 performed earlier
The number of times that does not correspond to the judgment of (1) is continuously Z times (for example, 10
It is determined whether the number of times has exceeded the number of times. If the number does not exceed the number of times of Z, the flow returns to step 402 to execute the same operation as described above.
If the number of times exceeds Z, the second CPU 21 determines that the first CPU 11 is abnormal and ends the abnormality monitoring processing operation.

That is, when the startup synchronization probability processing operation is completed and the operation proceeds to the abnormality monitoring processing operation, the first CPU 11 stores “1Fh” in the first data area 31 in step 301.
Is written, and the second CPU 21 writes “27h” in the second data area 32 in step 401. Now, in a state where transmission / reception of data is not performed, the first CPU 11 proceeds to step 305 via steps 302 and 303, and proceeds to step 305 of the second data area 32.
After reading the contents of "h", the process proceeds to step 306. On the other hand, in parallel with this, the second CPU 21
After reading the contents of "1Fh" in the first data area 31, the process proceeds to step 406 via step 403.

In step 306, the first CPU 1
1 compares the relationship between the contents of the first data area 31 and the contents of the second data area 32. At this time, since the contents of the first data area 31 are “1Fh” and the contents of the second data area 32 are “27h”, the first CPU 11
Are determined to have a predetermined relationship, and the flow proceeds to step 307. The first CPU 11 rewrites the contents of the first data area 31 based on the contents of the second data area 32 at that time. At this time, since the content of the second data area 32 is “27h”, the content of the first data area 31 is changed to “1”.
Fh ”to“ 3Ch ”. Then, after clearing the counter in step 308, the first CPU 11
Goes to step 305 again via steps 302 and 303. At this time, the first CPU 11 reads the content of “27h” in the second data area 32 that has not been rewritten.

On the other hand, in step 406, the second C
The PU 11 compares the relationship between the contents of the first data area 31 and the contents of the second data area 32. At this time, the first
Of the second data area 32 is "1h" and the content of the second data area 32 is "27h".
U21 determines that there is no predetermined relationship, and step 409
Move on to The second CPU 21 sets the content of the counter to “1”.
In step 410, it is checked whether or not the content of the counter has exceeded Z times. At this time, the second CPU 21 determines that the count has not exceeded Z times yet,
Return to

In this step 402, the second CP
U11 reads the contents of “3Ch” in the first data area 31 rewritten by the first CPU 11 in step 307. Then, the second CPU 21 compares the content of “3Ch” in the first data area 31 with the content of “27h” in the second data area 32, and determines that there is a predetermined relationship. The second CPU 21 determines in step 407 that the content of the first data area 31 is “3Ch”.
Therefore, the content of the second data area 32 is rewritten from “27h” to “1Fh”. Then, after clearing the counter in step 408, the second CPU 21 returns to step 402 again.

On the other hand, in step 306, the first C
The PU 11 compares the content of “27h” in the second data area 32 before rewriting read in step 305 with the “3Ch” of the first data area 31 previously rewritten. Then, the first CPU 11 determines that there is no predetermined relationship, and proceeds to step 309. First
CPU 11 adds "1" to the content of the counter and checks in step 310 whether the content of the counter has exceeded Y times. At this time, the first CPU 11 returns to step 305 via steps 302 and 303, assuming that the number has not exceeded Y times.

In this step 305, the first CP
U11 reads the contents of “1Fh” in the second data area 32 rewritten by the second CPU 21 in step 407. Then, the first CPU 11 compares the content of “3Ch” in the first data area 31 with the content of “1Fh” in the second data area 32, and determines that there is a predetermined relationship. The first CPU 11 determines in step 307 that the content of the second data area 32 is “1Fh”.
Therefore, the content of the first data area 31 is rewritten from “3Ch” to “27h”. Then, after clearing the counter in step 308, the first CPU 11 returns to step 305 again.

Therefore, when both the CPUs 11 and 21 are operating normally, the contents of the first and second data areas 31 and 32 are rewritten alternately, and when the contents are not rewritten, "1" is set. The contents of the added counter are cleared alternately. As a result, when both CPUs 11 and 21 are operating normally in a state where transmission / reception of data is not performed, the contents of the first and second data areas 31 and 32 always have a predetermined relationship alternately. To establish. The content of each counter does not exceed Y times and Z times.

On the other hand, if the second CPU 21 causes an abnormality for some reason and the rewriting in step 407 is not performed, the first CPU 11 stops the relationship in step 306 and the content of the counter becomes Y. If the number of times has exceeded, the second CPU 21 determines that an abnormality has occurred for some reason. Also, if the first CPU 11 causes an abnormality for some reason and the rewriting in step 307 is not performed, the second CPU 21 does not satisfy the above relation in step 406 and the content of the counter exceeds Z times. Then, it is determined that the first CPU 11 has caused an abnormality for some reason.

Accordingly, it is possible to detect and determine the abnormality of the partner CPU without using a detection circuit for detecting the abnormality as in the related art. Next, a data transfer routine (transmission data transfer processing operation) of step 304 executed by the first CPU 11 and step 405 executed by the second CPU 21 when transmission / reception of transmission data is started halfway will be described. (Transmission Data Transfer Processing Operation) The transmission data transfer processing operation is a processing operation for each CPU 11 and 21 to transfer transmission data to each other via the DPRAM 30. In the present embodiment, steps 304 and 405 are performed.
Of the data transfer routine. Here, for convenience of explanation, a case where transmission data is transmitted from the first CPU 11 to the second CPU 21 will be described as an example.

Now, the first CPU 11 is replaced with the second CPU 21
When the communication flag and the transmission flag of “1” are set in the first specific memory 12 to transmit the transmission data to the first
CPU 11 reads the communication flag in step 302 and executes the data transfer routine of steps 303 to 304.

FIGS. 5 and 6 show the first and second CPUs 11 and 12, respectively.
21 is a flowchart for explaining a data transfer routine of No. 21; First, the first CPU 11 first proceeds to step 500.
At step 501, a transmission flag of "1" is read into the first unique memory 12, and at step 501, it is confirmed that the flag is "1". Step 50
2, the first CPU 11 is connected to the first specific memory 12
Is transferred to the fifth data area 35 of the DPRAM 30 and transferred to the write step 503. In step 503, the first CPU 11 writes the contents of “FFh” in the third data area 33, and then proceeds to step 505. In step 501, when the first CPU 11 sets the communication flag to "0", the first CP
U11 writes the content of "00h" in the third data area 33 in step 504, and proceeds to step 505.

In other words, "FFh" written in the third data area 33 has a content meaning that there is data to be transmitted. “00h” written in the third data area 33 is a content indicating that there is no data to be transmitted.

In step 505, the first CPU 1
1 writes the content of “00h” in the first data area 31. “0” written in the first data area 31
The content of “0h” means that data is exchanged with the second CPU 21 (in this case, that there is data to be transmitted to the second CPU 21).
This is for executing the data transfer routine of step 405 through steps 02-404.

When "00h" is written in the first data area 31, the first CPU 11 executes steps 506 and 507.
Move on to The first CPU 11 reads the contents of the second data area 32 at step 506, checks at step 506 whether the contents are "FFh",
h ”. That is, the first CPU 11
Checks whether the second CPU 21 has read the transmission data written in the fifth data area 35, and waits until the reading is completed.

On the other hand, the second CPU 21
By writing “00h” to the first data area 31 in step 505 by 11, the process proceeds to the data transfer routine (transmission data transfer processing operation) in step 405 via steps 402, 403 and 404 shown in FIG. Note that the second CPU 21 determines in step 404 that the second
"00h" is written in the data area 32 of the data area 32. The contents of the data area "00h" means that the transmission data recorded in the fifth data area 35 has been read.

When entering the data transfer routine, the second CP
U21 moves to step 600 shown in FIG.
The contents of the third data area 33 written by U11 are read, and the flow proceeds to step 601. At this time, the first C
Since the PU 11 has written the content of “FFh” in the third data area 33 in step 503, the second CP
U21 moves from step 601 to step 602. In step 602, the second CPU 21 executes the first C
The PU 11 reads the transmission data written in the fifth data area 35 in Step 502 and writes the transmission data in the second specific memory 22. Therefore, at this time, the second CPU 1
1 means that the transmission data from the first CPU 11 has been input.

When the transmission data is input, the second CPU 2
In step 603, the second CPU 21 sets the first C
The content of the transmission flag provided in the second specific memory 22 indicating whether to transmit the transmission data to the PU 11 is read, and the process proceeds to Step 604. In step 604, the second C
The PU 21 determines whether the transmission flag is “1” and determines whether the first CP
It is determined whether there is data to be transmitted to U11. In this case, since the transmission data is not transmitted to the first CPU 11, the transmission flag is "0" and the second CP
U21 moves on to step 607, where the fourth data area 3
After writing “00h” to No. 4, the process proceeds to step 608.

When the transmission flag is "1", it is determined that there is transmission data, and the second CPU 21 proceeds to step 605.
To the first CP stored in the second specific memory 22.
After transferring and writing the transmission data to be transferred to U11 to the sixth data area 36 of the DPRAM 30, the process proceeds to step 606. In step 606, the second CP
U21 proceeds to step 608 after writing the contents of "FFh" in the fourth data area 34. That is, “FFh” written in the fourth data area 34 is a content that notifies the first CPU 11 that there is data to be transmitted. “00h” written in the fourth data area 34 is a content notifying that there is no data to be transmitted.

When the transmission data from the first CPU 11 is input, the second CPU 21 writes the contents of “FFh” in the second data area 32 in step 608.
In other words, the second CPU 21 notifies the first CPU 11 waiting at steps 506 and 507 that the reading has been completed.

The first CPU 11 determines that the content of “FFh”, that is, the transmission data has been read out in the second data area 32, and determines in step 508 the fourth data area 3
After reading the contents of step No. 4, the process proceeds to step 509. In step 509, the first CPU 11 determines whether the contents of the fourth data area 34 are “FFh”, that is, whether there is transmission data from the second CPU 21. At this time, since the content of the area 34 is “00h”, the first CPU 11
Moves to step 512. The fourth data area 34
Is "FFh", the first CPU 11 sends the second C
Step 510 assuming that there is transmission data from PU 21
The transmission data transferred to and written in the sixth data area 36 is written in the first unique memory 12 and
Then, the process proceeds to step S11, where a reception flag provided in the unique memory 12 indicating that data has been received is set, and thereafter, the process proceeds to step S512.

In step 512, the first CPU 1
1 writes the content of “3Ch” in the first data area 31. The contents of the "3Ch" indicate that when the transfer routine is completed and the process returns to the abnormality monitoring processing operation shown in FIG. This is to make it possible.

When the contents of "3Ch" are written in the first data area 31, the first CPU 11 proceeds to step 513,
At 514, the process waits for the content of the second data area 32 to be rewritten to “1Fh” by the second CPU 21.

On the other hand, the second CPU 21
11, the content of the first data area 31 is "3Ch"
When it is determined in steps 609 and 610 that the data area has been rewritten,
Write the contents of “1Fh” to 2. As described above, when the transfer routine is completed and the process returns to the abnormality monitoring processing operation shown in FIG. 4, the contents of “1Fh” are set so that the conditions are met in steps 306 and 406 only at the first time. Is to be able to do. Then, the second CPU 21 proceeds to step 6
Then, the process proceeds to step 12, where "00h" is written in the fourth data area 34, the data transfer routine is completed, and the process returns to the abnormality monitoring processing operation.

When the first CPU 11 determines in steps 513 and 514 that the content of the second data area 32 has been rewritten to “1Fh” by the second CPU 21, the process proceeds to step 515 and the third data The contents of "00h" are written in the area 33 to complete the data transfer routine and return to the abnormality monitoring processing operation.

Therefore, the first and second CPUs 11 and 21
Returns to the abnormality monitoring processing operation, the first data area 3
1 is “3Ch”, and the second data area 32 is “1Fh”
Are written, and the two contents are contents in which a predetermined relationship is established in step 306, and the next predetermined relationship is established in step 406. As a result, even when the transmission data transfer processing operation is completed, it is possible to immediately return to the abnormality monitoring processing operation.

Next, the features of the dual CPU system such as the industrial robot configured as described above will be described below. (1) In the present embodiment, the first CPU 11 and the second C
Even if the initialization of each system of the PU 21 is different, a startup establishment processing operation prevents the next processing operation from proceeding until both systems have been initialized. In addition, the first and second CPUs 11 and 21 determine whether or not the system initialization has been completed.
It is only necessary to rewrite the contents of the first and second data areas 31 and 32 of the M30 and to read and recognize the rewritten contents respectively to determine whether the startup synchronization has been established.

Therefore, as in the prior art, a timer circuit is provided, and the start-up synchronization time is set to a sufficiently long time in consideration of safety, and the start-up synchronization is established after the set time has elapsed. It is possible to shorten the system start-up time and to reduce the circuit scale, as compared with the case where the judgment is made.

(2) In the present embodiment, the first CPU 1
The first and second CPUs 21 monitor an abnormality of the system of each other by an abnormality monitoring processing operation. Moreover, this abnormality monitoring processing operation is performed by the first and second CPUs.
The contents of the first and second data areas 31 and 32 of the DPRAM 30 are rewritten alternately in a predetermined order by the contents 11 and 21, and the contents of the first and second data areas 31 and 32 are changed. The presence or absence of an abnormality is determined based on whether a predetermined relationship is established alternately.

Therefore, instead of using a detection circuit such as a watched timer for abnormality detection as in the prior art,
Can be detected and determined, and the circuit scale can be reduced accordingly.

(3) In this embodiment, the transmission data transfer processing mode is set during the execution of the abnormality monitoring processing operation at a constant cycle, and the first and second data areas 3 are set.
The contents of 1, 32 are rewritten to the contents for the transmission data transfer processing mode. When the transmission processing mode ends in the transmission data transfer processing mode, the contents of the first and second data areas 31 and 32 are set so that a predetermined relationship in the abnormality monitoring operation is established so that the abnormality monitoring processing operation can be performed. Was rewritten.

Accordingly, even when the transmission data transfer processing operation is performed at each time and the operation is completed, the operation can immediately proceed to the abnormality monitoring processing operation. (4) In the present embodiment, the first and second data areas 31 and 32 of the DPRAM 30 used in the startup synchronization establishment processing operation are also used in the abnormality monitoring processing operation and the transmission data transfer processing operation. . Therefore, DP
The use efficiency of the RAM 30 is good, which can contribute to saving of memory capacity.

The present invention is not limited to the above embodiment, but can be implemented in the following modes. (1) In the above embodiment, eight bits are allocated to the first to fourth data areas 31 to 34. That is, first to fourth
Although the contents to be written in the data areas 31 to 34 are 8 bits, the present invention is not limited to this. For example, 2 bits, 4 bits, or the like may be used as appropriate.

(2) In the above embodiment, in the abnormality monitoring processing operation, the first CPU 11 determines that the counterpart CPU is abnormal when the counter exceeds Y times and the second CPU 21 exceeds Z times. However, the number of times may be changed as appropriate according to the processing capacity of the first CPU 11 and the second CPU 21, for example.

[0086]

According to the first aspect of the present invention, the determination that initialization has been completed can be made only by the processing operations of both CPUs until the system of both CPUs is initialized. Can be shortened, and the circuit scale can be simplified.

According to the second aspect of the present invention, the abnormality of both CPUs can be determined only by the processing operations of both CPUs, so that the circuit scale can be simplified. According to the third aspect of the present invention, the determination that initialization has been completed and the determination of an abnormality in both CPUs can be performed only by the processing operations of both CPUs until the systems of both CPUs are both initialized.
The system startup time can be reduced, and the circuit scale can be further simplified.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram illustrating a dual CPU system.

FIG. 2 is a schematic diagram illustrating a configuration of a storage area of a DPRAM.

FIG. 3 is a flowchart of a startup synchronization establishment processing operation.

FIG. 4 is a flowchart of an abnormality monitoring processing operation.

FIG. 5 is a flowchart of a transmission data transfer processing operation.

FIG. 6 is a flowchart of a transmission data transfer processing operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 1st CPU 12 1st specific memory 21 2nd CPU 22 2nd specific memory 30 Dual port RAM (DPRAM) 31 1st data area as 1st storage area 32 2nd storage area Second data area

Claims (3)

[Claims] 1. A dual CPU system in which a dual port RAM accessible from both CPUs is provided between a first CPU and a second CPU, and data is transmitted and received between the two CPUs via the dual port RAM. The dual port RAM includes a first storage area for writing data to the first CPU and reading data to the second CPU, and writing data to the second CPU. A second storage area for reading data from the first CPU; the first CPU writes first initialization data to the first storage area when the power is turned on; Of the second CP written in the second storage area
After waiting until the second initialization data of U is read, first response data indicating that the second initialization data has been read is written to the first storage area, and the second CPU writes the first response data to the first storage area. After reading the first response data and waiting until reading the second response data written to the second storage area based on the reading of the first response data,
The second CPU determines that the initialization of both CPUs has been completed, writes the second initialization data to the second storage area when the power is turned on, and then initializes the system. After waiting until the first response data indicating that the initialization data of No. 2 has been read is read, the second response data is read.
And a method of establishing startup synchronization in a dual CPU system, wherein it is determined that the initialization of both CPUs has been completed after writing the second response data indicating that the first response data has been read into the storage area. 2. A dual CPU system in which a dual port RAM accessible from both CPUs is provided between a first CPU and a second CPU, and data is transmitted and received between the two CPUs via the dual port RAM. A first storage area for writing a plurality of types of predetermined monitoring data to the first CPU and reading the data to the second CPU; A second storage area for writing data of the plurality of types of monitoring data to the second CPU and reading data to the first CPU, wherein the first CPU The monitoring data written in the first storage area is compared with the monitoring data read from the second storage area, and both the monitoring data are determined in a predetermined relation. The monitoring data in the first storage area is rewritten in a predetermined order each time the monitoring data is stored, and the monitoring data in the first storage area is not rewritten when there is no predetermined relationship. CPU compares the monitoring data written in the second storage area with the monitoring data read from the first storage area, and each time both monitoring data have a predetermined relationship, the second storage The monitoring data in the area is rewritten in a predetermined order, and the monitoring data in the second storage area is not rewritten when there is no predetermined relationship. The first and second CPUs respectively When the relationship is not established, the number is counted, and when the relationship is established, the count value is cleared, and when the count value exceeds a predetermined value, at least one of the CPs is cleared. Is determined to be abnormal, and the initial writing of the monitoring data by the first and second CPUs is performed in one of the first CPU and the second CPU so that the monitoring data has a predetermined relationship. Holds,
On the other hand, the monitoring data is written so that the predetermined relationship is not established between the two monitoring data. In a dual CPU system, the monitoring data is rewritten so that a predetermined relationship is established between the monitoring data, and the first and second CPUs alternately establish a predetermined relationship between the two monitoring data. Abnormality monitoring method. 3. A dual CPU system in which a dual-port RAM accessible from both CPUs is provided between a first CPU and a second CPU, and data is transmitted and received between the two CPUs via the dual-port RAM. The dual port RAM includes a first storage area for writing data to the first CPU and reading data to the second CPU, and writing data to the second CPU. A second storage area for reading data from the first CPU; the first CPU writes first initialization data to the first storage area when the power is turned on; Of the second CP written in the second storage area
After waiting until the second initialization data of U is read, first response data indicating that the second initialization data has been read is written to the first storage area, and the second CPU writes the first response data to the first storage area. And waits until the second response data written in the second storage area is read based on the reading of the first response data.
The second CPU determines that the initialization of the PU has been completed, writes the second initialization data to the second storage area when the power is turned on, and then initializes the system. After waiting for reading first response data indicating that the first initialization data written to the storage area has been read, the second response indicating that the first response data has been read to the second storage area After writing the response data, it is determined that the initialization of both CPUs has been completed. After the initialization of both CPUs has been completed, the first CPU performs a plurality of types of predetermined monitoring for the first storage area. The data is written, the second CPU writes the plurality of types of monitoring data in the second storage area, and the first CPU writes the monitoring data written in the first storage area and the second storage area. Monitoring data read from the area The comparison is made, and the monitoring data in the first storage area is rewritten in a predetermined order each time the two monitoring data have a predetermined relationship, and the monitoring of the first storage area is performed when the two are not in the predetermined relation. The second CPU compares the monitoring data written in the second storage area with the monitoring data read from the first storage area, and determines that both monitoring data are predetermined. Rewriting the monitoring data of the second storage area in a predetermined order each time the relation is established, and not rewriting the monitoring data of the second storage area when the relation is not a predetermined relation, The first and second CPUs each count the number of times when a predetermined relationship is not established, clear the count value when the relationship is established, and when the count value exceeds a predetermined value. At this time, it is determined that at least one of the CPUs is abnormal, and the first writing of the monitoring data by the first and second CPUs is performed by either the first CPU or the second CPU. The relationship defined by the application data is established,
On the other hand, the monitoring data is written so that the predetermined relationship is not established between the two monitoring data. In a dual CPU system, the monitoring data is rewritten so that a predetermined relationship is established between the monitoring data, and the first and second CPUs alternately establish a predetermined relationship between the two monitoring data. Abnormality monitoring method.