JPH1090353A - Ic testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of executing times of skew adjustment by constantly maintaining the temperatures of circuit elements in an enclosure by housing a group of circuit units which operate in accordance with a timing signal in the same enclosure and constantly maintaining the internal temperature of the enclosure. SOLUTION: A circuit unit groqp composed of a timing generating section 102, a waveform generating section 103, a pattern data selector 105, a timing logic system comparing section l07A, and an applied-voltage control section 109 which operate in accordance with a timing signal is housed in a test head 200 together with a level comparator 202. Another circuit unit is housed in a main frame 100. In the test head 200, cold water is circulated from a heat exchanger provided on the outside of the head 200 by using a cooling means 204, such as the water-cooled radiator. At the same time, a wind is circulated in the head 200 by means of an air blasting means 206 through a means 206 so as to maintain the internal temperature of the head 200 at nearly the same level. Therefore, the number of executing times of skew adjustment can be reduced, because the fluctuation of the propagation delay time of each circuit element can be inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for testing whether a manufactured IC operates normally.

[0002]

2. Description of the Related Art FIG. 3 shows a schematic configuration of a conventional IC test apparatus. The IC test apparatus includes a housing called a main frame 100, a housing called a test head 200, and a test head 200 (not shown).
And a handler for automatically transporting and contacting the C400 sequentially. The test head 200 is connected to the main frame 100 by cables K _{1 to} K _{4 and} is separated from the main frame 100 so that the test head 200 can be attached to and detached from the handler.

[0003] The mainframe 100 operates under the control of the host computer 300 and mainly operates the test head 200.
An operation of supplying a test pattern signal to the IC under test 400 through the interface and an operation of determining whether the response output signal of the IC under test 400 is normal are performed. The mainframe 100 includes a tester processor 101 and a timing generator 102.
, A waveform generator 103, a pattern generator 104, a pattern data selector 105, a failure analysis memory 106
Logic comparison unit 107, voltage / current measurement unit 108,
A circuit unit group configured by the applied voltage control unit 109 and the like is stored.

The timing generator 102 compares, for example, the rising timing and the falling timing of the test pattern signal, and the timing at which the response output signal output from the IC under test 400 is compared to determine whether or not a logic value of a regular level is output. And outputs a timing signal defining the timing of logical comparison and the like. The waveform generator 103 generates a test pattern signal having an analog real waveform according to the pattern data (digital signal) selected and extracted by the pattern data selector 105 and the rising and falling timings output from the timing generator 102. I do.

The test pattern signal generated by the waveform generator 103 is sent to the test head 200 through the cable K ₁ and supplied to each terminal of the IC under test 400 through the drive circuit 201. That is, the timing generator 102,
Waveform generator 103 and pattern data selector 105
In this case, the number of the driving circuits 201 is smaller than the number n of the terminals of the IC 400 under test. Therefore, here, the signal path applied to one terminal is referred to as a pin series.

[0006] The output terminal P _in 1 of each pin series, P _in 2, P
The _in 3 ... P _in n input terminal of the level comparator 202 is connected. The level comparator 202 includes the mainframe 100
From the applied voltage control unit 109 provided in the
00 response output signal of the comparison voltage for comparison determination whether or not provided with a logic H level and L logic level of the normal is given through the cable K _4, the level comparison output if the comparison result is normal fed to the logic comparing section 107 through a cable K ₂ and K _3.

The logic comparator 107 compares the pattern with the expected value pattern given from the pattern data selector 105, and writes a signal representing a logic "1" failure into the failure analysis memory 106 each time a mismatch is detected, and uses the signal for failure analysis. .
The number of level comparators 202 and the number of logic comparison units 107 are also equal to the number of pin series. As described above, the IC test apparatus includes a test pattern signal generation system and a test pattern signal supply drive system for each pin series, generates a test pattern signal for each pin series, and A test pattern signal is supplied to each terminal. For this reason, the delay time _{Tpd of the} entire system including the test pattern signal generation system and the test pattern signal supply drive system needs to be identical for each pin series. That is, the phase of the test pattern signal applied to each terminal of the IC under test 400
The timing must be aligned with the timing specified in 2.

For this reason, conventionally, the IC test apparatus is provided with a skew adjusting means for each pin series, and the skew adjusting means can perform adjustment to make the propagation delay times T _pd of all the pin series coincide with each other. Have been.

[0009]

By the way, ICs are frequently used for each pin series. As is well known, a logic circuit element or an active amplification element constituting an IC has a characteristic that the delay time T _pd changes with a change in temperature. Of course,
Since the amount of change in the delay time with respect to the temperature change varies, it is not uniform. Therefore, even if the skew adjusting means adjusts the delay time T _pd for each pin series, if the temperature of the circuit element deviates from the temperature at the time of the skew adjustment, the delay time T _There is a disadvantage that _pd changes to a different value again.

FIG. 4 shows this state. Even if the skew adjustment is performed at the temperature A [° C.] and the delay time of each pin series is set to T _pd1 , the temperature-delay time characteristic of each pin series has a different slope like P1, P2, P3, and P4. Therefore, if the temperature deviates from A [° C.], the delay time of each pin series changes to a different value. Therefore, the skew must be adjusted each time the temperature of the circuit element changes, and when a large number of ICs need to be tested, the efficiency of the test (throughput) deteriorates.

The propagation delay time T _{pd with} respect to temperature change
Is small (difference in delay time between pin series), the variation cannot be ignored when testing an IC operating at high speed. SUMMARY OF THE INVENTION An object of the present invention is to provide an IC test apparatus which can stably maintain a delay time for each pin series even when the temperature of a circuit element changes, thereby eliminating the need for frequent skew adjustment.

[0012]

According to the present invention, a first circuit unit group mainly operating according to a timing signal and another second circuit unit group are stored in separate housings, and a first circuit unit operating according to the timing signal is stored. The configuration is such that the temperature inside the housing housing the unit group is maintained at a constant value to reduce the fluctuation of the propagation delay time for each pin series.

Therefore, according to the present invention, since the first circuit unit group that operates according to the timing signal is stored in the case having a constant temperature, the temperature of the circuit element can be maintained at a constant value. Therefore, the fluctuation of the propagation delay time with respect to the temperature is suppressed. As a result, the skew adjustment does not need to be performed frequently, so that there is an advantage that the throughput of the IC test can be improved.

[0014]

FIG. 1 shows an example of an IC test apparatus according to the present invention. In FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals. According to the present invention, the first circuit unit group operating according to the timing signal and the other second circuit unit group are stored in separate housings, and the cooling means is stored in the housing storing the first circuit unit group operating according to the timing signal. And a blowing means, so that the temperature inside the housing is maintained at a constant value.

In the example shown in FIG. 1, the first circuit unit group which operates according to the timing signal includes a timing generator 102, a waveform generator 103, a pattern data selector 105, and a logic comparator 107 which handle timing signals. The timing-based logic comparison unit 107A and the applied voltage control unit 109 of FIG. These circuit units 102, 103, 105, 107 A, and 109 are combined with a drive circuit 201 and a level comparator 202 by a test head 20.
0 and the other circuit units are stored in mainframe 1
00 is stored.

That is, the main frame 100 includes a test processor 101, a pattern generator 104, a failure analysis memory 106, and a non-timing logical comparator 10 which does not operate according to a timing signal in the logical comparator 107.
7B shows a case where the second circuit unit group including the voltage / current measuring unit 108 is stored. A timing generator 102 to be stored in the test head 200, a waveform generator 103, a pattern data selector 105,
Timing-based logic comparison section 107A and applied voltage control section 1
09 is mounted on the board 203 for each pin series. In the example shown in the figure, the circuit units 102, 103, 105, and
Although the case where 7A and 109 are mounted has been illustrated, a required circuit unit may be mounted on a single board 203 with a plurality of pin series.

Further, in the present invention, a cooling means 204 and a blowing means 205 are provided in the test head 200. As the cooling means 204, for example, a water-cooled radiator can be used. That is, as shown in FIG. 2, a water-cooled heat exchanger 206 is provided outside the test head 200, and a hose 206 is provided between the water-cooled heat exchanger 206 and the cooling means 205.
A and 206B are connected, and cold water is circulated to the cooling means 204 by hoses 206A and 206B.

At the same time, the air in the test head 200 is circulated by the blowing means 205 through the cooling means 204. FIG. 2 is a plan view of the test head 200 viewed from above. As shown in the figure, a large number of boards 203 are mounted on the test head 200 in an upright posture. A gap is formed between the boards 203, and the air blown by the blowing means 205 is circulated in the test head 200 through the cooling means 204.

The air blowing means 205 includes arrows W ₁ and W shown in FIG.
₂ , a wind is generated in the directions of W ₃ and W ₄ , and the wind is cooled by cooling means 2.
Then, it is fed into the opposing gap of the board 203 through the line 04. A case is shown in which two sets of blowing means 205 and cooling means 206 are provided, and wind is generated in one and the other to circulate the wind in the test head 200. In this way, by circulating the air in the test head 200 through the cooling means 206, the temperature in the test head 200 can be maintained at a substantially constant temperature.

Thus, the temperature of the circuit elements constituting each circuit unit can be maintained at a constant value.

[0021]

As described above, according to the present invention, the circuit unit 10 which operates according to the timing signal is provided.
2, 103, 105, 107A, and 109 are stored in the test head 200, and a cooling means 204 and a blowing means 205 are mounted inside the test head 200. Since the temperature is maintained at a constant value and the temperature distribution in the test head 200 is made uniform, the circuit units 102 mounted on any board 203
103, 105, 107A and 109 can also be placed in the same temperature environment.

As a result, it is possible to prevent the propagation delay time of each pin series from fluctuating, and it is possible to maintain the set state for a long time once the skew adjustment is performed. Therefore, a large number of ICs can be continuously tested without interruption by skew adjustment, and the advantage that the throughput of the IC test can be improved is obtained. Furthermore, by relocating the timing generator 102 to the test head 200 side, it is possible to shorten the distance between the timing generator 102 to the output terminal _{P in 1, P in 2 ...} P in n of the test head 200 . Thus, the length worth only a propagation delay time of each pin series least cable K ₁ ~K ₄ can be shortened. This also provides an advantage that the fluctuation width of the propagation delay time can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a plan view for explaining a structure of a main part of the present invention.

FIG. 3 is a block diagram for explaining a conventional technique.

FIG. 4 is a graph for explaining inconvenience of the conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Main frame 101 Tester processor 102 Timing generator 103 Waveform generator 104 Pattern generator 105 Pattern data selector 106 Failure analysis memory 107 Logic comparison unit 107A Timing-based logic comparison unit 107B Non-timing-based logic comparison unit 108 Voltage / current measurement unit 109 Applied voltage control unit 200 Test head 201 Drive circuit 202 Level comparator 203 Board 204 Cooling means 205 Blowing means 300 Host computer 400 IC under test

Claims (4)

[Claims] 1. A. First Embodiment A. a first circuit unit group that operates according to a timing signal, changes its own propagation delay time due to a temperature change, and the change in the propagation delay time affects an IC test; B. a second circuit unit group in which a change in its own propagation delay time does not affect an IC test; An IC test apparatus comprising two housings for separately storing the first circuit unit group and the second circuit unit group. 2. A. A. a first circuit unit group that operates according to a timing signal, changes its own propagation delay time due to a temperature change, and the change in the propagation delay time affects an IC test; B. a second circuit unit group in which a change in its own propagation delay time does not affect an IC test; D. a test head storing the first circuit unit group; And a main frame storing the second circuit unit group. 3. The IC test apparatus according to claim 1, wherein the first circuit unit group includes a timing generator, a waveform generator, and a test pattern signal generated by the waveform generator. A drive circuit to be provided to the IC under test, a level comparator for determining whether or not the response output signal of the IC under test has a regular level and taking in the signal; a timing logic comparator for handling a timing signal of the logic comparator; The second circuit unit group comprises a test processor, a pattern generation unit, a non-timing logic comparison unit that does not handle the timing signal of the logic comparison unit, a failure analysis memory, and a voltage / current measurement. IC characterized by comprising
Testing equipment. 4. The IC test apparatus according to claim 1, wherein the housing storing the first circuit unit group includes a cooling unit and a blowing unit, and the air in the housing is controlled by the blowing unit. By circulating through cooling means,
An IC test apparatus characterized in that the temperature inside the housing is maintained at a constant value and the temperature distribution inside the housing is made uniform.