JPH1090317A - Frequency detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency detection circuit which can precisely detect the frequency of an output signal of a PLL circuit or the like. SOLUTION: The output signal fout of a PLL circuit is converted into zerocross pulses ZP by a zerocross detection part 21, and given to counters 22, 23. On the basis of a time base signal TB1 of a timer 25, the count value CNT1 of the counter 22 is read at every period T1 by a synchronization judgement part 24. When continuous M-number of read values are all in a constant range, a synchronization detection signal SYN telling 'effective' is outputted from the synchronization judgement part 24. On the basis of a time base signal TB2 of a period T2 (=T1×M) of a timer 27, a frequency judgement part 26 reads the count value CNT2 of the counter 23. When the count value CNT2 is in a specified range, and the synchronization judgement signal SYN is 'effective', a detection signal OUT telling 'normal' is outputted from the frequency judgement part 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a frequency detection circuit that detects the frequency of an output signal from a (Phase Locked Loop, phase locked loop) circuit or the like and determines whether the output signal is a normal frequency output signal.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional frequency detection circuit. The frequency detection circuit 10 includes, for example, a zero-crossing detection unit 11 to which an output signal fout of the PLL circuit 1 is provided. The zero-crossing detector 11
It detects a so-called zero-crossing in which the polarity of the applied output signal fout changes from positive to negative and from negative to positive. A counter 12 for counting the number of zero crossings is connected to the output side of the zero crossing detector 11. The frequency determination unit 13 is connected to the counter 12. Frequency determining section 13 reads count value CNT of counter 12 according to time base signal TB having a constant cycle provided from timer 14, determines whether or not count value CNT is a value within a predetermined range, and determines the determination result. Is output. Further, the frequency determination unit 13
Has a function of resetting the counter 12 for the counting operation in the next cycle after reading the count value CNT of the counter 12. For example, it is assumed that when the PLL circuit 1 is synchronized with the input signal fin, the frequency of the output signal fout is 6000 Hz. The output signal fout is supplied to a zero-crossing detecting unit 11 of the frequency detecting circuit 10, and when the polarity changes from positive to negative and from negative to positive, the zero-crossing detecting unit 11 outputs a zero-crossing pulse ZP.
Is output. The zero-crossing pulse ZP is counted by the counter 12.

On the other hand, from a timer 14, for example, a period of 0.1
The time base signal TB of s is supplied to the frequency determination unit 13, and the count value CNT of the counter 12 is read by the frequency determination unit 13 based on the time base signal TB. If the frequency of the output signal fout has a constant value of 6000 Hz, the count value CNT of the counter 12 in the period of 0.1 s is 1200. When the count value CNT from the counter 12 is within a predetermined range (for example, 1
If it is within 200 ± 4), the frequency determination unit 13 determines that the output signal fout of the PLL circuit 1 is normal, and outputs a normal detection signal OUT. If the count value CNT does not fall within the predetermined range, the output signal fout of the PLL circuit 1 is determined to be abnormal, and the frequency determination unit 13 outputs a detection signal OUT indicating an abnormality. After the normal or abnormal detection signal OUT is output from the frequency determination unit 13, a reset signal RST is output to the counter 12, and the count value CNT of the counter 12 is reset to zero. In this manner, the output signal f of the PLL circuit 1 is set at a constant period of 0.1 s, for example.
Whether or not out is normal is detected.

[0004]

However, the conventional frequency detection circuit has the following problems. PLL
Even if the circuit 1 is not in the synchronized state and the output signal fout in the first half is 6100 Hz and the output signal fout in the second half is 5900 Hz in the period of 0.1 s,
The determination result in the frequency determination unit 13 becomes normal. Therefore, if the counting cycle is shortened in order to avoid such erroneous determination, an erroneous determination of determining a synchronous state occurs when the state is not the synchronous state. The present invention solves the problem of the prior art and provides a frequency detection circuit that can accurately detect the frequency of an output signal fout of a PLL circuit 1 or the like.

[0005]

According to a first aspect of the present invention, there is provided a frequency detecting circuit, comprising: an input signal which alternately changes in a positive direction and a negative direction with respect to a fixed threshold value; Is provided, a first counting means for counting the number of changes of the input signal with respect to the threshold at a constant first cycle, and the input signal is provided, and the number of changes of the input signal with respect to the threshold is determined. Second counting means for counting at a fixed second cycle longer than the first cycle, and whether or not all of the latest plurality of count values counted by the first counting means are all within a certain range. Determining means for determining whether the plurality of count values are all within a certain range;
Detecting means for detecting whether or not the count value of the counting means falls within a predetermined range, and outputting the detection result. According to a second aspect, an input signal of the frequency detection circuit according to the first aspect is a signal output from a PLL circuit, and the second cycle is M of the first cycle (where M
Are the plural times), and the latest plural count values are configured as the latest M count values.

A third invention provides a frequency detection circuit,
An input signal which alternately changes in a positive direction and a negative direction with respect to a certain threshold value is provided, and a counting means for counting the number of changes of the input signal with respect to the threshold value in a certain cycle; and a count counted by the counting means. N (where N is a plurality) holding means for holding the value and shifting the held count value sequentially to the subsequent stage at the constant period, and the N number of holding means. Adding means for calculating the sum of each count value at regular intervals, detecting means for detecting whether the sum calculated by the adding means is within a predetermined range, and outputting the detection result; It has. According to a fourth aspect of the present invention, in the frequency detection circuit, an input signal which alternately changes in a positive direction and a negative direction with respect to a certain threshold value is provided, and a count for counting the number of changes of the input signal with respect to the threshold value in a certain cycle Means for holding the count value counted by the counting means, and holding the shifted count value to the subsequent stage sequentially at the constant period and holding the count value, wherein N is a plurality of stages; A total value holding means for holding a total of each count value held by the N-stage holding means; a count value held by a first-stage holding means of the N-stage holding means; The value held in the holding means is added, and the count value held in the N-th holding means of the N-stage holding means is subtracted from the added value to obtain an updated total. Total value hold The total value updating means for outputting the stage, the total updated by the total value updating means and a detecting means for detecting whether or not within a predetermined range, and outputs the detection result.

According to a fifth aspect, in a frequency detection circuit,
An input signal which alternately changes in a positive direction and a negative direction with respect to a certain threshold value is provided, and a counting means for counting the number of changes of the input signal with respect to the threshold value in a certain cycle; and a count counted by the counting means. N (where N is a plurality) holding means for holding the value and shifting the held count value sequentially to the subsequent stage at the constant period, and the N number of holding means. Adding means for calculating the sum of the count values; determining means for determining whether all the count values held in the holding means of the N stages are within a certain range; Detecting means for detecting whether or not the sum of the count values calculated by the adding means is within a predetermined range, and outputting the detection result when it is determined that the count value is within the range; It is equipped with a. According to the first and second inventions, since the frequency detection circuit is configured as described above, the following operation is performed.

An input signal given from a PLL circuit or the like is
The first counting means counts each first cycle, and the determining means determines whether or not all of the latest count values are all within a certain range. The input signal is counted by the second counting means in a second cycle longer than the first cycle. If the determination means determines that all the count values are within a certain range, the detection means detects whether the count value of the second count means is within a predetermined range,
The detection result is output. According to the third aspect, the following operation is performed. The input signal is counted in a fixed cycle by the counting means, and the count value is given to N-stage holding means, and is sequentially shifted and held. N
The sum of the count values held in each stage of the stage holding unit is calculated by the addition unit, and the detection unit detects whether the total is within a predetermined range. According to the fourth aspect, the following operation is performed.

The input signal is counted at a fixed period by the counting means, and the count value is applied to holding means of N stages, and is sequentially shifted and held. The count value of the first stage of the N stages of holding means is added to the value of the total value holding unit, the count value of the last stage is subtracted, and the value of the total value holding unit is updated. And by the detecting means,
It is detected whether the updated sum falls within a predetermined range. According to the fifth aspect, the following operation is performed. The input signal is counted in a fixed cycle by the counting means, and the count value is given to N-stage holding means, and is sequentially shifted and held. The sum of the count values held in each stage of the N-stage holding unit is calculated by the adding unit, and the determining unit determines whether all the count values are within a certain range. When it is determined that all the values are within the predetermined range, the detection unit detects whether the sum of the addition units is within the predetermined range.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a configuration diagram of a frequency detection circuit according to a first embodiment of the present invention. The frequency detection circuit 20 includes, for example,
It has a zero-crossing detector 21 to which the output signal fout of the PLL circuit 1 is input. The zero-crossing detecting unit 21 detects a zero-crossing of the output signal fout provided, and has on its output side first and second counting means (for example, a counter) 22 for counting the number of zero-crossings. ,
23 are connected. A determination means (for example, a synchronization determination unit) 24 is connected to the counter 22, and the synchronization determination unit 24 receives a first cycle T from a first timer 25.
1 time base signal TB1 is provided. The synchronization determination unit 24 reads and stores the count value CNT1 of the counter 22 in accordance with the time base signal TB1, and when all the values of the continuous M (where M is plural) count values CNT1 read every period T1 are all A determination is made as to whether or not the signal is within a certain range, and if so, a synchronization determination signal S indicating "valid", otherwise indicating "invalid".
YN is output. In addition, the synchronization determination unit 24
It has a function of resetting the counter 22 for the counting operation of the next cycle T1.

On the other hand, detecting means (for example, a frequency determining unit) 26 is connected to the counter 23, and the frequency determining unit 26 has a synchronization determination signal SYN from the synchronization determining unit 24.
And a second period T2 from the second timer 27 (where T2
2 = T1 × M). When the synchronization determination signal SYN is "valid", the frequency determination unit 26 reads the count value CNT2 of the counter 23 according to the time base signal TB2, and determines whether or not the count value CNT2 is within a certain range. The detection signal OUT indicates "normal" if it is within a certain range, and "abnormal" if it is not within a certain range. If the synchronization determination signal SYN is “invalid”, the frequency determination unit 26
Outputs a detection signal OUT indicating "abnormal" regardless of the count value CNT. Further, the frequency determination unit 26 has a function of resetting the counter 23 for the counting operation in the next cycle T2.

Next, the operation will be described. For example, the output signal fou when the PLL circuit 1 is synchronized with the input signal fin
It is assumed that the frequency of t is 6000 Hz. In the zero-crossing detecting section 21 of the frequency detecting circuit 20, the output signal fou
When the polarity of t changes from positive to negative and from negative to positive, a zero-crossing pulse ZP is output. The zero-crossing pulse ZP is counted by the counters 22 and 23. For example, a time base signal TB1 having a period T1 = 0.01 s is provided from the timer 25 to the synchronization determination unit 24,
Based on the time base signal TB1, the synchronization determination unit 24
Thus, the count value CNT1 of the counter 22 is read. If the frequency of the output signal fout is 6000 Hz and has a constant value, the count value CNT1 of the counter 22 in the period T1 of 0.01 s is 120. In the synchronization determination unit 24, for example, the period T2 = 0.1 s
(= T1 × 10) It is determined whether or not all the count values CNT1 read ten times consecutively in the cycle T1 are within a certain range (for example, 120 ± 1). The synchronization detection signal SYN indicating “valid” is output to the frequency determination unit 26.

In the frequency determination section 26, a time base signal TB2 having a period T2 = 0.1 s is provided from a timer 27, and the count value CNT2 of the counter 23 is read based on the time base signal TB2. Output signal f
If the frequency of out is 6000 Hz and has a constant value, the count value CNT2 of the counter 23 during 0.1 s is 1200. The frequency determination unit 26 determines whether or not the count value CNT2 of the counter 23 is within a predetermined range (for example, 1200 ± 4). If the count value CNT2 is within the range, it is determined that the output signal fout of the PLL circuit 1 is normal. A “normal” detection signal OUT is output. If the count value CNT2 is not within the predetermined range, the output signal fout of the PLL circuit 1 is output.
Is determined to be abnormal, the frequency determination unit 26 outputs a detection signal OUT indicating “abnormal”. After the normal or abnormal detection signal OUT is output, a reset signal RST2 is output from the frequency determination unit 26 to the counter 23, and the counter 23 is reset to 0.

On the other hand, if at least one of the ten count values CNT1 read and stored by the synchronization determination unit 24 does not fall within a certain range, the output signal fo of the PLL circuit 1 is output.
ut is determined to be abnormal, and a synchronization detection signal SYN indicating "invalid" is output. Accordingly, the frequency determination unit 26 outputs the detection signal OUT indicating “abnormal” regardless of the count value CNT2 of the counter 23. As described above, the frequency detection circuit of the first embodiment has the synchronization determination unit 24 that reads the frequency of the output signal fout at a relatively short cycle T1 and determines whether the frequency is valid or invalid. In addition, there is no possibility of erroneously determining a synchronization state when synchronization is not performed. Further, when the synchronization state is determined, the frequency determination unit 26 reads the frequency of the output signal fout at a relatively long cycle T2 (= T1 × M), so that the frequency of the output signal fout is reliably detected. There is an advantage that can be.

Second Embodiment FIG. 3 is a block diagram of a frequency detection circuit showing a second embodiment of the present invention, and is common to elements in FIG. 1 showing the first embodiment and common elements. Are given. The difference between this frequency detection circuit 20A and the frequency detection circuit 20 of FIG. 1 is that a switch 28 is added. The switch 28 controls the output of the output signal fout of the PLL circuit 1 based on the synchronization determination signal SYN output from the synchronization determination unit 24. When the synchronization determination signal SYN is “valid”, the output signal fout is output. When the synchronization determination signal SYN is “invalid”, the output of the output signal fout is stopped. As described above, the frequency detection circuit 20A according to the second embodiment not only outputs the “normal” or “abnormal” detection signal OUT, but also
In the case of "abnormal", the output signal fou from the PLL circuit 1
Since the switch 28 for stopping t at the same time is provided,
In addition to the advantages of the first embodiment, a stable output signal fo
ut can be output.

Third Embodiment FIG. 4 is a block diagram of a frequency detection circuit showing a third embodiment of the present invention, and is common to the elements in FIG. 3 showing the second embodiment in common. Are given. This frequency detection circuit 20B is provided with a changeover switch 29 instead of the switch 28 in the frequency detection circuit 20A of FIG. The changeover switch 29 outputs either the input signal fin or the output signal fout of the PLL circuit 1 based on the synchronization determination signal SYN output from the synchronization determination unit 24. That is, when the synchronization determination signal SYN is “valid”, the output signal fout is output, and the synchronization determination signal S
When YN is "invalid", an input signal fin is output. Other configurations are the same as those in FIG. Thus, the frequency detection circuit 20 of the third embodiment
B outputs not only the detection signal OUT indicating “normal” or “abnormal” but also outputs the input signal fin on the input side in place of the unstable output signal fout from the PLL circuit 1 in the case of “abnormal”. Switch 29 for performing the operation. Accordingly, in addition to the advantage of the second embodiment, there is an advantage that a stable output frequency can be continuously supplied without stopping.

Fourth Embodiment FIG. 5 is a configuration diagram of a frequency detection circuit according to a fourth embodiment of the present invention. This frequency detection circuit 30 is, for example,
It has a zero-crossing detector 31 to which the output signal fout of the PLL circuit 1 is input. The zero-crossing detector 31 detects a zero-crossing of the applied output signal fout and outputs a zero-crossing pulse ZP.
A counting means (for example, a counter) 32 for counting the zero-crossing pulse ZP is connected. On the output side of the counter 32, N cascade-connected N stages (for example, N = 10)
Register 33 _1, 33 _2, ..., the holding means consists of 33 ₁₀ (e.g., a shift register) input side of the first-stage register 33 ₁ 33 are connected. Shift register 3
3 is a constant period T (for example, given by the timer 34)
T = 0.01 s) based on the time base signal TB
The input side of the signal of each register 33 _to 333 ₁₀ latches and outputs the latched signal to the output side.

Each of the registers 33 ₁ to 33 ₁ of the shift register 33
The output side of the 33 _10, summing means (e.g., an adder) is connected to the input side of 35. Adding unit 35 is composed of the adder 35 ₁ to 35 ₉ of N-1 stage is縱続connected, so the final sum TOT is outputted to the output side of the adder 35 ₉ of the last stage ing. The output side of the addition section 35 is connected to the input side of a detection means (for example, a frequency determination section) 36. The frequency determining unit 36 reads the total value TOT added by the adding unit 35 according to the time base signal TB given from the timer 34, and determines whether the total value TOT is a value in a certain range. A detection signal OUT as a result of the determination is output. Further, the frequency determination unit 36 has a function of resetting the counter 32 for the counting operation in the next cycle T. Next, the operation will be described.

For example, when the frequency of the output signal fout when the PLL circuit 1 is synchronized with the input signal fin is 6000H
z. The zero-crossing pulse ZP is output from the output signal fout by the zero-crossing detecting unit 31 of the frequency detecting circuit 30 when the polarity changes from positive to negative and when the polarity changes from negative to positive. The zero-crossing pulse ZP is counted by the counter 32. When a time base signal TB having a period T (= 0.01 s) is supplied from the timer 34 to the shift register 33 and the frequency determination unit 36, the count value CNT (= 120) of the counter 32 is changed according to the time base signal TB. is held in the register 33 _1, the register 33 _1, 33 _2, ..., 33 ₉ each count value CNT held in the latter stage of the register 3
3 _2, 33 _3, ..., are sequentially shifted to 33 _10. Then, the value of each register 33 _to 333 _10, which is shifted and summed by an adder 35, the sum value TOT (= 120
0) is provided to the frequency determination unit 36.

If the total value TOT of the adder 35 is within a predetermined range (for example, 1200 ± 4), the frequency determiner 36 outputs a detection signal OUT indicating a determination result indicating “normal”. . If the total value TOT does not fall within the predetermined range, a detection signal OUT indicating "abnormal" is output. After the normal or abnormal detection signal OUT is output from the frequency determination unit 36, a reset signal RST is output to the counter 32, and this counter 3
2 is reset to zero. As described above, in the fourth embodiment, the ten-stage shift register 33 shifts and holds the count value CNT every 0.01 s, and the adder 35 shifts the count value CNT held in each stage of the shift register 33. The values are added to output a total value TOT. Therefore, 0.01 s
The latest 10 counts, that is, the count value CN during 0.1 s
The frequency can be determined based on the total value TOT of T. As a result, accurate and responsive frequency detection can be performed.

Fifth Embodiment FIG. 6 is a block diagram of a frequency detection circuit according to a fifth embodiment of the present invention, and is common to the elements in FIG. 5 showing the fourth embodiment in common. Are given. This frequency detection circuit 30A is different from the frequency detection circuit 30 of FIG. 5 in that the addition section 35 is replaced with a total value updating section (for example, an operation section) 37 and a total value holding section (for example,
(Total register) 38 is provided. Other configurations are the same as those in FIG. Calculation unit 37, the sum register 3 the value of the first-stage register 33 ₁ of the output signal of the shift register 33
8 an adder 37 ₁ adds the value of the output signal, and is configured in this adder 37 ₁ of the addition result from subtracting the value of the output signal of the register 33 ₁₀ subtractor 37 _2. Then, the output side of the subtractor 37 _2, the input side of the sum register 38 is connected to the frequency determination unit 36. In the frequency detection circuit 30A having such a configuration, the value of the register 33 ₁₀ in the total register 38
_The updated total value TOT replaced with the value of ₁ is output. Other operations are the same as in the fourth embodiment. As described above, in the fifth embodiment, by providing one total register 38, the configuration of the operation unit 37 can be simplified.

Sixth Embodiment FIG. 7 is a block diagram of a frequency detection circuit showing a sixth embodiment of the present invention, and is common to the elements in FIG. 5 showing the fourth embodiment in common. Are given. This frequency detection circuit 30B adds a determination unit (for example, a synchronization determination unit) 39 to the frequency detection circuit 30 of FIG.
A frequency determining unit 36A having a function slightly different from that of the frequency determining unit 36 is provided instead of the frequency determining unit 36. Other configurations are the same as those in FIG. Synchronization determination unit 39, the output signals from the respective registers 33 _to 333 ₁₀ of the shift register 33 is given a constant of these output signals are all range (e.g. 120 ± 1)
If so, a synchronization detection signal SYN indicating "valid" is output to the frequency determination unit 36A. Also, if any of them does not fall within the certain range, the synchronization determination unit 39
The synchronization detection signal SYN indicating "invalid" is output to the frequency determination unit 36.
A function to output to A. On the other hand, the frequency determination unit 3
6A is a fixed period T (for example, T = 0.01) given from the timer 34 when the synchronization determination signal SYN is “valid”.
s), the total value TOT of the adder 35 is read in accordance with the time base signal TB, and it is determined whether or not the total value TOT is within a certain range.
T is output. If the synchronization determination signal SYN is “invalid”, the frequency determination unit 36A determines that the sum TO
The detection signal OUT indicating "abnormal" is output regardless of the value of T. Further, the frequency determining unit 36A has a function of resetting the counter 34 to 0 by the reset signal RST for the counting operation of the next cycle T after reading the total value TOT of the adding unit 35.

As described above, in the sixth embodiment, since the synchronization determination section 39 is provided, the possibility of erroneous detection can be further reduced in addition to the advantages of the fourth embodiment.
Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (e). (A) The counters 22 and 25 count the zero-crossing signal ZP from the zero-crossing detecting unit 21, but the present invention is not limited to such a method.
The number of times that the output signal fout from the L circuit 1 or the like exceeds a certain threshold may be counted. (B) The periods of the time base signals TB1 and TB2 of the timers 24 and 27 in FIG. 1 have a relationship of 1: M. However, the present invention is not limited to such conditions, and any period may be set. Can be. (C) The synchronization determination units 24 and 39 determine “valid” or “invalid” using the ten count values CNT, but the number is not limited to ten and any number of count values C
It can be determined based on NT. (D) The shift register 33 has a ten-stage configuration, but is not limited to ten stages, and can be configured with any N stages. (E) In the synchronization determination unit 39, the individual count values CNT
Are in a certain range or not.
For example, the validity of the count value CNT may be determined based on whether or not the difference between the maximum value and the minimum value is within a certain range.

[0024]

As described above in detail, according to the first and second aspects, the input signal is counted in the first cycle, and it is determined whether or not the count value is within a certain range. And a detecting means for detecting whether or not the count value counted in the second cycle is within a predetermined range when the value falls within a certain range. Thereby, for example, the frequency of the input signal from the PLL circuit or the like can be reliably detected. According to the third aspect, the holding means for sequentially shifting and holding the count value of the fixed period, the adding means for summing the count values of the respective stages of the holding means, and whether the sum value is within a predetermined range Detection means for detecting whether or not there is no data. As a result, a quick response to a change in the input signal is enabled, and the frequency can be detected reliably. According to the fourth aspect of the present invention, since there is provided the total value holding means for holding the total of the count values and the total value updating means for updating the value held by the total value holding means, the same as the third invention is provided. This has an effect and can simplify the circuit configuration. According to the fifth aspect, the determination means for determining whether or not all the count values of the holding means are all within a certain range is added to the third aspect, so that the frequency can be detected more reliably. can do.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frequency detection circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an example of a conventional frequency detection circuit.

FIG. 3 is a configuration diagram of a frequency detection circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a frequency detection circuit according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a frequency detection circuit according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a frequency detection circuit according to a fifth embodiment of the present invention.

FIG. 7 is a configuration diagram of a frequency detection circuit according to a sixth embodiment of the present invention.

[Explanation of symbols]

20, 20A, 20B, 30, 30A, 30B Frequency detection circuit 22, 23, 32 Counter 24, 29 Synchronization determination unit 25, 27, 34 Timer 26, 36, 36A Frequency determination unit 28 Switch 29 Switching switch 33 Shift register 35 Addition Unit 37 Operation unit 38 Total register

Claims (5)

[Claims] An input signal that alternates in a positive direction and a negative direction with respect to a certain threshold value is provided, and a first count of the number of changes of the input signal with respect to the threshold value is performed in a certain first cycle. Counting means, provided with the input signal, a second counting means for counting the number of changes of the input signal with respect to the threshold value in a fixed second cycle longer than the first cycle, Determining means for determining whether or not the latest plurality of count values counted by the counting means are all within a certain range; and if it is determined that all of the plurality of count values are within a certain range, Detecting means for detecting whether or not the count value of the second counting means is within a predetermined range, and outputting a result of the detection. 2. The method according to claim 1, wherein the input signal is a signal output from a PLL circuit, and the second cycle has a length M (where M is a plurality) times the first cycle. 2. The frequency detection circuit according to claim 1, wherein the plurality of count values are the latest M count values. 3. An input signal which alternately changes in a positive direction and a negative direction with respect to a certain threshold value is provided, and counting means for counting the number of changes of the input signal with respect to the threshold value in a certain cycle; And N (where N is a plurality) stages of holding means for holding the count value counted in the step (b) and sequentially shifting and holding the held count value to the subsequent stage at the constant period; Adding means for calculating the sum of the respective count values held in each of the predetermined cycles; and detecting whether or not the sum calculated by the adding means falls within a predetermined range, and detecting the detection result. A frequency detection circuit, comprising: a detection unit that outputs a signal. 4. An input signal which alternately changes in a positive direction and a negative direction with respect to a certain threshold value is provided, and counting means for counting the number of changes of the input signal with respect to the threshold value in a certain cycle; And N (where N is a plurality) stages of holding means for holding the count value counted in the step (b) and sequentially shifting and holding the held count value to the subsequent stage at the constant period; A total value holding means for holding the sum of the count values held in the step S, a count value held in the first-stage holding means of the N-stage holding means, and a count value held in the total value holding means. Value, and subtracts the count value held in the N-th holding means of the N-stage holding means from the added value, and outputs an updated total to the total value holding means. Total value update Means for detecting whether or not the sum updated by the sum value updating means falls within a predetermined range, and outputting a result of the detection. 5. A counting means for receiving an input signal which alternately changes in a positive direction and a negative direction with respect to a certain threshold value, and counting the number of changes of the input signal with respect to the threshold value in a certain cycle; And N (where N is a plurality) stages of holding means for holding the count value counted in the step (b) and sequentially shifting and holding the held count value to the subsequent stage at the constant period; Adding means for calculating the sum of the count values held in the storage means; determining means for determining whether all the count values held in the N-stage holding means are all within a certain range; When it is determined that all the count values are within a certain range, it is detected whether or not the sum of the count values calculated by the adding means is within a predetermined range, and the detection result is obtained. Frequency detection circuit, characterized in that the force detecting means comprises a.