JPH1084288A - Code converter, and variable length code decoder and decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the variable length coding/decoding device in which restoration in the decoding processing is conducted more in details than that of a conventional device, the reliability of code data after the restoration is enhanced and which is also applicable to real time decoding processing. SOLUTION: When a bit stream BIN being a conversion object is not corresponding to any variable length code in a prescribed code system, a variable length code converter 45 provides an output of an incorrect code detection signal NG. In this case, a controller 48 provides an output of an error signal ER, and a selector 47 gives '1' to a memory 41 as a read signal RO according to the error signal ER. On the other hand, an accumulator 46 resets an accumulated value of sets of code length DL, that is, a shift amount SV to '0'. Thus, a bit stream read from the memory 41 is continuously outputted in the unit of 8-bit from a shifter 44. When the controller 48 detects a header denoting a delimiter of data from an output bit stream from the shifter 44, the controller 48 releases the error signal ER. As a result, the decoding of the bit streams stored in the memory 41 is restarted just after the detected header.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code converter for converting a code into code data based on a predetermined coding system, a variable length code decoding device for decoding a bit string composed of continuous variable length codes into code data, and a decoding device. About the method.

[0002]

2. Description of the Related Art In recent years, with the digitization of recording media and communication paths, compression of an information amount using entropy coding has become indispensable. In the entropy coding, the average code length is shortened by assigning a short code to a symbol having a high probability of appearance.
In particular, in the field of image processing, the MPEG standard, which is an international standard for compression and decompression, specifies the use of variable length codes based on a predetermined coding system.

[0003]

For example, in the case of performing a decoding process according to MPEG in a DVD device, a variable length code conversion that can perform variable length code conversion based on one of a plurality of code systems externally specified is performed. A long code converter is required. However, in order to realize such a variable-length code converter, a plurality of circuits corresponding to each coding system are provided, and a configuration for selectively operating a circuit corresponding to the specified coding system is provided. Therefore, there is a problem that the circuit scale of the entire device becomes large.

[0004] When decoding a variable-length code, usually, code data corresponding to the variable-length code is obtained, and the code length of the variable-length code is also obtained as information for decoding. The process of obtaining the first bit position of the variable length code to be decoded is repeated. For this reason,
When an error occurs in the bit of the variable length code, not only the code data corresponding to the error cannot be obtained, but also the code length of the variable length code cannot be obtained. The first bit position will not be known. As a result, the subsequent variable-length code cannot be decoded because the bit separation position is not known at all.
Alternatively, even if decoded, the code data becomes completely random.

That is, in the case of variable-length code decoding, if an error such as "0" / "1" inversion occurs in a bit string for some reason, subsequent decoding becomes impossible or random decoding. Will be performed.

In order to cope with this problem, conventionally, for example, a malfunction in decoding processing due to an error in a bit string is detected by a temporal interruption. However, in this case, since the decoding process does not return to normal until a temporal interruption is performed, the decoding process cannot be recovered in a detailed manner.

In order to cope with the above problem, a conventional variable-length code decoding system employs a bit-length-sequence method in which a cut-out bit sequence does not correspond to a previously stored bit pattern (variable-length code) and the code length cannot be detected. There is a method in which the bit shift information for controlling the cut-out position is increased / decreased to search for a bit string cut-out position at which no bit pattern detection becomes impossible, and decoding is continued from this position (Japanese Patent Laid-Open No.
-350458).

However, in the above-described conventional example, the searched bit string cutout position is not always appropriate, and there is a possibility that the bit pattern cannot be detected immediately after the restoration, and the reliability of the code data after the restoration of the decoding process may occur. Was low. Further, in order to recover the decoding process, a new bit string cutout position is searched by a so-called trial and error method, so that there is a possibility that time is not enough for real-time decoding processing.

In view of the above problems, it is an object of the present invention to provide a code converter for performing code conversion based on a plurality of code systems, and to reduce the circuit scale as compared with the related art.

Further, the present invention can recover the decoding process more finely than before in the variable-length code decoding, improves the reliability of the coded data after the recovery, and realizes the real-time decoding process. It is intended to be applicable.

[0011]

Means for Solving the Problems In order to solve the above-mentioned problem, a solution taken by the invention of claim 1 is to provide a method for converting an encoded bit string to be converted into a designated one of a plurality of code systems. As a code converter for converting into code data based on one coding system, the correspondence between codes and code data included in a common part in one coding system and another coding system is stored, and the conversion target A common conversion means for converting the bit string into code data based on the stored correspondence is provided, wherein the code conversion based on the one code system and the code conversion based on the other code system are both performed. This is performed using common conversion means.

According to the first aspect of the present invention, when performing code conversion based on one code system, code conversion is performed by a common conversion unit on a portion of the one code system that is common to another code system. On the other hand, when performing a code based on the other code system, code conversion is performed by the common conversion unit on a portion of the other code system that is common to the one code system. It is possible to reduce the number of circuits corresponding to parts common to the system and another coding system. Therefore, the circuit scale can be made smaller than before.

[0013] In the invention of claim 2, the common conversion means in the code converter of claim 1 outputs the non-conversion code when the bit string to be converted does not correspond to any of the stored codes. The code converter outputs a detection signal, and the code converter performs the code conversion based on the one coding system or another coding system, and when the non-detection signal is not output from the common conversion unit, the common conversion unit. And a selection unit for selectively outputting the code data converted by the code converter as output data of the code converter.

According to the third aspect of the present invention, the second aspect is provided.
In the code converter, the correspondence between codes other than those stored in the common conversion means and the code data in the one coding system is stored, and the bit string to be converted is stored. Dedicated conversion means for outputting a non-detection signal when the bit string to be converted does not correspond to any code belonging to the stored correspondence while converting and outputting the code data based on the relationship; When performing a code conversion based on the system, when a non-detection signal is output from both the common conversion unit and the dedicated conversion unit, an invalid code detection signal indicating that there is an error in the bit string to be converted is output. It is assumed that an illegal code detecting means is provided.

[0015] In the invention of claim 4, according to claim 1 of the present invention.
The common conversion means in the code converter of the above, when the bit string to be converted does not correspond to any code belonging to the stored correspondence, shall output a non-detection signal,
The code converter stores a correspondence relationship between codes and code data other than those stored in the common conversion means in the one code system, and stores the bit string to be converted. A first dedicated conversion unit that outputs a non-detection signal when the bit string to be converted does not correspond to any code belonging to the stored correspondence while converting and outputting the code data based on the relationship; It stores the correspondence between codes and code data other than those stored in the common conversion means among other code systems, and converts the bit string to be converted into code data based on the stored correspondence. A second dedicated conversion unit that outputs a non-detection signal when the conversion target and the conversion target bit string do not correspond to any of the codes belonging to the stored correspondence relationship;
When performing code conversion based on the one coding system, the code data converted by the common conversion unit and the first dedicated conversion unit that did not output a non-detection signal is output by the code converter. While selectively outputting as data,
When performing code conversion based on the other code system, the code data converted by one of the common conversion means and the second dedicated conversion means that did not output a non-detection signal is selectively output as the output data. When performing the code conversion based on the one code system, when the non-detection signal is output from both the common conversion means and the first dedicated conversion means, an error occurs in the bit string to be converted. While performing the code conversion based on the other code system while outputting the unauthorized code detection signal indicating that there is a non-detection signal from both the common conversion means and the second dedicated conversion means At this time, it is assumed that the apparatus comprises an unauthorized code detection means for outputting the unauthorized code detection signal.

According to a fifth aspect of the present invention, there is provided a variable length code decoding apparatus for decoding a bit string composed of a continuous variable length code into code data, wherein a bit string to be converted cut out from the bit string is input. It is determined whether or not this bit string to be converted corresponds to any of the variable length codes belonging to a predetermined coding system, and if so, the bit string to be converted is coded based on the predetermined coding system. While converting and outputting data, if none of the above applies, a variable-length code converter that outputs an invalid code detection signal indicating that the bit string to be converted has an error, and an invalid code from the variable-length code converter. When a detection signal is output, header search means is provided for searching backward from the bit string to be converted a header indicating a data delimiter in the bit string. , The variable-length code decoding device,
When an invalid code detection signal is output from the variable length code converter, decoding of the bit string is interrupted, and decoding of the bit string is restarted immediately after the header detected by the header search means.

According to the fifth aspect of the present invention, when the bit string to be converted does not correspond to any of the variable length codes belonging to a predetermined coding system, an invalid code detection signal is output from the variable length code converter. That is, if there is an error in the input bit string, it is immediately detected. At this time, the decoding process is interrupted, and the header indicating the data delimiter is searched backward from the bit string to be converted by the header search means. Since the position immediately after the detected header is always appropriate as the extraction position of the bit string to be converted, immediately after decoding is resumed, the bit string to be converted again corresponds to any of the variable length codes belonging to the predetermined coding system. There is no possibility that a detection error of not performing will occur. Further, since a trial and error method as in the related art is not used to detect a new bit string cutout position, decoding can be restarted instantaneously. Therefore, the restoration of the decoding process can be performed more finely than before, and the reliability of the coded data after the restoration is high, and the decoding process can be applied to the real-time decoding process.

According to a sixth aspect of the present invention, in the variable length code decoding apparatus according to the fifth aspect, the variable length code converter comprises:
Based on a single coding system, to convert the bit string to be converted into code data, when the bit string to be converted does not correspond to any of the variable length code belonging to the single coding system, An illegal code detection signal is output.

According to the seventh aspect of the present invention, the fifth aspect of the present invention is provided.
The variable-length code converter in the variable-length code decoding device of the present invention converts a bit string to be converted into code data based on a designated one of a plurality of code systems. It stores the correspondence between the variable-length code and the code data, which is included in a part common to other code systems, and converts the bit string to be converted into code data based on the stored correspondence. ,
When the bit string to be converted does not correspond to any of the variable-length codes belonging to the stored correspondence, a common conversion unit that outputs a non-detection signal, and the common conversion unit of the one code system stores the common conversion unit. And stores the correspondence between the variable-length code and the code data other than the converted one. Based on the stored correspondence, the bit string to be converted is converted into code data. ,
A dedicated conversion unit that outputs a non-detection signal when the variable length code does not correspond to any of the stored variable length codes, and a shared conversion unit that performs variable length code conversion based on the one code system. Selecting means for selecting and outputting, as output data of the variable-length code converter, code data converted and output from the non-detection signal not output of the dedicated conversion means, and a variable length based on the one code system. In the case of performing code conversion, it is assumed that the code conversion device includes an unauthorized code detection unit that outputs the unauthorized code detection signal when a non-detection signal is output from both the common conversion unit and the dedicated conversion unit.

According to another aspect of the present invention, there is provided a variable-length code decoding method for decoding a bit string composed of continuous variable-length codes into code data, wherein a bit string to be converted cut out from the bit string is An illegal code detecting step of determining whether or not the variable length code belongs to any of the variable length codes belonging to the predetermined code system; and in the illegal code detecting step, the bit string to be converted is one of the variable length codes belonging to the predetermined code system. A header search step of interrupting decoding of the bit string, and searching backward from the bit string to be converted, a header indicating a data delimiter, in the bit string, Immediately after the header, the decoding of the bit string is restarted.

According to the invention of claim 8, in the illegal code detecting step, it is determined whether or not the bit string to be converted corresponds to any of the variable length codes belonging to a predetermined code system. Is immediately detected if there is an error. Further, at this time, in the header search step, decoding is interrupted, and a header indicating a data delimiter is searched backward from the bit string to be converted. Since the position immediately after the detected header is always appropriate as the extraction position of the bit string to be converted, immediately after decoding is resumed, the bit string to be converted again corresponds to any of the variable length codes belonging to the predetermined coding system. There is no possibility that a detection error of not performing will occur. Further, since a trial and error method as in the related art is not used to detect a new bit string cutout position, decoding can be restarted instantaneously. Therefore,
Recovery of the decoding process can be performed more finely than before, and the reliability of the coded data after the recovery is high, and the decoding process can be applied to a real-time decoding process.

[0022]

FIG. 1 is a block diagram showing the configuration of a variable length code converter as a code converter according to an embodiment of the present invention. The variable-length code converter according to the present embodiment shown in FIG. 1 realizes variable-length code conversion based on two types of code systems T1 and T2.

In this embodiment, two types of coding systems T1,
The correspondence between the variable length code included in T2 and the code data is classified into the following three groups. (Group 1) Code system T2 included in code system T1
(Group 2) Included in both coding systems T1 and T2 (Group 3) Not included in coding system T1 but included in coding system T2 Each is provided with a conversion means.

In FIG. 1, reference numeral 11 denotes first conversion means as first dedicated conversion means corresponding to group 1, 12 denotes second conversion means as shared conversion means corresponding to group 2, and 13 denotes group 3 Is a third conversion means as a second dedicated conversion means, and the first to third conversion means 11, 12, and 13 respectively determine the correspondence between the stored variable-length code and the code data. Based on this, the bit string BIN to be converted is converted into code data DT1, DT2, DT3. When the conversion target bit string BIN does not correspond to any of the stored variable-length codes and the variable-length codes belonging to the correspondence between the code data and the first to third conversion units 11, 12, and 13, respectively. Non-detection signals NS1, NS2,
NS3 is output.

Reference numeral 20 denotes a selection signal T1 for instructing selection of the coding system T1 and a selection signal T for instructing selection of the coding system T2.
2 is a selection means for selectively outputting one of the output code data DT1, DT2, DT3 of the first to third conversion means 11, 12, 13 as output data DOUT of the variable length code converter. When the control input is "1", the selection means 20 outputs the input signal as it is, while when the control input is "0", the output terminals become high impedance when the first to third tri-state buffers 21, 22, 23,
AND gates 24, 25, 26 for controlling tri-state buffers 21, 22, 23, and selection signals T1, T
It comprises an OR gate 27 that generates a logical sum signal of two. The first tri-state buffer 21
First conversion means 1 generated by ND gate 24
The AND signal of the inverted signal of the non-detection signal NS1 and the selection signal T1 is used as a control input, and the second tri-state buffer 22 outputs the second tri-state buffer 22 generated by the AND gate 25.
The AND signal of the inverted signal of the non-detection signal NS2 of the conversion means 12 and the OR signal of the selection signals T1 and T2 generated by the OR gate 27 is used as a control input, and the third tristate buffer 23 The logical product signal of the inverted signal of the non-detection signal NS3 of the third conversion means 13 and the selection signal T2 generated by the second conversion means 13 is used as a control input.

Numeral 30 denotes an incorrect code detection signal NG indicating that there is an error in the bit string input to the variable length code converter.
Is an illegal code detection unit that outputs The illegal code detection means 30 receives the non-detection signals NS1 and NS2 of the first and second conversion means 11 and 12 and the selection signal T1 as inputs.
A which receives the non-detection signals NS2 and NS3 of the gate 31, the second and third conversion means 12 and 13, and the selection signal T2 as inputs.
An ND gate 32 and an OR gate 33 that outputs a logical sum signal of the output signals of the AND gates 31 and 32 to an output line of the illegal code detection signal NG.

Table 1 is a table showing two types of coding systems T1 and T2 according to the present embodiment. Table 2 is a truth table in binary notation in which the variable length codes are input and the code data is output for the code systems T1 and T2 shown in Table 1 classified into the above three groups.

[0028]

[Table 1]

[0029]

[Table 2]

In the variable length code converter according to the present embodiment shown in FIG. 1, the first conversion means 11 operates according to the truth table of group 1 shown in Table 2, and the second conversion means 12 operates in accordance with the truth table of group 2. The third conversion means 13 operates according to the truth table of group 3, and operates according to the truth table. That is, each of the conversion means 11, 12, and 13 stores the correspondence between the variable-length code and the code data as shown in Table 2, and based on the stored correspondence, a 4-bit conversion target bit string BIN. Are converted to 3-bit code data DT1, DT2,
Convert and output to DT3.

The first to third conversion means 11, 12, 1
3 outputs “1” to the output lines of the non-detection signals NS1, NS2, and NS3 when there is no code data corresponding to the bit string BIN to be converted, and outputs the bit string BI to be converted.
When there is code data corresponding to N, the non-detection signal NS
"0" is output to the output lines of 1, NS2 and NS3. That is, each of the first to third conversion units 11, 12, and 13 converts the bit string B to be converted to any of the stored variable-length codes and the variable-length codes belonging to the correspondence relationship between the code data and the code data.
When IN does not apply, the non-detection signals NS1, NS2, N
"1" is output as S3.

In this embodiment, the first to third conversion means 1
Based on the truth table shown in Table 2, 1, 12, and 13 are configured using the product-sum standard form. That is, each variable length code is detected using an AND gate (product), and code data corresponding to each variable length code is generated from an output signal of the AND gate using an OR gate (sum).

FIG. 2 is a circuit diagram showing the structure of the first conversion means 11. In FIG. 2, reference numeral 11a denotes a code detection unit which receives a bit string BIN to be converted, detects each variable length code, and outputs a detection result. A code data generator 11b generates and outputs code data corresponding to the detected variable-length code based on the detection result of the code detector 11a, and outputs a non-detection signal when no variable-length code is detected. NS1 is generated and output. Code detector 11a
Are complementary buffers 111 to 11 which receive each bit of the bit string BIN to be converted as an input and output normal and inverted signals.
4 and AND gates 115 and 116, and the code data generator 11b includes a NOR gate 117.

In the code detection section 11a, the complementary buffers 111 to 114 generate the normal and inverted signals of each bit (bit 3 to bit 0) of the bit string BIN to be converted. The AND gates 115 and 116 respectively correspond to the variable length codes to be detected, and the complementary buffers 111 to 114 determine whether or not the corresponding variable length code matches the bit string BIN to be converted. Detect based on signal. The AND gate 115 corresponds to the variable length code “101x” of Group 1 shown in Table 2.
The non-inverted output signal of the complementary buffer 111 (the non-inverted signal of bit 3 of the bit string BIN to be converted) and the complementary buffer 112
Output signal (bit 2 of the bit string BIN to be converted)
) And the non-inverted output signal of the complementary buffer 113 (the non-inverted signal of the bit 1 of the bit string BIN to be converted) are input. Only when all the input signals are “1”, that is, when the bit string BIN to be converted is “101x” "1" is output only when "1". On the other hand, the AND gate 116 corresponds to the variable length code “1111” of group 1 shown in Table 2, and outputs the normal output signal of the complementary buffer 111, the normal output signal of the complementary buffer 112, and the normal output signal of the complementary buffer 113. The signal and the non-inverted output signal of the complementary buffer 114 are input, and "1" is output only when all the input signals are "1", that is, only when the bit string BIN to be converted is "1111".

The code data generation section 11b includes a code detection section 1
1a is generated and output as 3-bit code data DT1 in which the output signal of the AND gate 115 is the lower 2 bits and the output signal of the AND gate 116 is the upper 1 bit. Thus, when the output signal of the AND gate 115 is “1” and the output signal of the AND gate 116 is “0” (that is, when the bit string BIN to be converted is “101x”), “01” is used as the code data DT1.
When the output signal of the AND gate 115 is "0" and the output signal of the AND gate 116 is "1" (that is, when the bit string BIN to be converted is "1111"), the code data is output. "10" as DT1
When the output signals of the AND gates 115 and 116 are both "0" (that is, when the conversion target bit string BIN is neither "101x" nor 1111 ")," 000 "is output as code data. While
"1" is output from the NOR gate 117 as the non-detection signal NS1.
Is output.

The second and third conversion means 12, 13 are also shown in FIG.
Has the same configuration as the first conversion means 11 shown in FIG.

FIG. 3 is a circuit diagram showing the structure of the second conversion means 12. In FIG. 3, reference numeral 12a denotes a code detection unit;
b is a code data generation unit, and the code detection unit 12a is composed of complementary buffers 121 to 124 and AND gates 125 and 12
6, and the sign data generation unit 12b includes a NOR gate 12
7 is provided.

As can be seen from Table 2, since the code length of the variable-length code belonging to group 2 is 2 bits, the second conversion means 12 can change only the upper 2 bits of the 4-bit conversion target bit string BIN. Used for code conversion. In the sign detection unit 12a, the AND gate 125 is connected to the complementary buffer 1
21 and the inverted output signal of the complementary buffer 122 are input, and only when all the input signals are "1", that is, the bit string BIN to be converted is group 2 shown in Table 2.
"1" is output only when the variable length code is "00xx". On the other hand, the AND gate 126 receives the inverted output signal of the complementary buffer 121 and the non-inverted output signal of the complementary buffer 122 as inputs, and only when the input signals are all “1”, that is, when the bit string BIN to be converted corresponds to the group 2 "1" is output only when the variable length code is "01xx".

The code data generation unit 12b includes the code detection unit 1
2a, the output signal of the AND gate 125 is the least significant bit, the output signal of the AND gate 126 is the second least significant bit, and 3-bit code data DT2 having "1" as the most significant bit is generated and output. I do. Thus, when the output signal of the AND gate 125 is “1” and the output signal of the AND gate 126 is “0” (that is, when the bit string BIN to be converted is “00xx”), “001” is used as the code data DT2. Is output while the output signal of the AND gate 125 is "0" and the output signal of the AND gate 126 is "1" (that is, when the bit string BIN to be converted is "01xx").
Outputs "010" as code data DT2. When the output signals of the AND gates 125 and 126 are both “0” (that is, when the conversion target bit string BIN is neither “00xx” nor “01xx”), “000” is output as the code data DT2, NOR
“1” is output from the gate 127 as the non-detection signal NS1.

FIG. 4 is a circuit diagram showing the configuration of the third conversion means 13. In FIG. 4, reference numeral 13a denotes a code detection unit;
b denotes a code data generation unit, and the code detection unit 13a includes complementary buffers 131 to 134 and AND gates 135, 13
6 and the code data generation unit 13b includes a NOR gate 13
7 is provided. In the sign detection unit 13a, the AND gate 135 outputs the non-inverted output signal of the complementary buffer 131, the inverted output signal of the complementary buffer 132, and the complementary buffer 133.
And "1" only when the input signals are all "1", that is, only when the bit string BIN to be converted is the variable length code "100x" of group 3 shown in Table 2.
Is output. On the other hand, the AND gate 136 receives the non-inverted output signal of the complementary buffer 131, the non-inverted output signal of the complementary buffer 132, the non-inverted output signal of the complementary buffer 133, and the inverted output signal of the complementary buffer 134, and all the input signals are "1". "1" is output only when the bit string BIN to be converted is the variable length code "111x" of group 3 shown in Table 2.

The code data generation unit 13b includes the code detection unit 1
It outputs 3-bit code data DT3 with the output signal of the AND gate 135 of 3a being the lower 2 bits and the output signal of the AND gate 136 being the most significant bit. Thus, when the output signal of the AND gate 135 is “1” and the output signal of the AND gate 136 is “0” (that is, when the bit string BIN to be converted is “100x”), “011” is used as the code data DT3. Is output, and when the output signal of the AND gate 135 is "0" and the output signal of the AND gate 136 is "1" (that is, when the bit string BIN to be converted is "1110"), the code data DT3 is output. “100” is output. When the output signals of AND gates 135 and 136 are both “0” (that is, when bit string BIN to be converted is neither “100x” nor “1110”), “000” is output as sign data DT3, and NOR is output.
“1” is output from the gate 137 as the non-detection signal NS3.

The operation of the variable length code converter according to this embodiment shown in FIG. 1 will be described.

When the coding system T1 is selected by the selection signal T1, the first and second conversion means 11 and 12 are selected, while when the coding system T2 is selected by the selection signal T2, the second and second conversion means are selected. 3 conversion means 12 and 13 are selected. Then, of the two selected conversion means, the code data output from the conversion means to which the non-detection signal is not output is converted to the output data D of the variable length code converter.
OUT.

For example, when the selection signal T1 is "1" and the selection signal T2 is "0", that is, when the coding system T1 is selected, the output signal of the AND gate 26 is such that the selection signal T2 which is one input is Since it is "0", it becomes "0", so that the output of the third tristate buffer 23 enters a high impedance state, and the third conversion means 13
Will not be output as output data DOUT.

On the other hand, the output signal of the AND gate 24 has the same value as the inverted signal of the non-detection signal NS1 of the first conversion means 11 which is the other input because the selection signal T1 as one input is "1". Since the output signal of the OR gate 27, which is one input, that is, the logical sum signal of the selection signals T1 and T2 is "1", the output signal of the AND gate 25 is the second conversion means which is the other input. It has the same value as the inverted signal of the twelve non-detection signals NS2.

At this time, assuming that “00xx” is input as the bit string BIN to be converted, the variable length code “00xx” in Table 2 is not in Group 1 but in Group 2
, The non-detection signal NS1 of the first conversion means 11
Becomes "1", while the non-detection signal NS2 of the second conversion means 12 becomes "0". Therefore, the output signal of the AND gate 24 becomes "0", while the output signal of the AND gate 25 becomes "1", whereby the output of the first tri-state buffer 21 becomes a high impedance state, and The second tri-state buffer 22 outputs the code data DT2 of the second conversion means 12 as it is. Since the second conversion means 12 outputs "001" as the code data DT2, the output data DO from the variable-length code converter is output.
“001” is output as the UT.

At this time, in the illegal code detecting means 30, the output signal of the AND gates 31, 32 is such that the non-detection signal NS2 of the second converting means 12, which is one input, is "0".
Therefore, both become "0", and the OR gate 33 outputs the logical sum signal of the output signals of the AND gates 31, 32, that is, "0".
Is output to the output line of the illegal code detection signal NG.

On the other hand, at this time, the bit string BIN to be converted is
Assuming that a variable length code that does not belong to any of the groups 1 and 2, for example, “100x” is input, the first and second conversion units 11 and 12 both output the non-detection signals NS1 and N2.
Since "1" is output as S2, the illegal code detecting means 3
At "0", the output signal of the AND gate 31 becomes "1" because the input signals are all "1". Therefore, "1" is output from the OR gate 33 as the illegal code detection signal NG.

The same operation is performed when the selection signal T1 is "0" and the selection signal T2 is "1", that is, when the coding system T2 is selected.

As described above, according to the variable-length code converter according to the present embodiment, the second conversion means 12 is shared for the common part between the coding system T1 and the other coding system T2. Accordingly, the number of circuits can be reduced, and the circuit scale can be made smaller than before. Further, the variable-length code converter according to the present embodiment can output an incorrect code detection signal NG indicating that the input bit string BIN to be converted has an error.

In this embodiment, all of the parts common to the coding system T1 and the coding system T2 are
Although the conversion means 12 is used, a configuration may be adopted in which the conversion means is shared for a part of a portion common to the coding system T1 and the coding system T2.

Further, the number of coding systems is not limited to two, and even if it is three or more, it is possible to realize a configuration sharing the conversion means in the same manner as in the present embodiment.

Although the variable length code converter is used here,
In the fixed-length code converter, similarly to the present embodiment,
A configuration that shares the conversion means can be realized.

FIG. 5 is a block diagram showing a configuration of a variable length code decoding apparatus according to one embodiment of the present invention. The variable-length code decoding device shown in FIG. 5 includes a variable-length code converter having a function of outputting an illegal code detection signal NG as shown in FIG. 1, and is used for variable-length code decoding in a DVD device, for example. It is something that can be done.

In FIG. 5, reference numeral 41 denotes a memory which stores a bit string to be decoded, 42 denotes a first register which stores a bit string read from the memory 41, and 43 denotes a first register which stores a bit string to be decoded. A second register for storing the output bit string, 44 is a first register and a second register.
A shifter that inputs the bit strings stored in the registers 42 and 43 as shifter inputs SIN, shifts the shifter input SIN by the shift amount SV toward the upper bits, and outputs
Numeral 45 designates the upper bit of the bit string output from the shifter 44 as a bit string BIN to be converted, and sign data DOUT
And a variable-length code converter for converting and outputting to a code length DL, 46
Is an accumulator that accumulates the code length DL output from the variable length code converter 45 and inputs the accumulated value to the shifter 44 as the shift amount SV. 47 indicates a case where variable length code decoding is not performed normally. Is a selector for selectively inputting either the overflow signal CR of the accumulator 46 or the signal "1" to the memory 41 as a read signal RO.

The memory 41 stores a bit string to be decoded in 8 bits.
Aligned and stored for each bit, and the read signal R
When "1" is given as O, a bit string is output in units of 8 bits. The first and second registers 42 and 43 constitute a shift register. The first register 42 stores an 8-bit bit string output from the memory 41 and stores the stored bit string in a second register. 43, and the second register 43 updates the stored bit string every time the bit string is input from the first register 42. The shifter 44 inputs a 16-bit bit string having the bit sequence stored in the first register 42 as the lower bit and the bit sequence stored in the second register 43 as the upper bit.
IN, the input 16-bit bit string is shifted to the upper side by the shift amount SV, that is, the number of bits corresponding to the accumulated value of the code length DL by the accumulator 46, and the upper 8 bits of the bit string of the shift result are shifted. Output.

The upper 4 bits of the 8-bit bit string output from the shifter 44 are input to the variable-length code converter 45 as a bit string BIN to be converted. The variable-length code converter 45 has a configuration as shown in FIG. 1, and the bit string BIN to be converted is a code system T1, T1 shown in Table 1.
It is determined whether or not any of the variable length codes belonging to the one designated by the selection signals T1 and T2 among T2 is applicable,
If so, the corresponding 3-bit code data is output as the output data DOUT. If none of the above applies, “1” is output as the incorrect code detection signal NG. The output data DOUT output from the variable length code converter 45 is output as decoded data from the variable length code decoder, and the illegal code detection signal NG output from the variable length code converter 45 is output from the variable length code decoder. Output as an error detection signal.

In this embodiment, the variable-length code converter 4
5 also generates and outputs the code length DL of the variable length code as information for obtaining the head bit position of the variable length code to be decoded next. Table 3 is a table showing the relationship between variable length codes, code data, and code lengths in the coding system T1, and Table 4 is a truth table in binary notation corresponding to Table 3.

[0059]

[Table 3]

[0060]

[Table 4]

The configuration for generating and outputting the code length in the variable-length code converter 45 is, for example, by using the output signal of the code detection unit 11a as in the case of the code data generation unit 11b shown in FIG. 4 can be easily realized based on the truth table shown in FIG. The accumulator 46 accumulates the 3-bit code length DL output from the variable-length code converter 45 up to “7” (decimal number), and inputs the accumulated value to the shifter 44 as the shift amount SV. When the accumulated value exceeds the upper limit, the overflow signal CR is set to "1". Normally (when the abnormal signal ER is not output from the controller 47), the selector 47 selects and outputs the overflow signal CR output from the accumulator 46 to the memory 41 as a read signal RO.

The controller 48 includes a variable length code converter 45
Outputs an abnormal signal ER when an invalid code detection signal NG is output from the controller. When the abnormal signal ER is output from the controller 48, the accumulator 46 resets the accumulated value to "0", and the selector 47 selectively inputs the signal "1" to the memory 41 as a read signal RO. Thereby, the memory 41
Outputs the stored bit string continuously in units of 8 bits.

The normal operation of the variable length code decoding apparatus according to this embodiment shown in FIG. 5 will be described first. In a normal operation, the controller 48 does not output the abnormal signal ER, and the selector 47 always outputs the overflow signal CR of the accumulator 46.
Is input to the memory 41 as a read signal RO.

FIG. 6 is a flowchart showing a normal operation of the variable length code decoding apparatus according to the present embodiment shown in FIG. Here, it is assumed that variable length code conversion based on the coding system T1 is performed.

Now, in cycle 1, the bit strings stored in the first and second registers 42 and 43 are "111xxxxxx" and "00011011", respectively.
It is assumed that the accumulated value of the accumulator 46 is “0”. At this time, the bit string input to the shifter 44 (shifter input SI
N) is “00011011111xxxxxx”,
Since the shift amount SV is “0”, the bit string output from the shifter 44 (enclosed by a broken line in the shifter input SIN in FIG. 6) is “00011011”. The variable length code converter 45 has the upper 4 bits of the output bit string of the shifter 44.
Since the bits are input as the bit string BIN to be converted, here, “0001” is the bit string BIN to be converted.
And based on the truth table of Table 4, the data DO
“001” as the UT and “010” as the code length DL
(Decimal "2") is output. Accumulator 4
6 accumulates the code length DL output from the variable length code converter 45, so that the accumulated value becomes "2".

Next, in cycle 2, the shifter 44
Since the shift amount SV is “2”, “01” is
101111 ". Therefore, the bit string BIN to be converted becomes" 0110 "and the variable-length code converter 45
Outputs “010” as data DOUT and “010” (decimal “2”) as code length DL based on the truth table of Table 4. As a result, the accumulator 46
Is "4".

The same operation is performed in cycle 3. The shifter 44 outputs “10111111” as a bit string because the shift amount SV is “4”. Therefore, the conversion target bit string BIN becomes “1011”, and the variable-length code converter 45 outputs the data DOU based on the truth table of Table 4.
“011” as T and “011” as code length DL
(Decimal "3") is output. As a result,
The accumulated value of the accumulator 46 becomes "7".

The same operation is performed in cycle 4. The shifter 44 outputs “1111xxxx” as a bit string because the shift amount SV is “7”. Therefore, the conversion target bit string BIN becomes “1111”, and the variable-length code converter 45 outputs the data DOU based on the truth table of Table 4.
“100” as T and “100” as code length DL
(Decimal "4") is output.

At this time, the accumulator 46 adds the code length "4" to the accumulated value "7". However, since the upper limit of the accumulated value is "7", overflow occurs, and the accumulated value becomes "3". And outputs “1” as the overflow signal CR. Since the overflow signal CR is input to the memory 41 via the selector 47 as a read signal RO, as a result, in the cycle 5,
From the memory 41, a new 8-bit bit string “xxxx
xxx "is read out, and the bit string" 111x "stored in the first register 42 is stored in the second register 43.
xxxx "is stored. At this time, the shifter input SIN
Becomes “111xxxxxxxxxxxx” and the shift amount SV is “3”, so that the bit string output from the shifter 44 becomes “xxxxxxxxx”.

Next, the operation when an error occurs in the bit string will be described.

For some reason, "0" / "1" is added to the bit string.
When an error such as inversion of
Since the code length cannot be determined correctly, decoding after the occurrence of an error is random or impossible. In the variable length code decoding apparatus according to the present embodiment shown in FIG. 5, the occurrence of an error in a bit string is detected by the variable length code converter 45, and at this time, an operation of searching for a header in the bit string is performed.

FIG. 7 is a diagram showing a schematic configuration of a bit string in a DVD device. As shown in FIG. 7, a bit sequence in a DVD device has a hierarchical structure of slices, pictures, and sequences. A sequence corresponding to the entire bit sequence includes several pictures, a picture includes several slices, and a slice. Consists of a block of data called a macroblock. Also slice,
Each of the picture and the sequence has a header indicating the head position of the data. MPEG, which is an international standard for image compression, defines a bit string in which 23 or more “0” s are followed by “1” as a start code prefix indicating the beginning of a header. The header indicates the type of the header (slice, picture or sequence) in addition to the start code prefix.
It has a start code value of bits.

In the variable length code decoding apparatus shown in FIG.
The variable length code converter 45 outputs an invalid code detection signal NG when the input bit string BIN to be converted does not correspond to any variable length code. Controller 4
8 is an illegal code detection signal NG from the variable length code converter 45.
Is output, the decoding operation is interrupted and the variable-length code decoding device is controlled so that the header in the bit string is searched backward from the bit string BIN to be converted.

That is, when the illegal code detection signal NG is output from the variable length code converter 45, the controller 48
Outputs an abnormal signal ER, and in accordance with the abnormal signal ER, the accumulator 46 resets the accumulated value to “0”, and the selector 47
Selectively outputs a signal "1" to the memory 41 as a read signal RO. As a result, the bit string of 8
The shift amount S of the shifter 44 is read out in bit units.
Since V is “0”, the bit string stored in the memory 41 is output from the shifter 44 in units of 8 bits. The controller 48 monitors the 8-bit bit string output from the shifter 44. When the same bit string as the start code prefix indicating the start of the header is output from the shifter 44, the controller 48 recognizes that the header has been detected and recognizes the abnormal signal ER. Cancel. As a result, normal variable-length code decoding is restarted immediately after the detected header.

For example, in the case of MPEG, “00000000”, “00000000”, “000”
It is sufficient to recognize that the header has been detected when the data is continuously output as "00001". In this case, the header of the slice (in some cases, the header of the picture or the sequence) is detected.

By such an operation, even when an error occurs in the bit string, a normal variable length code decoding operation can be reliably restored in a short time. Further, since the normal variable-length code decoding operation can be restarted from the next slice, the error of the bit string hardly affects the data.

In this embodiment, the controller 47, the selector 48, the memory 41, the first and second registers 42, 43, and the shifter 4 used in the normal operation are used.
4 and the accumulator 46 constitute a header search means. That is, the variable-length code decoding device according to the present embodiment has a
7 and a selector 48, and a header search means is realized by an extremely simple configuration.

The variable-length code decoding apparatus according to the present embodiment shown in FIG. 5 is not only used for variable-length code decoding in a DVD device, but is not limited to variable-length code decoding for a bit string having a header indicating data delimiter. If it is code decoding, it can be applied to other uses.

The configuration of the variable-length code converter 45 shown in FIG. 5 is not limited to that shown in FIG. 1, but may be, for example, a configuration shown in FIG. 8, which does not have a plurality of conversion means. The variable length code converter shown in FIG.
And a code detecting section 51 which receives a bit string BIN to be converted and detects each variable length code, and detects a variable length detected based on the detection result of the code detecting section 51. Output data DOU corresponding to code
And a code data generator 52 for generating and outputting T and an invalid code detection signal NG. The code detection unit 51 includes a complementary buffer group 53 that receives each bit of the bit string BIN to be converted and outputs a non-inverted signal and an inverted signal, and an AND gate group 54 corresponding to each variable-length code. From output signals of AND gate group 54, output data D
An OR gate 55 for generating and outputting OUT, and a NOR gate 56 for generating and outputting an incorrect code detection signal NG from the output signal of the AND gate group 54 are provided.

Although the variable-length code decoding apparatus is used in the present embodiment, the present invention may be applied to an algorithm of variable-length code decoding software including an illegal code detection step and a header detection step.

[0081]

As described above, according to the code converter of the present invention, it is possible to reduce the number of circuits corresponding to parts common to one code system and another code system.
The circuit scale can be made smaller than before.

Further, according to the variable length code decoding apparatus and method of the present invention, if an error is found in a bit string, it is immediately detected, and decoding is restarted immediately after a header indicating a data delimiter. Recovery of the decoding process can be performed more finely than before, and the code data after the recovery has high reliability and can be applied to a real-time decoding process.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a code converter according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a first converter 11 in the code converter according to the embodiment of the present invention shown in FIG.

FIG. 3 is a diagram showing a configuration of a second conversion unit 12 in the code converter according to the embodiment of the present invention shown in FIG. 1;

FIG. 4 is a diagram showing a configuration of a third conversion unit 13 in the code converter according to the embodiment of the present invention shown in FIG. 1;

FIG. 5 is a diagram showing a configuration of a variable-length code decoding device according to one embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the variable length code decoding device according to the embodiment of the present invention shown in FIG.

FIG. 7 is a diagram showing a schematic configuration of a bit string in a DVD device.

FIG. 8 is a diagram illustrating another configuration example of the variable-length code converter used in the variable-length code decoding device according to the embodiment of the present invention.

[Explanation of symbols]

 11 first conversion means (first dedicated conversion means) 12 second conversion means (shared conversion means) 13 third conversion means (second dedicated conversion means) 20 selecting means 30 illegal code detection means 41 memory 42 First register 43 Second register 44 Shifter 45 Variable length code converter 46 Accumulator 47 Controller 48 Selector BIN Bit string to be converted CR Overflow signal DT1, DT2, DT3 Code data DOUT Output data DL Code length ER Abnormal signal NS1, NS2, NS3 Non-detection signal NG Unauthorized code detection signal RO Readout signal SIN Shifter input SV Shift amount

Claims (8)

[Claims] 1. A code converter for converting a coded bit string to be converted into code data based on a designated one of a plurality of coding systems, comprising: one coding system and another coding system. A common conversion means for storing the correspondence between codes and code data included in a common part with the coding system, and for converting the bit string to be converted into code data based on the stored correspondence. A code converter, wherein both the code conversion based on the one code system and the code conversion based on the other code system are performed using the shared conversion unit. 2. The code converter according to claim 1, wherein the common conversion unit outputs a non-detection signal when the bit string to be converted does not correspond to any of the stored codes. When the code converter performs code conversion based on the one coding system or another coding system, when a non-detection signal is not output from the common conversion unit, the code conversion is performed by the common conversion unit. A code converter characterized by comprising a selecting means for selecting and outputting the encoded data as output data of the code converter. 3. The code converter according to claim 2, wherein a correspondence relationship between codes other than those stored in said common conversion means and code data in said one coding system is stored, and Is converted into code data based on the stored correspondence relationship, and when the bit string to be converted does not correspond to any of the codes belonging to the stored correspondence relationship, a dedicated non-detection signal is output. Conversion means, when performing code conversion based on the one coding system, when a non-detection signal is output from both the common conversion means and dedicated conversion means, that there is an error in the bit string to be converted. And a malicious code detection means for outputting a malicious code detection signal shown in the figure. 4. The code converter according to claim 1, wherein the common conversion means outputs a non-detection signal when the bit string to be converted does not correspond to any of the stored codes. The code converter stores the correspondence between codes and code data other than those stored in the common conversion unit in the one coding system, and stores the bit string to be converted. First dedicated conversion means for outputting a non-detection signal when the bit string to be converted does not correspond to any code belonging to the stored correspondence while converting the code data into code data based on the corresponding correspondence And a correspondence relationship in which the correspondence between codes other than those stored in the shared conversion means and the code data in the other code systems is stored, and the bit string to be converted is stored. A second dedicated conversion unit that outputs a non-detection signal when the bit string to be converted does not correspond to any code belonging to the stored correspondence, When performing code conversion based on the system, code data converted by one of the common conversion means and the first dedicated conversion means that did not output a non-detection signal is selectively output as output data of the code converter. While
When performing code conversion based on the other code system, the code data converted by one of the common conversion means and the second dedicated conversion means that did not output a non-detection signal is output from the code converter. Selecting means for selecting and outputting as data; and performing code conversion based on the one coding system, when a non-detection signal is output from both the common conversion means and the first dedicated conversion means, the conversion target While outputting an invalid code detection signal indicating that there is an error in the bit string of
When performing code conversion based on the other code system, when a non-detection signal is output from both of the common conversion unit and the second dedicated conversion unit, an unauthorized code detection unit that outputs the unauthorized code detection signal And a transcoder. 5. A variable-length code decoding apparatus for decoding a bit string consisting of continuous variable-length codes into code data, comprising: a conversion target bit string cut out from the bit string as an input; Determine whether it corresponds to any of the variable length codes belonging to the coding system,
When applicable, the conversion target bit string is converted and output into code data based on the predetermined coding system, and when none of the above applies, an invalid code detection indicating that there is an error in the conversion target bit string is performed. A variable-length code converter that outputs a signal, and a header search that searches backward from the bit string to be converted from the bit string to be converted, when an invalid code detection signal is output from the variable-length code converter. Means, the variable-length code decoding device, when an illegal code detection signal is output from the variable-length code converter, interrupts the decoding of the bit string, from immediately after the header detected by the header search means A variable length code decoding apparatus, wherein decoding of the bit string is restarted. 6. The variable-length code decoding device according to claim 5, wherein the variable-length code converter converts a bit string to be converted into code data based on a single coding system. A variable-length code decoding device that outputs the illegal code detection signal when the bit sequence does not correspond to any of the variable-length codes belonging to the single coding system. 7. The variable-length code decoding device according to claim 5, wherein the variable-length code converter converts a bit string to be converted into code data based on a designated one of a plurality of code systems. It stores the correspondence between the variable-length code and the code data, which is included in a common part between one coding system and another coding system, based on the stored correspondence. A common conversion unit that converts a bit string to be converted into code data, and outputs a non-detection signal when the bit string to be converted does not correspond to any variable length code belonging to the stored correspondence relationship. The correspondence between variable-length codes and code data other than those stored in the common conversion means in one coding system is stored, and the conversion target is stored based on the stored correspondence. Dedicated conversion means for converting a bit string into code data and outputting a non-detection signal when the bit string to be converted does not correspond to any of the variable length codes belonging to the stored correspondence; and the one code When performing variable-length code conversion based on the system, code data converted and output from the common conversion means and the dedicated conversion means from which the non-detection signal is not output is selected as output data of the variable-length code converter. Selecting means for outputting, and when performing variable length code conversion based on the one coding system, outputting the illegal code detection signal when a non-detection signal is output from both the common conversion means and the dedicated conversion means. A variable-length code decoding device comprising: an unauthorized code detection unit. 8. A variable-length code decoding method for decoding a bit string composed of continuous variable-length codes into code data, wherein a bit string to be converted cut out from the bit string is
An illegal code detection step of determining whether or not the variable length code belongs to a predetermined code system; and in the illegal code detection step, a bit string to be converted is one of a variable length code belonging to a predetermined code system. A header search step of interrupting decoding of the bit string, and searching backward from the bit string to be converted for a header indicating a data delimiter in the bit string when the bit search is not performed. A decoding of the bit string is resumed immediately after the header.