JPH1084117A - Liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high mobility even if the semiconductor has a photosensitivity by a method wherein insulated-gate type field-effect transistor (TFTs) are formed on the same substrate and impurities are added to a channel formation region using the N-channel and P-channel TFTs (NTFT and PTFT), which are provided at the irradiation part of the display device, as non-photosensitive ones. SOLUTION: A silicon oxide film is formed on a glass 1, which can stand a heat treatment of 700 deg.C or lower, as a blocking layer 38. A silicon film, which is added the total amount only of 7×10<19> cm<-3> or less of oxygen, carbon and nitrogen impurities, is formed on this film 8. A silicon film in an amorphous state is formed and is treated by heating in a non-oxidizing atmosphere of a middling temperature in an extent that a crystal growth is not caused. Moreover, a drift of a P-channel TFT and an N-channel TFT is eliminated setting the concentration of oxygen, nitrogen or carbon in a channel formation region at a concentration of 1×10<20> to 8×10<21> cm<-3> . Thereby, a liquid crystal display device has a photosensitivity and can be given a large mobility.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor (hereinafter referred to as a TFT) having a thin film structure used for an active type liquid crystal display device or an image sensor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an active liquid crystal display device using a TFT has been known. This display device has a display portion and a peripheral circuit portion, and the peripheral circuit portion is provided with a single crystal integrated circuit by tab bonding or COG (chip-on-glass) bonding, and furthermore, a TFT is provided in each pixel in the display portion. It is a hurry. For the TFT, a polycrystalline semiconductor having an amorphous or crystal grain boundary is used, and a TFT of only one of the P and N conductivity types is used for one pixel.
That is, generally, an N-channel TFT (referred to as NTFT) is serially connected to a pixel.

However, a semiconductor having an amorphous structure has a low carrier mobility, and in particular, a hole has a carrier mobility of 0.1.
As small as 1 cm ² / Vsec or less. Also, semiconductors with a polycrystalline structure
There are drawbacks that the drain breakdown voltage cannot be sufficiently increased due to impurities such as oxygen segregated at the crystal grain boundaries and dangling bonds, and it is difficult to form a P-channel TFT. Furthermore these TF
T has photosensitivity (photosensitivity PS), and Vg-I _D (gate voltage-drain current)
There is a drawback that characteristics and the like change greatly.

[0004] Therefore, the backlight of the liquid crystal display device,
For example, it was an important process to form a light-blocking layer so that 2000 cd (candela) did not irradiate the TFT channel formation region with light.

A liquid crystal display device is, for example, as shown in FIG.
A liquid crystal (12) and an NTFT (11) connected in series with the liquid crystal (12) are provided and arranged in a matrix. Generally 640
In this drawing, a 2 × 2 matrix arrangement is simply used in the same meaning as in the case of × 480 or 1260 × 960. Peripheral circuits (16), (17)
Apply more voltage, selectively turn on certain pixels,
Other pixels were turned off. Then, when the on / off characteristics of the TFT are generally good, a liquid crystal display device having a high contrast can be manufactured. However, when actually manufacturing such a liquid crystal display device, the output of the TFT, that is, the voltage V _LC (10) of the input to the liquid crystal (referred to as the liquid crystal potential) is often "1" (High) when it should be "1" (High). Sometimes it does not become 1 "(High), and conversely it does not become" 0 "(Low) when it should be" 0 "(Low). The liquid crystal (12) is inherently insulating in its operation, and the liquid crystal potential (V _LC ) floats when the TFT is off. Since the liquid crystal 12 is equivalently a capacitor, _VLC is determined by the electric charge stored therein. This charge is _leaked through the RSD of the channel of the TFT when the shading is not sufficient because the conventional TFT is photosensitive.
(15), and as a result, the level of _VLC fluctuates. Furthermore, the liquid crystal becomes relatively small in resistance due to _RLC , and the leakage occurs.
If the step (14) occurs, _VLC will be in an incomplete state. Therefore, in a liquid crystal display device having 200,000 to 5 million pixels in one panel, a high yield cannot be achieved.

[0006]

According to the present invention, a TFT in a display section of a display device is made non-photosensitive, and a peripheral circuit section which is a non-display section has a complementary structure in which high-speed operation is performed. In addition, a TF selected from among multiple TFTs
In an active type liquid crystal display device as an application of the method, only the T is made non-photosensitive, and the liquid crystal potential is constantly kept at the same level as the initial value for one frame, and the level is drifted. It is an improvement of the TFT so that it does not.

[0007]

According to the present invention, a semiconductor material in a channel forming region of a TFT provided in a display portion of a display device to which light is irradiated is made of a material which is not photosensitive to light. Silicon in which oxygen, carbon, or nitrogen impurities are selectively added to a channel formation region is used, and the region has crystallinity but is desensitized to photosensitivity. For the peripheral circuit portion on the same substrate that is not irradiated with light, a high-speed operation is performed to make it complementary, and further crystallization is promoted by not adding or reducing impurities. It is a thing.

In addition, the total amount of impurities of O, C, and N is selectively reduced to 1 × 10 ²⁰ cm ^{−3 to} 20 atom% (8 × 10 ²¹ cm) in the non-photosensitive TFT channel formation region by ion implantation or the like. ^-3 ), preferably 2 × 10 ²⁰ cm ^-3 to 2 atomic% (5 × 10 ²⁰ cm ^-3 ).
However, the semiconductor material is crystallized by a heat treatment at 500 to 750 ° C., and has a carrier mobility of 5 cm ² / Vsec or more, thereby substantially eliminating crystal grain boundaries and providing a crystalline semiconductor material.

Thus, this TFT is non-photosensitive, that is, the change in current in the ON state is 10% or less, and the TFT is in the OFF state (sub-threshold state) and has a dark current of the order of 10 ^-9 A. An increase of less than 10 ^-7 A, that is, a change of less than two orders of magnitude
It was achieved by irradiating visible light of 2000 candela.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS When the present invention is used for a display device, particularly for a liquid crystal display device, an electrode of one transparent conductive film (pixel) of each pixel (combined transparent conductive film and TFT) arranged in a matrix. And the output terminal of the complementary TFT. That is, a P-channel type TFT (hereinafter, referred to as PTFT) and an NTFT are connected to all the pixels arranged in a matrix as a complementary type (hereinafter, referred to as C / TFT) to form a pixel.

A typical example is shown in FIGS. 4, 5 and 6 as a circuit. FIGS. 8, 9 and 10 show examples of actual pattern layouts (arrangement diagrams). That is, in FIG. 4, the display section has a 2 × 2 matrix, and the peripheral circuit sections are indicated by (16) and (17). One pixel (34) of the display unit connects the gates of the PTFT and the NTFT to each other, and further connects to a line V _GG (22) or V _{GG ′} (23) in the Y-axis direction. The common output of the C / TFT is connected to the liquid crystal (12).
Connect the PTFT input (Vss side) to the X-axis line V _DD (18), V _DD '(1
Linked to 8 '), are input NTFT the (V _SS side) is connected to Vss (19).

When V _DD (18) and V _GG (22) are “1”, the liquid crystal potential (10) becomes “0”, and V _DD (18) becomes “1” and V _GG (22).
Is "0", the liquid crystal potential (10) becomes "1". That is, V _GG and V
_LC is "opposite phase". 4, when arranged in reverse the NTFT and PTFT, and V _GG and V _LC can be "in phase".

Further, the peripheral circuit is free from such impurities such as oxygen, and has a sufficiently small TFT, especially C / TF.
Made of T, each TFT mobility 40-200 cm / Vsec
As high speed operation.

[0014]

【Example】

Embodiment 1 In this embodiment, the present invention will be described with reference to FIGS.

A manufacturing process when two types of C / TFTs are formed on the same glass substrate will be described with reference to FIGS. (A) to (F) in each drawing are used in other drawings.
(A) to (F) are supported.

FIG. 1 shows an example in which a non-photosensitive TFT is formed as a C / TFT. Figure 2 shows a high mobility TFT, especially C / TF, on the same substrate.
Here is an example of making T.

In FIG. 1 and FIG. 2, a heat treatment of NO glass (manufactured by Nippon Electric Glass), LE-30 (manufactured by HOYA), Bicol 7913 (manufactured by Corning), etc. at 700 ° C. or less, particularly about 600 ° C. Using a magnetron RF (high frequency) sputtering method, a silicon oxide film as a blocking layer (38)
Fabricated to a thickness of ~ 3000 mm.

Process conditions are 100% oxygen atmosphere, film formation temperature
The temperature was 150 ° C, the output was 400 to 800 W, and the pressure was 0.5 Pa. Film formation rate using quartz or single crystal silicon as target is 30Å
/ Min.

On top of this, a silicon film to which a total amount of oxygen, carbon or nitrogen is added not more than 7 × 10 ¹⁹ cm ^−3, preferably 1 × 10 ¹⁹ cm ⁻³ or less is formed by LPCVD (low pressure gas phase) method or sputtering method. Alternatively, it was formed by a plasma CVD method. When formed by the reduced pressure gas phase method, 450 to 100 ° C lower than the crystallization temperature
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied at 550 ° C., for example, 530 ° C., to a CVD apparatus to form a film. The pressure in the reactor was 30 to 300 Pa. The deposition rate was 30 to 100 Å / min. NTET and PTFT threshold voltage (Vth)
May be added during the film formation at a concentration of 1 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ using diborane.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ⁻⁵ Pa or less, single crystal silicon is used as a target, and argon is mixed in an atmosphere containing 50 to 80% by volume of hydrogen. For example, argon was 20% by volume and hydrogen was about 80% by volume. The film formation temperature was 150 ° C., the frequency was 13.56 MHz, and the sputter output was 400 to 800 W. The pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a reactive gas. these
The film was introduced into a PCVD apparatus, and a film was formed by applying a high frequency power of 13.56 MHz.

The coatings formed by these methods are:
Oxygen was only contained at 7 × 10 ²⁰ cm ^−3, preferably at 1 × 10 ¹⁹ cm ⁻³ or less. Then, although this film has photosensitivity, it has a feature that it is more easily crystallized than when oxidation or the like is added.

In this embodiment, as shown in FIGS.
The semiconductor film (2),
Other parts were removed except for (2 '), (42), and (42'). Further, in FIG. 1, the photoresist (35) was selectively removed using a second photomask. The removed regions (36), (3
6 ') constitutes the PTFT and NTFT channel forming regions, respectively. For this opening, C, N or O, for example, O is 2 ×
A dose impurity of 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² was added by an ion implantation method (shaded area). The applied voltage was 30 to 50 KeV, for example, 35 KeV.

As a result, in FIG. 1A, no impurity is added at all, and the source
The region serving as a source or drain has very few impurities such as oxygen, and crystallization can proceed more strongly. A part of it extends to a lateral depth of 0 to 5 μm in a region to be a source and a drain in a later step (FIG. 1C).
(Relations between (61) and (62)).

In other words, C, O, and N may be added to make the film non-photosensitive. However, if it is too much, it becomes difficult to crystallize even in the subsequent heat treatment, and the carrier mobility is 5 cm ² / Vsec or more, preferably 10 to 10 cm ² / Vsec. This is because 100 cm ² / Vsec cannot be obtained.

Thus, the amorphous silicon film is reduced to 50
After fabrication to a thickness of 0-10000 Å (1 μm), for example 2000 Å,
Heat treatment was performed in a non-oxide atmosphere at a medium temperature of 500 to 750 ° C. at a temperature that does not cause crystal growth for 12 to 70 hours. For example, it was kept at a temperature of 600 ° C. in a nitrogen or hydrogen atmosphere.

Since a silicon oxide film having an amorphous structure is formed on the lower substrate surface of the semiconductor film, no specific nucleus is present in this heat treatment, and the whole is annealed uniformly. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By this annealing, the semiconductor film in the channel formation region shifts from an amorphous structure to a highly ordered state, and a part of the semiconductor film exhibits a crystalline state. In particular, a region having a relatively high order at the time of forming a silicon film is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, the silicon mutually pulls each other. When the crystal is measured by laser Raman spectroscopy, the peak of the single crystal silicon (111) crystal orientation is 522.
A (111) crystal peak having a lattice strain shifted to a lower frequency side than cm ⁻¹ is observed. Calculated from the half-value width, the apparent particle size is 50 to 500 mm, which is like a microcrystal.In fact, there are many regions with high crystallinity and a cluster structure. Was able to form a semi-amorphous film that was bonded (anchored) by silicon together.

For example, when the distribution measurement in the depth direction is performed by SIMS (Secondary Ion Mass Spectrometry), the lowest region (surface or a position away from the surface (inside)) as an additive (impurity)
Oxygen is 2 × 10 ²¹ cm ⁻³ (5 atomic%) and nitrogen is 4 × 10 ¹⁷
cm ^-3 was obtained. Hydrogen is 4 × 10 ²⁰ cm ⁻³ and silicon 4
It was 1 atomic% as compared with × 10 ²² cm ⁻³ .

In this crystallization, the oxygen concentration is, for example, 1.5 × 10 ²¹
In the case of cm ^-3 , heat treatment at 600 ° C. (48 hours) is possible with a film thickness of 1000 °. When this is set to 5 × 10 ²¹ cm ⁻³ , the film thickness becomes 0.
Crystallization by annealing at 600 ° C. was possible with a thickness of 3 to 0.5 μm, but heat treatment at 650 ° C. was required for crystallization with a thickness of 0.1 μm. That is, the thicker the film, the lower the concentration of impurities such as oxygen,
Crystallization was easy. As for the non-photosensitivity, the light irradiation amount was reduced when oxygen was further reduced.

As a result, the coating exhibits a state substantially free of grain boundaries (GB). Carriers can easily move from one another between the clusters through anchored locations, resulting in higher carrier mobilities than 13 so-called GB of well-defined polycrystalline silicon. That is, hole mobility (μh) = 10 to 50 cm ² / Vsec and electron mobility (μe) = 15 to 100 cm ² / Vsec.

The PS is shown in FIGS. 7A and 7B.
Is Vg (gate voltage) −I_D(Drain power
Irradiate 2000 candela lights from the glass side while obtaining the characteristics
Shoot I_DMoves only 10% or less in the area where
No conditions or sub-threshold voltage
I in the area_DWhen there is no more than two orders of magnitude increase (drift)
(The condition where the off-state current is sufficiently small) was measured. Do
And the oxygen concentration in the channel formation region is 8 × 10¹⁹cm^-3Etc.
There is a drift when the concentration is low, but 1 × 10^{twenty one}cm ^-3Less than
Preferably 3 × 10^{twenty one}cm^-3With the above, almost
Ft was not seen in PTFT or NTFT.

On the other hand, when the film is polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at medium temperature as described above, segregation of impurities such as oxygen in the film by solid phase growth from nuclei. In GB, impurities such as oxygen, carbon, and nitrogen are increased in GB, and the mobility in the crystal is large. However, a barrier is formed in GB to hinder the movement of carriers there. As a result, only a mobility of 5 cm ² / Vsec or less can be obtained, and in fact, a reduction in breakdown voltage due to leakage at a drain junction at a crystal grain boundary occurs.

That is, as described above, in the embodiment of the present invention, a silicon semiconductor having a semi-amorphous or semi-crystalline structure which is not photosensitive and has crystallinity is used in FIG. In FIG. 2, a silicon semiconductor having photosensitivity but having a mobility two to four times larger than that of FIG. 1 is used.

In FIG. 1 and FIG. 2B, a silicon oxide film is formed thereon as a gate insulating film to have a thickness of 500 to 2000.
Å formed. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. A small amount of fluorine may be added during this film formation.

In order to improve the interface characteristics between the silicon oxide and the underlying semiconductor film and remove the interface level, it is preferable to simultaneously apply ultraviolet light and perform ozone oxidation. That is, when the sputtering method and the photo CVD method were used together under the same conditions as those for forming the blocking layer (38), the interface level could be reduced.

After this, phosphorus is added on the upper side by 1 to 5 ×.
Silicon film with a concentration of 10 ²⁰ cm ^-3 or this silicon film and molybdenum (Mo), tungsten (W), MoSi ₂
Alternatively, a multilayer film with WSi ₂ was formed. This was patterned using a third photomask. Then, a gate electrode (4) for PTFT and a gate electrode (4 ′) for NTFT were formed. For example, a channel length is 10 μm, and a gate electrode is made of phosphorous silicon.
2 μm, and molybdenum was formed thereon to a thickness of 0.3 μm.

In FIGS. 1 and 2C, the photoresist (3
1 ') using a photomask to form a PTFT source
(5) Boron was added to the region serving as the drain (6) with a low oxygen concentration at a dose of 1-2 × 10 ¹⁵ cm ⁻² by ion implantation.

Next, as shown in FIG. 1 and FIG.
1) was formed using a photomask. Then, phosphorus is added to the region to be the source (5 ′) and drain (6 ′) for NTFT by 1 ×.
An amount of 10 ¹⁵ cm ^-2 was added by ion implantation.

These steps were performed through the gate insulating film (3). However, in FIGS. 1 and 2 (B), the gate electrode (4),
Using (4 ′) as a mask, remove silicon oxide on the silicon film,
Thereafter, boron or phosphorus may be directly ion-implanted into the silicon film.

Next, after removing the photoresist (31), annealing was performed again at 630 ° C. for 10 to 50 hours. The PTFT source (5), drain (6), and NTFT source
(5 ′) and drain (6 ′) were formed as P ⁺ and N ⁺ regions by activating impurities.

Since this region has a small amount of oxygen and the like, the crystallinity is further improved even at the same temperature. As a result, the ionization rate (the number of acceptors or donors / the amount of implanted impurities) of impurities imparting a conductivity type such as boron and phosphorus could be varied to 50 to 90%.

Under the gate electrodes (4), (4 '), (44) and (44'), the channel forming regions (7), (7 ') (47) and (47') are semi-amorphous semiconductors. Is formed.

In FIG. 1C, the end (62) of the region to which an impurity such as oxygen is added extends from the end (61) of the impurity region to the impurity region, so that the boron or phosphorus here is formed. Although the ionization rate decreases, the crystal grain boundaries hardly exist on the surface where N ⁺ -I and P ⁺ -I are present, and as a result, the drain breakdown voltage can be increased.

In this manner, two types of C / TFTs can be manufactured as shown in FIGS. 1 and 2 without applying a temperature of 700 ° C. or more in all the steps even though the self-alignment method is used. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process that is extremely suitable for the large pixel liquid crystal display device of the present invention.

Thermal annealing was performed twice in FIGS. 1 and 2 (A) and (D). However, the annealing in FIGS. 1 and 2 (A) may be omitted depending on the desired characteristics, and both may be combined with the thermal annealing in FIG. 1 (D) to shorten the manufacturing time. 1 and 2E, an interlayer insulator (8) was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCV
The D method or the photo CVD method may be used. For example, 0.2 to 2.0 μm
It was formed in thickness. Then, as shown in FIGS. 1 and 2 (E),
A window (32) for an electrode was formed using a photomask.

Further, the total content of aluminum is 0.5 to
A lead (9), formed to a thickness of 1 μm by sputtering.
(9 ') and contacts (29) and (29') were fabricated using a photomask as shown in FIG. 1 (F).

In FIG. 2F, the leads (49), (49 ') and the output terminal (39) are formed of aluminum.
6 to form a logic circuit in the peripheral circuit section.

FIGS. 7A and 7B show the characteristics of PTFT and NTFT.
In FIG. 7 (A), a curve (72) is a characteristic of the PTFT (21) of FIG. 1. When light of 2000 cd is irradiated to the curve, the current in the sub-threshold region is assimilated by about one digit and the curve (72) is obtained. ') Got it. Curve (73) shows the characteristics of PTFT (51) in FIG.

In FIG. 7B, the curve (71) corresponds to FIG.
It is a characteristic example of 1). Irradiation with 2000 cd light increased the curve (71 ') and the current by about one digit in the off region. Curve (72)
Shows the characteristics of the NTFT of FIG.

The characteristics of such a TFT will be abbreviated. Mobility (
μ), threshold voltage (gate voltage when I _D = 0.1 μA), drain withstand voltage (V _BDV ), and photosensitivity (PS) were as follows. The above shows the case where the channel length is 5 μm and the channel width is 15 μm.

This embodiment is an example of a liquid crystal display device. Further, in order to connect the output of this C / TFT to the pixel, FIG.
In (F), an organic resin (34) such as polyimide was formed. The window was opened again with a photomask. In order to connect the output terminals of the two TFTs to one of the transparent electrodes of the liquid crystal device, an ITO (indium tin oxide film) was formed by a sputtering method. It was etched using a photomask to form a transparent electrode (33). The ITO was deposited at room temperature to 150 DEG C. and was achieved with oxygen at 200 DEG to 300 DEG C. or in air.

Thus, the PTFT without PS (21)
And NTFT (11) and transparent conductive electrode (33) on the same glass substrate
(1) Prepared above. PTFT (41), NTFT (51) with PS
Was fabricated on the same glass substrate as shown in FIG.

[Embodiment 2] FIG. 8A shows an embodiment corresponding to FIG. V _DD (18), V _SS (19), V _DD '(1
8 '), V _SS ' (19 '). V _GG (2
2), V _GG '(22') was formed.

FIG. 8A is a plan view, and FIG. 8B is a longitudinal sectional view of AA`. FIG. 8 is a longitudinal sectional view of BB ′.
It is shown in (C).

A PTFT (21) is provided at the intersection of the X-ray V _DD (18) and the Y-ray V _GG (22), and at the intersection of V _DD (18) and V _GG '(22'). A PTFT (21A) for each pixel is similarly provided. NTFT
(11) is provided at the intersection of V _SS (19) and V _GG (22). Below the intersection of V _DD (18 ′) and V _GG (22), a PTFT for another pixel is provided. It has a matrix configuration using C / TFT. The PTFT (21) is connected to the X-ray V _DD (18) through a contact (32) at the input end of the source (5),
The gate (4) is connected to the multilayered Y line V _GG (22). The output terminal of the drain (6) is connected to a pixel electrode (33) via a contact (29).

On the other hand, in the NTFT (11), the input terminal of the source (5 ') is connected to the X-ray V _SS (19) through the contact (32'), and the gate (4 ') is connected to the Y-ray V _GG. In (22), the output terminal of the drain (6 ') is connected to the pixel (33) via a contact (29'). Thus, between the X-rays (18) and (19) (inside), one pixel was constituted by the pixel (33) made of a transparent conductive film and the C / TFT. By repeating such a structure left, right, up and down, it has become possible to produce one example of a 2 × 2 matrix or a liquid crystal display device of a large pixel such as 640 × 480 or 1280 × 960 which is enlarged. FIGS. 8B and 8C correspond to the numbers in FIG. 1F.

The feature here is that two TFTs per pixel.
Are provided in a complementary configuration, pixel (33) has a liquid crystal potential V _LC , which means that either the PTFT is on and the NTFT is off, or the PTFT is off and the NTFT is on. It is fixed to the level of.

In FIG. 8, an alignment film and an alignment treatment are performed on these transparent conductive films, and a certain distance is left between this substrate and the other substrate having a liquid crystal electrode (FIG. 4 (23)). The components were arranged with each other by a known method. In the meantime, liquid crystal was injected or wired to complete the process.

If a TN liquid crystal is used as the liquid crystal material, it is necessary to make the interval about 10 μm and to form an alignment film on both transparent conductive films by rubbing.

When an FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is set to ± 20 V and the cell interval is set to 1.5 to
It may be 3.5 μm, for example, 2.3 μm, and an alignment film may be provided only on the opposite electrode (FIG. 4) (23) and rubbing treatment may be performed.

When a dispersion type liquid crystal or a polymer liquid crystal is used, an alignment film is unnecessary, and an operating voltage is ± 10 to ± 15 V and a cell interval is 1 in order to increase a switching speed.
薄 く 10 μm.

In particular, when a dispersion type liquid crystal is used, since a polarizing plate is not required, the amount of light can be increased both in a reflection type and in a transmission type. Since the liquid crystal has no threshold, as shown in the C / TFT of the present invention,
By using a C / TFT type in which a clear threshold voltage is defined, large contrast and crosstalk (bad interference with adjacent pixels) could be eliminated.

"Embodiment 3" This embodiment corresponds to FIGS.
It corresponds to. As is clear from this drawing, in the display section, the Y-line V _GG (22) is disposed at the center, and the portion sandwiched between the X-rays V _DD (18) and Vss (19) is one pixel (3
4) One pixel is composed of one transparent conductive pixel (33) and two PTFTs (21), (21 ′) and two NTFTs (1
1) and (11 ') are connected to two C / TFTs. All the gate electrodes are connected to V _GG (22) and two PTFTs (21),
(21 ') is V _DD (18), and the two NTFTs (11) and (11') are V _DD (18).
Connected to ss (19). If one of the two PTFTs or one of the NTFTs was defective, the defective TFT was destroyed by laser light irradiation, thereby providing redundancy. Therefore, the transparent conductive film (33) constituting the pixel has four TFs.
The source and drain of T were provided so as not to cover them.

For the peripheral circuit sections (16) and (17), high-speed operation was performed by using the TFT shown in FIG. 2, especially the C / TFT.

The other points are the same as those of the second embodiment, and these two types of C / TFTs use FIGS. 1 and 2 of the first embodiment.

"Embodiment 4" This embodiment corresponds to FIGS.
It corresponds to 0. One pixel in the display section is composed of two C / TFTs and two pixels. Ie PT
Liquid crystal connected to C / TFT output consisting of FT (21) and NTFT (11)
Composed of pixel (33) of (12) and other PTFT (21 ') and NTFT (11')
The pixel (33 ') of the liquid crystal (12') connected to the output of the C / TFT
It constitutes one pixel (34). Pixels (33) and (33 ')
Correspond to the combined pixel (33) that constitutes one pixel.

In this way, even if one of the pixels does not operate, the other pixel operates and the probability of generating a non-operational pixel when colorizing is reduced.

The peripheral circuit is shown by (16) and (17) in FIG. Here, the TFT of FIG.
T was used.

Other points not described here are the same as those described in the first and second embodiments.

Fifth Embodiment In the second, third and fourth embodiments, the input terminal of the PTFT is connected to V _DD and the input terminal of the NTFT is connected to Vss. In this embodiment, conversely, NT to V _DD side
The input terminal of FT was connected to the input terminal of PTFT on the Vss side. Then V when the V _LC is V _GG and the in-phase which is the output (V _GG is "1"
_LC becomes "1", and when V _GG is "0", V _LC becomes "0"). The output potential is given by V _GG -Vth. Thus, there is a disadvantage that V _GG must be larger than V _DD , but there is a feature that little or no care is required between the gate electrode and V _LC .

In such a case, in FIGS. 4, 5 and 6, the PTFT (21) and the NTFT (11) may be provided opposite to each other.
The peripheral circuit performed high-speed arithmetic processing using the TFT shown in FIG. 2, especially C / TFT. Therefore, Examples 2, 3, and 4
It can be made exactly the same as the manufacturing process in.

[Embodiment 6] In this embodiment, each pixel shown in FIG. 3 is provided with only 1T by connecting only NTFT to each pixel and the like.
It is of the r / cell type. Then, the level of _VLC becomes floating and varies, but the TFT shown in the present invention has a variation.
Since it is non-photosensitive, there is no need to provide light-blocking means for preventing light from being applied to the TFT in actual use, and an active-type liquid crystal display device can be manufactured more easily than before.
Others are the same as the first and third embodiments.

[0074]

According to the present invention, a TFT capable of performing high-speed operations on the same substrate, in particular, a C / TFT, and a non-photosensitive NTFT and PTFT are simultaneously provided in an irradiated portion to which light is irradiated. A non-photosensitive semi-amorphous semiconductor was obtained by adding impurities such as oxygen to the formation region. By doing so, the peripheral circuits do not irradiate light, so even if they have photosensitivity, high-speed arithmetic processing is performed using TFTs with high mobility, while the display unit is illuminated with light. But,
Light-shielding means is no longer required by using non-photosensitive TFTs.

1) A liquid crystal display device that does not require a shielding means can be manufactured. 2) A peripheral circuit and a display portion can be formed on the same substrate. 3) The carrier mobility of amorphous silicon The use of semi-amorphous semiconductor, which is more than 10 times larger than that of using a TFT, makes it possible to reduce the size of the TFT and has many advantages that even if two TFTs are provided in one pixel, there is almost no decrease in aperture ratio. Having.

The present invention relates to a high-speed TFT and a non-photosensitive
An example was shown in which a TFT was made and applied to a liquid crystal display device as an application. However, it can also be used as a load or a three-dimensional element in other semiconductor devices, for example, an image sensor, a monolithic integrated circuit.

In the present invention, a semi-amorphous or semi-crystalline semiconductor was used for the C / TFT. However, semiconductors of other crystal structures may be used if possible for the same purpose. Also self-aligned
High-speed processing was performed by C / TFT. However, the TFT may be manufactured by a non-self-aligned method without using the ion implantation method. Needless to say, an inverted stagger type TFT may be used instead of the stagger type.

The display medium of the present invention can be used as a transmission type liquid crystal display device or a reflection type liquid crystal display device. As the liquid crystal material, the above-mentioned TN liquid crystal, FLC liquid crystal, dispersion type liquid crystal, and polymer type liquid crystal can be used. In addition, an ionic dopant is added to a guest-host type or dielectric anisotropic type nematic liquid crystal and an electric field is applied. A phase change liquid crystal which causes a phase change between the liquid crystal and the liquid crystal and realizes a transparent or cloudy display can also be used. In addition to the liquid crystal, for example, a so-called electrophoretic display dispersion system in which pigment particles having different colors are dispersed in an organic solvent colored with a dye can be used.

[Brief description of the drawings]

FIG. 1 shows a manufacturing method in which a non-photosensitive thin film transistor (TFT) is formed in a complementary configuration.

FIG. 2 shows a method of manufacturing a TFT capable of high-speed operation in a complementary configuration.

FIG. 3 shows a circuit diagram of an active liquid crystal device using only one TFT.

FIG. 4 is a circuit diagram of an active liquid crystal device using the complementary TFT of the present invention.

FIG. 5 is a circuit diagram of an active liquid crystal device using the complementary TFT of the present invention.

FIG. 6 is a circuit diagram of an active liquid crystal device using the complementary TFT of the present invention.

FIG. 7 shows a characteristic (Vg-I _D ) curve of a TFT manufactured by the manufacturing method of FIGS.

8 shows a plan view (A) and longitudinal sectional views (B) and (C) of one substrate of the liquid crystal display device corresponding to FIG.

9 is a drawing of one substrate of the liquid crystal display device corresponding to FIG.

10 is a drawing of one substrate of the liquid crystal display device corresponding to FIG.

[Explanation of symbols]

(1) ・ ・ ・ ・ Glass substrate (2), (2 ′) ・ ・ Silicon semiconductor (3) ・ ・ ・ ・ Gate insulating film (4), (4 ′), (44), (44 ′) ・ ・.Gate electrodes (5), (5 '), (45), (45') ... source (6), (6 '), (46), (46') ... drain (7) , (7 ′), (47), (47 ′) ・ ・ ・ Channel forming region (9), (9 ′), (39), (49), (49 ′) ・ ・ ・ ・ Aluminum wiring (10) .... Liquid crystal potential (V _LC ) (11), (11 '), (11A), (11'A), (11B), (11'B), (50) ) (12), (12 '), (12A), (12'A), (12B), (12'B) ... liquid crystal (14), (15) ), (17) ・ Peripheral circuits (18), (18 ′) ・ V _DD (one of X-rays) (19), (19 ′) ・ Vss (one of X-rays) (21), (21 ′) ), (21A), (21'A), (21B), (21'B), (51)
P-channel thin film transistor (PTFT) (22), ( 22 ') · V GG, V GG' (Y line) (23), (33) , (33 '), (33A), (33'A), ( 33B), (33'B) ・ ・ ・ ・
Pixels made of transparent electrodes (34) ... Pixel (36) ... Oxygen-implanted region (38) ... Blocking layer ... Process using photomask

Claims (4)

[Claims] A silicon thin film semiconductor formed on a substrate and having a channel formation region, a source region, and a drain region; and a gate electrode provided near the channel formation region via a gate insulating film, The concentration of oxygen, nitrogen or carbon in the channel forming region is 1 × 10 ²⁰ to 8 × 10 ²¹ cm ⁻³ , and the concentration of oxygen, nitrogen or carbon in the source and drain is 7 × 10 ¹⁹ cm ^−3. An insulating gate type field effect transistor, an interlayer insulating film formed on the insulating gate type field effect transistor, and formed on the interlayer insulating film and electrically connected to the source region or the drain region. A lead, an organic resin film formed on the interlayer insulating film and the lead, and a drain region formed on the organic resin film. Or a liquid crystal display device characterized by having a pixel electrode electrically connected to the source region. 2. The liquid crystal display device according to claim 1, wherein said substrate is a glass substrate. 3. The liquid crystal display device according to claim 1, wherein the insulated gate field effect transistor is of a stagger type. 4. The liquid crystal display device according to claim 1, wherein said insulated gate field effect transistor is of an inverted stagger type.