JPH1083301A - Parallel processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To give compatibility between parallel processing and sequential processing and improve processing capability by invalidating the contents of an instruction register by a decoder by decoding an instruction. SOLUTION: A control means which executes only one instruction following a delayed branch instruction is provided to make the majority of software compatible. Namely, when a 2nd decoder 107 decodes the delayed branch instruction, the following delay slot instruction is present in a 1st instruction register 104. In this case, an instruction held in a 2nd instruction register 105, however, is an instruction which should not be executed. For the purpose, the 2nd instruction decoder 107 invalidates the contents of the 2nd instruction register 105 through a control signal line when detecting the delayed branch instruction to execute only the 1st instruction following the delayed branch instruction. When a 1st instruction decoder 106 is decoding the delayed branch instruction, the following delay slot instruction is being decoded by the 2nd instruction decoder 107 and there is no problem even at the time of parallel execution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU such as a minicomputer or a microcomputer, and more particularly to a parallel processing device and a parallel processing method suitable for high-speed operation.

[0002]

2. Description of the Related Art Conventionally, various measures have been taken to increase the speed of a computer. A typical approach is a pipeline. The pipeline is not to start the next instruction after completely processing one instruction, but to divide one instruction into multiple stages, and when the first instruction reaches the second stage, the next This is a method in which processing is performed in a bucket brigade manner, such as starting processing of the first stage of an instruction. For such a method, see Shinji Tomita, "Parallel Computer Configuration Theory", Shokodo, p. 25-68. When the n-stage pipeline method is used, one instruction is processed in each pipeline stage. However, n instructions can be simultaneously processed as a whole, and one instruction is provided for each pipeline pitch. Processing of the instruction can be completed.

It is well known that the instruction architecture of a computer has a great effect on its processing method and processing performance. Computers are classified from the viewpoint of instruction architecture.
er) and RISC (Reduced Instruction Set Computer)
And divided into

In the CISC, a complicated instruction is processed by using a micro instruction. In RISC, on the other hand, instead of narrowing down instructions to simple ones, instead of using microinstructions,
High speed is achieved by control using hard-wired logic.
The hardware outline and the pipeline operation of both conventional CISC and RISC will be described below.

FIG. 2 is a diagram for explaining a general configuration of a CISC type computer. 200 is a memory interface, 20
1 is a program counter (PC), 202 is an instruction cache, 203 is an instruction register, 204 is an instruction decoder,
205, an address calculation control circuit; 206, a control storage (CS) for storing microinstructions; 207, a microinstruction counter; 208, a microinstruction register;
09 is a decoder, 210 is a register MDR (Memory Data Register) for exchanging data with the memory, and 211 is a register MAR (Me) indicating an operand address on the memory.
mory AddressRegister), 212 is an address adder, 2
13 is a register file, 214 is an ALU (Arithmetic
and Logic Unit).

An outline of the operation will be described. The instruction indicated by the PC 201 is fetched from the instruction cache and set in the instruction register 203 through a signal 217. The instruction decoder 204 receives the instruction via signal 218 and sets the start address of the microinstruction via signal 220 to the microinstruction counter 207. Further, an address calculation method is instructed to the address calculation control circuit 205 through a signal 219. The address calculation control circuit 205 reads a register necessary for address calculation,
It controls the address adder 212 and the like. Registers required for address calculation are stored in the bus 2 from the register file 213.
26 and 227 to the address adder 212. On the other hand, the microinstruction is CS every machine cycle.
The ALU 214 and the register file 213 are used to control the ALU 214 and the register file 213. Reference numeral 224 denotes these control signals. The ALU 214 calculates data sent from the registers through the buses 228 and 229 and stores the data in the register file 213 again. The memory interface 200 is a circuit that exchanges data with the memory, such as fetching instructions and fetching operands.

Next, the pipeline operation of the computer shown in FIG. 2 will be described with reference to FIGS. 3, 4, and 5. The pipeline has six stages. In the IF (Instruction Fetch) stage, an instruction is read from the instruction cache 202 and set in the instruction register 203. In the D (Decode) stage, the instruction decoder 204 decodes the instruction. In the A (Address) stage, the address adder 21
2, the address of the operand is calculated. OF
In the (Operand Fetch) stage, the operand at the address pointed to by the MAR 211 is fetched through the memory interface 200 and set in the MDR 210. Next, EX
In the (Execution) stage, register file 213,
The data is called from the MDR 210, sent to the ALU 214, and calculated. Finally, in the W (Write) stage, the operation result is stored in one register in the register file 213 via the bus 230.

FIG. 3 shows a state in which an addition instruction ADD, which is one of the basic instructions, is continuously processed.
One instruction is processed for each machine cycle, and ALU21
4. Both address adders 212 operate in parallel every cycle.

FIG. 4 shows the processing of a conditional branch instruction BRAcc. A flag is generated by the TEST instruction. FIG. 4 shows a flow when the condition is satisfied. Since the flag is generated in the EX stage, three wait cycles occur until the jump destination instruction is fetched. As the number of pipeline stages increases, the number of wait cycles increases, and this becomes a bottleneck in performance improvement. FIG. 5 shows an execution flow of a complicated instruction. Instruction 1 is a complicated instruction. A complicated instruction is an instruction having a large number of memory accesses, such as a string copy, and is usually processed by extending the EX stage many times. The EX stage is controlled by a micro instruction. Microinstructions are accessed once per machine cycle. That is, complicated instructions are processed by reading the microprogram a plurality of times. At this time, since only one instruction enters the EX stage, the next instruction (instruction 2 in FIG. 5) is awaited. In such a case, ALU214 is always moving,
Play occurs in the address adder 212.

Next, the RISC type computer will be described. FIG. 6 is a diagram illustrating a general configuration of a RISC-type computer. 601 is a memory interface, 602 is a program counter, 603 is an instruction cache, 604 is a sequencer, 605 is an instruction register, 606 is a decoder,
607 is a register file, 608 is an ALU, 609 is an MDR, and 610 is a MAR.

FIG. 7 shows a processing flow of the basic instruction. IF
In the (Instruction Fetch) stage, the instruction indicated by the program counter 602 is read from the instruction cache and set in the instruction register 605. In addition, the sequencer 604 receives the flag signal 6 from the instruction signal 615 and ALU608.
16, the program counter 602 is controlled. R
In the (Read) stage, from the register file 607,
The register indicated by the instruction is transferred to ALU 608 via buses 618 and 619. In the E (Execution) stage, the ALU 608 performs calculations. Finally, W (W
In the (rite) stage, the calculated result is stored in the register file 607 via the bus 620.

In the RISC type computer, instructions are limited to only basic instructions. The operation is limited between the registers, and instructions involving operand fetch are only load instructions and store instructions. Complex instructions are realized by combining basic instructions. Further, the micro instruction is not used, and the contents of the instruction register 605 are directly decoded by the decoder 606 to control the ALU 608 and the like.

FIG. 7 shows a processing flow of a register-to-register operation. The pipeline has 4 simple instructions.
It is stepped.

FIG. 8 shows a processing flow at the time of a conditional branch. Since the number of pipeline stages is smaller than that of the CISC type computer, the number of wait cycles is small. In the example of FIG. 8, there is only one waiting cycle. In addition, the RISC type computer generally adopts a delayed branching method which effectively utilizes the one waiting cycle. In this method, as shown in FIG. 9, an ADD instruction following a BRAcc instruction is executed during a wait cycle. By embedding the instruction next to the branch instruction by the compiler in this way, a wasteful wait cycle can be completely eliminated.

However, R which can be efficiently executed in this way
The ISC type computer also has a disadvantage that it can execute only one instruction in one machine cycle.

For this reason, a recent RISC-type computer is provided with a plurality of operation units sharing a register file, as disclosed in Japanese Patent Application Laid-Open No. 63-49843, "Reduced instruction set computer", to simplify instructions and reduce the number of pipeline stages. A method has been devised in which a plurality of instructions are read in one machine cycle to control a plurality of arithmetic units.

However, in an actual RISC-type computer, instructions are sequentially processed using a single operation unit. Therefore, when a plurality of instructions are executed in parallel using a plurality of operation units, the same Operation cannot be guaranteed. For example, in the interrupt processing, m instructions are processed simultaneously, so that an interrupt is accepted in units of m instructions, which is different from the operation of the conventional sequential processing. In addition, software such as a debugger having a function of executing instructions in units of one instruction has a disadvantage that it cannot be used.

On the other hand, the above-mentioned special software can no longer be used, but a method which enables most conventional software to be used and can be executed at high speed is sufficiently useful. The most important point in such a method is how to execute m instructions including the delayed branch instruction described with reference to FIG. 9 in parallel and obtain the same execution result as in the case of sequential execution. The point is to solve the problem.

[0019]

SUMMARY OF THE INVENTION It is an object of the present invention to achieve both functions of increasing the processing capability by making the parallel processing compatible with the sequential processing.

Another object of the present invention is to provide, in a parallel operation,
Even if special conventional software cannot operate normally, most conventional software can operate normally and can be executed at high speed.

[0021]

In order to achieve the above object, the present invention comprises a program counter for indicating an instruction to be read from a memory, a plurality of instruction registers for respectively storing the instructions indicated by the program counter, A plurality of decoders for decoding an instruction stored in an instruction register, and a plurality of operation units for executing an operation, wherein at least one of the decoders invalidates the contents of the instruction register by decoding the instruction. It is characterized by the following.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.

FIG. 10 is a list of instructions of the processor described in this embodiment. All basic instructions are register-to-register operations. There are four branch instructions: an unconditional branch instruction BRA, a conditional branch instruction BRAcc (cc indicates a branch condition), a subroutine branch instruction CALL, and a return instruction RTN from the subroutine. In addition, there are a load instruction LOAD and a store instruction STOR. Data type is 3 for convenience of explanation
Although only a 2-bit integer is used, the present invention is not limited to this. The address is assigned every 32 bits (4 bytes). Further, the processing state flag change instruction includes a parallelized branch instruction PEXB and a branch destination instruction which start simultaneous reading of a plurality of instructions from the branch destination instruction, activate a plurality of arithmetic units, and turn on the processing state flag. , A serialized branch instruction SEXB instruction that starts reading one instruction, activates the first arithmetic unit, and turns off the processing state flag. For simplicity, the number of instructions is limited as described above. However, this does not limit the present invention, and the number of instructions may be further increased as long as it can process one machine cycle. FIG. 11 shows the instruction format. All instructions have a fixed length of 32 bits. The F, S1, S2, and D fields in the basic instruction each include a bit for indicating whether or not the operation result is reflected in the flag, a field for indicating the first source register, a field for indicating the second source register, and a destination register. Field.
FIG. 1A shows the configuration of this embodiment. 100 is an instruction cache, 101 is a program counter calculator that generates a 32-bit program counter, 102 is a latch that holds a program counter value, 103 is a processor status register that holds a processing state flag PE (116), and 143 is a program counter. Is a selector for adding 1 to “2”, 104 is a 32-bit first instruction register, 105 is a 32-bit second instruction register, 106 is a first instruction decoder, 107 is a second instruction decoder, and 108 is a second instruction decoder. One operation unit, 109 is a second operation unit, 110 is a register file, 111 is a sequencer, 112 is a memory address register MAR, 113 is a memory data register MDR, 114 is a memory write register MWR, and 115 is a data cache.

In this embodiment, two cycles are performed during one machine cycle.
Two instructions are read and executed in parallel. 12 to 15 show the operation of the basic pipeline processing in this embodiment. The pipeline is IF (Instruction Fetc)
h), R (Read), EX (Execution), and W (Write).

The operation of this embodiment will be described with reference to FIG. 1A again.

In the IF stage, the value of the processing state flag PE116 of the processor status register 103 is ON.
At this time, two instructions pointed to by the program counter are read out and set in the first instruction register 104 and the second instruction register 105 via the buses 117 and 118, respectively. When the PC is an even number, the instruction at the address PC is stored in the first instruction register and the instruction at the address PC + 1 is stored in the second instruction register. When the PC is an odd number, the first
The NOP instruction is set in the instruction register, and the instruction at the PC address is set in the second instruction register. That is, sequencer 1
Reference numeral 11 denotes a circuit for controlling the program counter. First
When neither the instruction register nor the second instruction register is a branch instruction, the value of the previous program counter value + 2 is set in the latch 102 in the program counter. At the time of branch,
Calculate the branch address and set it in the program counter. At the time of a conditional branch, the success or failure of the branch is determined from the flag information 120 from the first arithmetic unit 108 and the flag information 119 from the second arithmetic unit 109, and the program is executed using the branch destination address information 121 and the branch control information 122. The counter operation unit 101 is controlled.

Next, the operation of the R stage during basic instruction processing will be described. In the R stage, the first instruction register 1
04 is decoded by the first instruction decoder 106,
The contents of the second instruction register 105 are decoded by the second instruction decoder 107. As a result, the contents of the register pointed to by the first source register field S1 of the first instruction register 104 are transferred via the bus 127, and the contents of the register pointed to by the second source register field S2 are transferred via the bus 128 to the first operation unit 108. Sent to The contents of the register pointed to by the first source register field S1 of the second instruction
9, the contents of the register pointed to by the second source register field S2 are sent to the second arithmetic unit 109 via the bus 130. Next, the operation of the EX stage will be described.

In the EX stage, the first instruction register 10
4 according to the contents of the operation code of the first operation unit 108
, Execution between the data sent by the buses 127 and 128 is performed. In parallel, the second instruction register 105
In the second operation unit 109, the operation between the data transmitted by the buses 129 and 130 is performed according to the content of the operation code.

Finally, the operation of the W stage will be described. In the W stage, the operation result of the first operation unit 108 is
Through 31, it is stored in the register pointed to by the destination field D of the first instruction register. The operation result of the second operation unit 109 is stored in the register pointed to by the destination field D of the second instruction register via the bus 132.

FIG. 1B is obtained by adding the processing state flag changing means of FIG. 1A. That is, 144 and 145 are a first operation unit and a second operation unit, respectively, and PEXB and
This data line transmits flag value data to the processing state flag PE 116 when the SEXB instruction is executed. 14
Reference numeral 6 denotes a selector required when writing data to the processing state flag PE116.

FIG. 12 shows a flow of processing basic instructions continuously. Two instructions are processed in one machine cycle. Here, the upper one of the two instructions processed in FIG. 12 shows the processing of the first arithmetic unit, and the lower one shows the processing of the second arithmetic unit. In this example, the first operation unit and the second operation unit always operate in parallel.

FIG. 13 shows a flow for processing a load instruction or a store instruction as the first instruction and a basic instruction as the second instruction in succession. When the load instruction is executed, the contents of the register pointed to by the S2 field of the first instruction register are transferred to the MA through the bus 128 at the R stage.
Forwarded to R112. Next, in the EX stage, the operand is fetched from the data cache through the bus 133. Finally, the operand fetched at the W stage is stored in the register pointed to by the destination field D of the first instruction register via the bus 134. Fetching an operand in one machine cycle in the EX stage is possible if the high-speed data cache 115 is provided as shown in FIG. 1A. In particular, it is easy when the entire computer is integrated on a semiconductor substrate and both the instruction cache and the data cache are on-chip as shown in FIG. 1A. Of course, if the cache misses, the operand fetch cannot be completed in one machine cycle. In such a case, the EX stage may be extended by stopping the system clock. This is what is done with conventional computers.

Next, when the store instruction is executed, the contents of the register pointed to by the first source register field S1 of the first instruction register are transferred as data to the MWR 114 through the bus 135 in the R stage. At the same time, the contents of the register pointed to by the second source register field S2 of the first instruction register are used as an address as the bus 128
Through to the MAR 112. Next, at the EX stage,
The data in the MWR 114 is written to the address pointed to by the MAR 112. As shown in FIG. 13, a load instruction, a store instruction,
Two instructions can be processed in one machine cycle together with the instruction, for example, the ADD instruction in the figure.

FIG. 14B shows a processing flow when the unconditional jump BRA instruction is executed as the second instruction.
This drawing is also used for the description of another embodiment described later.

When the BRA instruction is read, the sequencer 111 adds the displacement field d and the program counter in the R stage, and sets the result in the latch 102 of the program counter. During this time B
The instruction at the address next to the RA instruction and the instruction at the next address (instruction 1 and instruction 2 in FIG. 14B) are read. In the next cycle, the two instructions at the jump destination are read. In the present embodiment, hardware capable of executing both the instruction 1 and the instruction 2 is used. That is, a wait cycle does not occur during the jump instruction processing. This method is called a delayed branch, and is also used in a conventional RISC computer. However, in the conventional RISC type computer, only one instruction can be executed during the calculation of the address of the jump instruction. However, in the present embodiment, two instructions are simultaneously processed during the calculation of the address of the jump instruction. Can be increased. The same applies to the processing flow of the CALL instruction and the RTN instruction. The compiler generates a code so that a valid instruction can be executed as much as possible during the calculation of the address of the branch instruction. However, when there is no operation, the instructions 1 and 2 in FIG. 14B are set as NOP instructions. At this time, a wait of substantially one machine cycle occurs. However,
Since the number of pipeline stages is shallow, the CI described in the conventional example
There is an advantage that the overhead at the time of branching can be reduced as compared with the SC type computer.

FIG. 15 shows a conditional branch instruction BR as a second instruction.
It shows a processing flow when an Acc instruction is executed. A
Flags are set by instructions DD and F, and the success or failure of the branch is determined according to the result. Also at this time, the instruction following the address where the BRAcc instruction is located, at the same time as the processing of the unconditional branch instruction described with reference to FIG.
Instruction 1 and the next instruction, Instruction 2 in FIG. 15, are read and processed. In the W stage during the processing flow of these two instructions, the operation result is stored in the register file regardless of whether the branch condition of the BRAcc instruction is satisfied or not. Writing is performed.

FIG. 16 shows a processing flow when the unconditional branch instruction BRA instruction is executed as the first instruction. B
When the RA instruction and the instruction 1 are read, in the R stage, the sequencer 111 performs addition of the displacement field d and the program counter, sets the result in the latch 102 of the program counter, and performs read parallel processing of the operand of the instruction 1. During this time, the instruction 2 at the next address of the instruction 1 and the instruction 3 at the next address are read out.
In this embodiment, the hardware is configured to execute the branch instruction and the instruction 1 in parallel, and to execute both the instruction 2 and the instruction 3. That is, two instructions including a branch instruction are executed in parallel, and the next two instructions can be executed. In a normal delayed branch instruction, only one instruction immediately after the branch instruction is executed in parallel, but in the case of FIG. 14B, the branch instruction executes two instructions immediately after the branch instruction, while in the case of FIG. Executes three instructions immediately after the branch instruction, which is different from a normal delayed branch. That is, the difference is that m instructions including a delayed branch instruction are executed in parallel, and the subsequent m instructions are executed using the branch time. Thereby, advanced parallel processing can be realized. On the other hand, FIG.
Shows a processing flow when the conditional branch instruction BRAcc instruction is executed as the first instruction. As in the processing flow of FIG. 16, the BRAcc instruction and instruction 1 are executed in parallel,
Instructions 2 and 3 are executed using the time to branch to jump destination instructions 1 and 2 regardless of whether the condition is satisfied.
This enables high-level parallel execution.
As can be seen from FIG. 7, two instructions and three instructions are executed immediately after the branch instruction. Thus, whether the branch instruction exists as the first instruction or the second instruction,
The number of instructions executed at the time of branching differs depending on the location.

As described above, FIG. 12, FIG. 13, FIG.
5, the processing status flag PE11 of the processor status register 103 as described with reference to FIGS.
When the value of 6 is ON, since two instructions are processed in one machine cycle, there is an advantage that the processing capacity is doubled at the maximum.

On the other hand, the processor status register 10
When the value of the processing state flag PE116 is OFF, the program counter is incremented by +1 via the control signal 136.
Instruction cache 1
00 is controlled by the control signal 137 so that one instruction having a 32-bit length is read out to the first instruction register 104 via the bus 117. The control signal 136 is
The first instruction decoder 106 and the second instruction decoder 107 are provided so that the first instruction decoder operates to process the instruction in the first instruction register 104 by the first arithmetic unit 108 and the second instruction decoder It operates to stop the second arithmetic unit. As a result, sequential processing by the first arithmetic unit can be performed.

Next, the pipeline operation when the value of the processing state flag PE116 of the processor status register 103 is OFF will be described in detail with reference to FIG. 1B.

In the IF stage, one instruction pointed to by the program counter is read out and set in the first instruction register 104 via the bus 117. It should be noted that the bus 118 has the processing status flag
At the time of FF, no valid instruction is output. That is, the sequencer 111 is a circuit that controls the program counter. When the first instruction register is not a branch instruction, the value of the previous program counter value + 1 is set to the latch 102 in the program counter. At the time of branching, the branch address is calculated and set in the program counter. At the time of the conditional branch, the flag information 12 from the first arithmetic unit 108
From 0, the branch success / failure is determined, and the branch destination address information 12 is determined.
The program counter arithmetic unit 101 is controlled by using 1 and the branch control information 122.

Next, the operation of the R stage during basic instruction processing will be described. In the R stage, the first instruction register 1
04 is decoded by the first instruction decoder 106. As a result, the contents of the register pointed to by the first source register field S1 of the first instruction register 104 are transferred via the bus 127, and the contents of the register pointed to by the second source register field S2 are transferred via the bus 128 to the first operation unit 108. Sent to

Next, the operation of the EX stage will be described.

In the EX stage, the first instruction register 10
4 according to the contents of the operation code of the first operation unit 108
, An operation is performed between the data transmitted by the buses 127 and 128.

Finally, the operation of the W stage will be described. In the W stage, the operation result of the first operation unit 108 is
Through 31, it is stored in the register pointed to by the destination field D of the first instruction register.

FIG. 18 shows a flow of processing basic instructions continuously. Although it has the ability to process two instructions in one machine cycle, it processes one instruction at a time.

FIG. 19 shows a flow for processing a load instruction and a store instruction continuously. When the load instruction is executed, the contents of the register pointed to by the S2 field of the first instruction register are transferred to the MAR 112 via the bus 128 in the R stage. Next, in the EX stage, the operand is fetched to the MDR 113 through the data cache 115. Finally, the operand fetched at the W stage is stored in the register pointed to by the destination field D of the first instruction register via the bus 134.

Next, when the store instruction is executed, in the R stage, the contents of the register pointed to by the first source register field S1 of the first instruction register are transferred as data to the MWR 114 through the bus 135. At the same time, the contents of the register pointed to by the second source register field S2 of the first instruction register are used as an address as the bus 128
Are transferred to the MAR 112 through the steps 131 and 131. Next, in the EX stage, the data in the MWR 114 is written to the address pointed to by the MAR 112. As shown in FIG. 19, even if a load instruction and a store instruction are successive, there is a capability of processing two instructions in one machine cycle, but one instruction can be processed.

FIG. 20 shows a processing flow when the unconditional jump BRA instruction is executed. When the BRA instruction is read, in the R stage, the sequencer 111 adds the displacement field d and the program counter, and sets the result in the latch 102 of the program counter. During this time, the instruction at the address next to the BRA instruction is read. In the next cycle, the instruction at the jump destination is read. In this embodiment, hardware capable of executing the instruction 1 is used. That is, a wait cycle does not occur during the jump instruction processing.

Although the case where the value of the processing state flag PE116 of the processor status register 103 is OFF has been described, in comparison with the case where the value of the processing state flag PE116 is ON, in this embodiment, the instructions 2 and 3 performed during the delayed branch are executed. Although it is no longer possible, one instruction can be executed during the address calculation of the jump instruction as in the conventional RISC type computer. As described above, the processing state flag PE116 of this embodiment is used.
When the value is OFF, there is an effect of maintaining compatibility with the related art. C
The same applies to the processing flow of the ALL instruction and the RTN instruction. The compiler generates a code so as to execute a valid instruction as much as possible during the calculation of the address of the branch instruction. However, when there is nothing to do, instruction 1 in FIG. 20 is set as a NOP instruction. At this time, a wait of substantially one machine cycle occurs.

FIG. 21 shows a processing flow of the conditional branch instruction BRAcc. With the instructions shown as ADD and F,
The flag is set, and the success or failure of the branch is determined according to the result. At this time, similarly to the unconditional branch instruction described with reference to FIG. 20, the instruction next to the address where the BRAcc instruction is located, that is, instruction 1 in FIG. 21 is read and processed. In the stage, the operation result is written to the register file regardless of whether the branch condition of the BRAcc instruction is satisfied or not.

As described above with reference to FIGS. 18 to 21, when the value of the processing state flag PE116 of the processor status register 103 is OFF, instructions are processed one instruction at a time to maintain compatibility with conventional software. There are advantages.

As described above, the embodiment of the processing means switching method based on the processing state flag having the advanced parallel processing means and the sequential processing means for maintaining the conventional software compatibility has been described. The sequential processing means of the present embodiment reads out one instruction at a time and executes it in the first arithmetic unit. However, as can be seen from FIG. 1B, since the two instruction registers 104 and 105 exist, the program counter is +2. The two instructions are read and stored in the first instruction register 104 and the second instruction register 105, and the instructions in the first instruction register 104 are executed by the first arithmetic unit 108, Subsequently, the present invention can also be realized by providing means for executing the instruction of the second instruction register 105 by the second arithmetic unit 109. That is, the instruction cache only needs to operate once every two times except for the branch instruction.

The operation of the "means for reading out and sequentially processing the m instructions" when the value of the processing state flag PE116 of the processor status register 103 is OFF will be described again with reference to FIG. 1B.

In the IF stage, two instructions pointed to by the program counter are read, and the bus 117,
Through 118, they are set in the first instruction register 104 and the second instruction register 105, respectively. When the PC is an even number, the instruction at the PC address is stored in the first instruction register by the PC +
The instruction at address 1 is stored in the second instruction register. Also,
When the PC is an odd number, the NOP instruction is set in the first instruction register, and the instruction at the PC address is set in the second instruction register. That is, the sequencer 111 is a circuit that controls the program counter. When neither the first instruction register nor the second instruction register is a branch instruction, the value of the previous program counter value + 2 is latched in the program counter.
Set to At the time of branching, the branch address is calculated and set in the program counter. At the time of conditional branch, the first
Based on the flag information 120 from the arithmetic unit 108 and the flag information 119 from the second arithmetic unit 109, the success or failure of the branch is determined, and the program counter arithmetic unit 101 is determined using the branch destination address information 121 and the branch control information 122.
Control. As will be described later, the instructions stored in the first instruction register and the second instruction register are sequentially processed in a later stage, so that the instruction cache is not operated for each machine cycle. The operation may be performed once in two machine cycles.

Next, the operation of the R stage during basic instruction processing will be described. In the R stage, the first instruction register 1
04 is decoded by the first instruction decoder 106,
Subsequently, in the next stage, the contents of the second instruction register 105 are decoded by the second instruction decoder 107. As a result, the contents of the register pointed to by the first source register field S1 of the first instruction register 104 are transferred via the bus 127, and the contents of the register pointed to by the second source register field S2 are transferred via the bus 128 to the first operation unit 108. Sent to Then, in the next stage, the contents of the register pointed to by the first source register field S1 of the second instruction register 105 are transferred through the bus 129.
The contents of the register pointed to by the second source register field S2 are sent to the second arithmetic unit 109 via the bus 130.

Next, the operation of the EX stage will be described.

In the EX stage, the first instruction register 10
4 according to the contents of the operation code of the first operation unit 108
, An operation is performed between the data transmitted by the buses 127 and 128. Subsequently, in the next stage, the operation between the data sent by the buses 129 and 130 is performed in the second operation unit 109 in accordance with the contents of the operation code of the second instruction register 105. Finally, the operation of the W stage will be described. In the W stage, the operation result of the first operation unit 108 is stored in the register pointed to by the destination field D of the first instruction register via the bus 131. In the next stage, the operation result of the second operation unit 109 is stored in the register pointed to by the destination field D of the second instruction register via the bus 132.

FIG. 22 shows a flow for continuously processing the basic instructions ADD. 2 per machine cycle
It has the ability to process instructions one by one, but it processes one instruction at a time. That is, two ADD instructions are fetched at the same time, but only the first ADD instruction executes the processing of the R stage. On the other hand, the second ADD instruction executes the processing of the R stage after waiting for one machine cycle. Here, FIG.
The upper one shows the processing of the first arithmetic unit and the lower one shows the processing of the second arithmetic unit.

FIG. 23 shows a flow for processing load instructions and store instructions successively. When the load instruction is executed, the contents of the register pointed to by the S2 field of the first instruction register are transferred to the MAR 112 via the bus 128 in the R stage. Next, in the EX stage, the operand is fetched from the data cache through the bus 133. Finally, the operand fetched at the W stage is stored in the register pointed to by the destination field D of the first instruction register via the bus 134. Fetching an operand in one machine cycle in the EX stage is possible if the high-speed data cache 115 is provided as shown in FIG. 1A.

Next, in the execution of the store instruction, after the execution of the R stage of the load instruction, the contents of the register pointed to by the second source register field S1 of the second instruction register are transferred to the MWR 114 through the bus 135 as data in the R stage. You. At the same time, the contents of the register pointed to by the second source register field S2 of the second instruction register are transferred to the MAR 112 via the bus 129 as an address. Next, at the EX stage, the MW is
The data in R114 is written. As shown in FIG.
Even if load and store instructions are consecutive, it has the ability to process two instructions in one machine cycle.
Instructions can be processed one by one.

FIGS. 24 to 27 show the unconditional jump BR.
It shows a processing flow when an A instruction and an instruction 1 at a subsequent address are executed. In particular, FIGS. 24 and 25 show a pipeline processing flow when an unconditional jump BRA instruction exists in the first instruction, and FIGS. 26 and 27 show a pipeline processing flow when an unconditional jump BRA instruction exists in the second instruction. FIG. 26 shows the case where the jump destination instruction is at the address corresponding to the first instruction, and FIGS. 25 and 27 show the case where the jump destination instruction is at the address corresponding to the second instruction. When the BRA instruction is read from the instruction register, the sequencer 111 adds the displacement field d and the program counter in the R stage and sets the result in the latch 102 of the program counter. During this time, the instruction at the address next to the BRA instruction is executed in the next cycle. Then, in the next next cycle, the two instructions at the jump destination are read. Here, when the unconditional jump BRA instruction is included in the second instruction (see FIGS. 26 and 2)
7), two instructions including the instruction at the address next to the BRA instruction are IF
At the stage, the instruction is read from the instruction cache, but the first instruction is executed, but the second instruction is not executed, but the jump destination instruction is controlled to be executed. That is, even if instructions following the instruction following the branch instruction are held in the instruction register, they are invalidated without being executed.

When the jump destination instruction is at an address corresponding to the second instruction (FIGS. 25 and 27), two instructions including the jump destination instruction are read from the instruction cache at the IF stage. Is controlled so that only the second instruction at the jump destination is executed without being executed. That is, even if instructions before the jump destination instruction are held in the instruction register, they are invalidated without being executed.
The same applies to the processing flow of the CALL instruction and the RTN instruction.

FIGS. 28 to 31 show a conditional branch instruction BRA.
It shows a processing flow when the cc instruction and instruction 1 are executed. Here, FIGS. 30 and 31 are processing flows when a conditional branch instruction BRAcc instruction is present in the first instruction, and FIGS. 28 and 29 are processing flows when a conditional branch instruction BRAcc instruction is present in the second instruction.
8 and 30 show the processing flow when the jump destination instruction is at the address corresponding to the first instruction, and FIGS. 29 and 31 are the processing flows when the jump destination instruction is at the address corresponding to the second instruction. FIG.
In FIGS. 8 to 31, flags are set by instructions ADD and F, and the success or failure of the branch is determined according to the result.
At this time, the instruction 1 next to the address located in the BRAcc instruction is executed similarly to the processing of the unconditional branch instruction described with reference to FIGS.
In the stage, the operation result is written to the register file regardless of whether the branch condition of the BRAcc instruction is satisfied.

As shown in FIGS. 30 and 31, the BRA instruction is
If the instruction exists, when the BRAcc instruction is read from the instruction register, the sequencer 111 adds the displacement field d and the program counter in the R stage, sets the result in the program counter latch 102, and sets the operand of the instruction 1 Is processed in parallel. During this time, the instruction at the address next to instruction 1 is executed in the next cycle. Then, in the next next cycle, the two instructions at the jump destination are read.

On the other hand, the conditional branch instruction BRAcc
When there is an instruction (FIGS. 28 and 29), two instructions including the instruction at the address next to the BRAcc instruction are read from the instruction cache at the IF stage, but the first instruction is executed but the second instruction is not executed. It is controlled to execute the jump destination instruction. In other words, even if instructions following the instruction following the conditional branch instruction are held in the instruction register, they are invalidated without being executed when the condition is satisfied.

Further, when the conditional branch instruction is executed and the condition is satisfied, a jump is made. When the jump destination instruction is at an address corresponding to the second instruction (FIGS. 29 and 31), two instructions including the jump destination instruction are read from the instruction cache at the IF stage, but the first instruction is not executed and the second instruction is not executed. Is controlled to execute the jump destination instruction. That is, even if instructions before the jump destination instruction are held in the instruction register, they are invalidated without being executed.

The operation of "means for simultaneously reading out m instructions and sequentially processing them by m arithmetic units" has been described. As a result, the program counter is controlled to be incremented by +2, and the first Instruction register 104, and
The two instructions are read and stored in the second instruction register 105, the instruction in the first instruction register 104 is executed by the first operation unit 108, and the instruction in the second instruction register 105 is subsequently executed by the second operation unit 109. This is to provide means for executing (sequential processing). As a result, the instruction cache only needs to operate once every two times except for the branch instruction. The embodiment of the processing means switching method based on the processing state flag having the high-speed parallel processing means and the sequential processing means for maintaining the conventional software compatibility has been described. However, when the value of the processing state flag PE116 of the processor status register 103 in FIG. 1A is ON, the parallel execution processing means of this embodiment processes two instructions at a time in one machine cycle. Although improved, as shown in FIGS. 14 to 17, the compatibility with the conventional software is lost due to the extension of the delayed branch instruction. Therefore, a method for maintaining the compatibility of most software by providing a control means for executing only one instruction following the delayed branch instruction will be described. FIG. 1C is obtained by adding a control signal line 147 to FIG. 1B. That is,
When the delayed branch instruction is decoded by the second instruction decoder 107, the subsequent delay slot instruction exists in the first instruction register 104. However, the instruction held in the second instruction register 105 is an instruction that must not be executed. Therefore, when the second instruction decoder 107 detects a delayed branch instruction, it invalidates the contents of the second instruction register 105 via the control signal line 147, thereby executing only one instruction subsequent to the delayed branch instruction.

When the first instruction decoder 106 is decoding the delayed branch instruction, the subsequent delay slot instruction is being decoded by the second instruction decoder 107,
There is no problem with parallel execution. As described above, the control signal line 1
By using 47 to invalidate the contents of the second instruction register 105, compatibility of most software can be maintained.

Next, a description will be given of an embodiment of a "method capable of correctly executing most conventional software" based on the fact that parallel processing is always performed without using a processing state flag.

In this embodiment, the processing excluding the branch instruction is basically performed two instructions at a time, and the branch instruction executes only the next succeeding instruction (only instruction 1 in FIGS. 14B to 17). The execution of the remaining instructions is to provide means for inhibiting.

FIG. 14A shows a configuration based on always performing parallel processing. That is, the program counter calculator 101 always adds +2 (143). However, the compatibility of software can be maintained by invalidating the contents of the second instruction register 105 using the control signal line 147. The operation of the configuration shown in FIG. 14A will be described below with reference to FIGS. 14B to 17. FIG. 14B
Is used for the embodiment described above.

FIG. 14B shows a processing flow when the unconditional jump BRA instruction is executed as the second instruction.
When the BRA instruction is read, in the R stage, the sequencer 111 adds the displacement field d and the program counter, and sets the result in the latch 102 of the program counter. During this time, the instructions 1 and 2 at the addresses following the BRA instruction are read, and in the next cycle, the two instructions at the jump destination are read. In this embodiment, only the instruction 1 is executed, and the execution of the instruction 2 is suppressed. In other words, control is performed so that only one instruction following the branch instruction BRA can be executed in order to achieve compatibility with conventional software. That is, the instruction 2 in FIG. 14B is controlled by the second instruction decoder 107 in FIG. 14A via the signal line 147 so that processing equivalent to the NOP instruction is performed, or the writing of the second instruction to the register file is performed. It becomes possible by controlling to suppress. The compiler generates a code so that an instruction as effective as possible can be executed during the calculation of the address of the branch instruction, but when there is nothing to do, instruction 1 in FIG. 14B is set as a NOP instruction. At this time, a wait of substantially one machine cycle occurs.

FIG. 15 shows a conditional branch instruction B as a second instruction.
It shows a processing flow when the RAcc instruction is executed.
Flags are set by instructions ADD and F,
The success or failure of the branch is determined according to the result. Again,
Similar to the unconditional branch instruction described with reference to FIG.
The instruction next to the address located in the Acc instruction, that is, instruction 1 and instruction 2 in FIG. 15 are read out, and in the W stage during the processing flow of instruction 1, the operation result of the BRAcc instruction is obtained regardless of whether the branch condition is satisfied or not. Writing to the register file is performed, while execution of instruction 2 is suppressed. That is, the instruction 2 in FIG. 15 is controlled by the second instruction decoder 107 in FIG. 14A so as to perform processing equivalent to the NOP instruction, or is controlled so as to suppress the writing of the second instruction to the register file. This is possible. At this time, a wait of substantially one machine cycle occurs.

FIG. 16 shows a processing flow when the unconditional jump BRA instruction is executed as the first instruction. When the BRA instruction and the instruction 1 are read, the sequencer 111 adds the displacement field d and the program counter in the R stage, sets the addition in the program counter latch 102, and
Read the operand of instruction 1. During this time, the next instruction 2
And instruction 3 are read. And in the next cycle,
Instructions 1 and 2 at the jump destination are read. However, for compatibility with the conventional software, the branch instruction BRA instruction and the instruction 1 are executed in parallel, but the execution of the instructions 2 and 3 is suppressed. That is, the instruction 2 and the instruction 3 in FIG.
6. It can be realized by controlling the second instruction decoder 107 to perform processing equivalent to the NOP instruction, or by controlling the writing of the second instruction and the third instruction to the register file. The compiler generates code so that the most effective instruction can be executed during the address calculation of the branch instruction.
The instruction 1 of No. 6 is set as a NOP instruction. At this time, a wait of substantially one machine cycle occurs.

FIG. 17 shows a conditional branch instruction B as the first instruction.
It shows a processing flow when the RAcc instruction is executed.
Instructions indicated by ADD and F set a branch state flag, and determine the success or failure of the branch according to the result. At this time, similarly to the unconditional branch instruction described with reference to FIG. 16, the BRAcc instruction and the instruction 1 at the subsequent address are simultaneously read out.
The operation result is written to the register file regardless of whether the branch condition of the RAcc instruction is satisfied or not. Further, the instruction 2 and the instruction 3 in FIG. 17 are controlled so that the first instruction decoder 106 and the second instruction decoder 107 in FIG. 14A perform processing equivalent to the NOP instruction, or the second instruction and the third instruction Or if the branch instruction is the first instruction, control is performed such that the instruction 1 is executed in parallel and then branched to the jump destination instruction 1. .

The operation of the method for enabling normal execution of most of the software and increasing the speed by parallel execution has been described with reference to FIG. 14A. As a result, the instruction 2 and the instruction 2 in FIGS. That is, the execution of the instructions 2 and 3 in FIGS. 16 and 17 is suppressed. This makes it possible to maintain the compatibility of the conventional delayed branch method that effectively uses one wait cycle, and that other instructions can be basically executed in parallel with two instructions. And the effect of improving processing performance between 1 and 2 times.

Although the parallel execution processing means has been described centering on the branch instruction, it is needless to say that both instructions may not be executed at the same time depending on the combination of the first instruction and the second instruction. This is called a conflict. The conflict is described below.

1. Combination of load and store instructions.

2. The register indicated by the destination register field D of the first instruction and the register indicated by the first source register field S1 of the second instruction or the register indicated by the second source register field S2 of the second instruction are When they match.

At the time of the above competition, Is a problem peculiar to this embodiment caused by the inability to simultaneously access the data cache from a plurality of instructions. For example, the problem can be solved by forming the data cache into two ports. Also, 2. 14A, the first instruction decoder and the second instruction decoder of FIG. 14A compare the source register field and the destination register field with each other, and if they match, change the second instruction to a NOP instruction. it can. That is, when the register specified by the destination register field D of the first instruction matches the register specified by the two source register fields of the second instruction, the second instruction is changed to the NOP instruction and the first instruction is changed to the NOP instruction. In the next cycle, this can be achieved by changing the first instruction to a NOP instruction and executing the NOP instruction and the second instruction in parallel.

The contention problem during parallel execution has been described above.

Although all the embodiments of the present invention have been described in the case where two instruction decoders and two arithmetic units are provided, there is no problem even if the number is increased to four or eight.

The last embodiment of the present invention will be described. This is for the processing state flag PE116 of the processor status register 103 in FIG. 1C. Originally, the processing state flag PE116 is a switchable means as an information source for performing hardware switching in a system that requires compatibility with conventional software, and that is switched by an instruction for switching. Met.

However, in a dedicated system or a system that only needs to execute new software to be created, only one of the functions may be used when assembling the system. Therefore, it is necessary to provide a data processing device with both parallel execution processing means and sequential execution processing means, and to incorporate only one means according to the system to be built. As one means for realizing this function, there is a means for setting the processing status flag PE116 of the processor status register 103 to any one of the instructions at the time of initialization and at the time of reset. In the case of an LSI such as a microprocessor, there is also a selecting means for switching between the above two means by using a pin for exchanging signals between the LSI and the outside. The pins extend from the LSI as is well known.

[0086]

According to the present invention, all software operating on a conventional sequential processing type computer can be operated normally, and can be executed at a higher speed by using an advanced parallel processing function. You can save time.

Further, most conventional software can be operated normally, and can be executed at higher speed by using advanced parallel processing functions.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing one embodiment of the present invention.

FIG. 2 is an overall block diagram of a conventional example.

FIG. 3 is a timing chart for explaining the operation of the configuration shown in FIG. 2;

FIG. 4 is a timing chart for explaining the operation of the configuration shown in FIG. 2;

FIG. 5 is a timing chart for explaining the operation of the configuration shown in FIG. 2;

FIG. 6 is an overall block diagram of another conventional example.

FIG. 7 is a timing chart for explaining the operation of the configuration shown in FIG. 6;

FIG. 8 is a timing chart for explaining the operation of the configuration shown in FIG. 6;

FIG. 9 is a flowchart of a delayed branch instruction processing of the RISC type computer.

FIG. 10 is a diagram showing a list of instructions according to the present invention.

FIG. 11 is a diagram showing an instruction format of the present invention.

FIG. 12 is a timing chart illustrating an operation in parallel processing according to the present invention.

FIG. 13 is a timing chart illustrating an operation in parallel processing according to the present invention.

FIG. 14 is a timing chart illustrating an operation in parallel processing.

FIG. 15 is a timing chart illustrating an operation in parallel processing.

FIG. 16 is a timing chart illustrating an operation in parallel processing.

FIG. 17 is a timing chart illustrating an operation in parallel processing.

FIG. 18 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 19 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 20 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 21 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 22 is a timing chart illustrating an operation in the sequential processing of the present invention.

FIG. 23 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 24 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 25 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 26 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 27 is a timing chart illustrating the operation in the sequential processing of the present invention.

FIG. 28 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 29 is a timing chart illustrating the operation in the sequential processing of the present invention.

FIG. 30 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 31 is a timing chart for explaining the operation in the sequential processing of the present invention.

FIG. 32 is an overall block diagram showing another embodiment of the present invention.

FIG. 33 is an overall block diagram showing another embodiment of the present invention.

FIG. 34 is an overall block diagram showing another embodiment of the present invention.

[Explanation of symbols]

103: processor status register, 104: first
Instruction register, 105: second instruction register, 106: first instruction decoder, 107: second instruction decoder, 108 ...
1st arithmetic unit, 109 ... 2nd arithmetic unit, 110
... Register file.

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Tadaaki Bando 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.

Claims (3)

[Claims] A program counter for designating an instruction to be read from a memory; a plurality of instruction registers for respectively storing instructions designated by the program counter; and a plurality of instruction registers for decoding instructions stored in the instruction register. A parallel processing device, comprising: a decoder; and a plurality of operation units for executing an operation, wherein at least one of the decoders invalidates the contents of the instruction register by decoding an instruction. 2. The parallel processing device according to claim 1, wherein said program counter, said plurality of instruction registers, said plurality of decoders, and said plurality of operation units are formed on the same semiconductor substrate. Parallel processing device. 3. The parallel processing device according to claim 1, wherein said parallel processing device further controls a processing state of operating the plurality of arithmetic units in parallel or sequentially. A parallel processing device having control means.