JPH1079876A - Automatic program sending-out system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate variance in process time between video equipments and a video switches and time the control processes of the both to each other by providing a circuit which adjusts timing, so that control output which is synchronized with a vertical synchronizing signal is enabled. SOLUTION: This system is provided with a clock-generating circuit 305 which generates a clock signal 400 shifted by nearly a half out of phase with the vertical synchronizing signal 200 and shift registers 341-34n and 351-35n which output a control signal to the video switch and a control signal to the video equipment, outputted in synchronism with second pulses, with delays corresponding to the numbers of clocks set previously with switches 361-36n and 371-37n. The control signal to the video switch and the control signal to the video equipment are adjusted in output timing so as to match the switching of the video switch to the transmission of video of the video equipment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic program transmission system, and more particularly to a program transmission system for automatically transmitting a television broadcast program.

[0002]

2. Description of the Related Art Generally, an automatic program transmission system controls a television set by controlling various video equipments containing program materials and a video switch for selecting an output video of these video equipments, based on pre-registered program scheduling data. Broadcast program transmission is performed automatically.

In a conventional automatic program transmission system,
Various video devices for transmitting program material of television broadcasting and a video switch for selecting output video of a plurality of video devices are time-controlled in units of seconds.

FIG. 5 is a block diagram showing a configuration example of a conventional automatic program transmission system.

In FIG. 1, n video devices 131 to 1
3n operates in synchronization with the vertical synchronizing signal 200, and the video output of these video devices 131 to 13n is controlled by the video switch 103 to obtain the output video 300. Automatic program transmission device (APS: automatic
program control system) 1
02 is the switching control signal 1 at the timing synchronized with the second pulse 100 from the clock device 101 based on the program data.
11-11n and device control signals 121-12n are output to control the video switch 103 and the video devices 131-13n.

In such a configuration, at present, the image switch 1
It is assumed that the output video of the video device 131 is selected by 03 and the output video of the video device 132 is switched. At this time, the video switch 103
Switching is performed at a blanking timing after V (1 V is a time corresponding to one cycle of the vertical synchronization signal), and the video device 132 transmits video at a blanking timing after 4 V after being controlled.

In this case, as shown in FIG. 6, which is a time chart showing the operation of the automatic program transmission system shown in FIG. 5, the APS 102 outputs the video switch 103 and the video equipment at a control time based on the program data. 132, a switching control signal 112 and a device control signal 122 are output, respectively. Then, the video device 132 takes 2 V from the control of the video switch 103 until the process is completed after receiving the control.
For a long time, in the time between time t1 and time t2,
Unnecessary video is output from the video switch 103 at 2V.

That is, the control signals output from the APS 102 are not synchronized with the vertical synchronizing signal 200, and the phase at which the blanking timing is output is not determined. Therefore, when the control signal is output at a time very close to the blanking timing, the internal processing of the video switch 103 and each video device cannot be made in time, and the control process is performed at 1 V (1/60 [T] = 16.7). [Ms]) There is a possibility of being delayed.

Here, the conventional program transmitting apparatus is disclosed in
248776. This device is a video adjusting device that selects one of a plurality of input material video signals by pressing a selection button, switches the output, and outputs the selected one. And a plurality of delay circuits for providing a preset delay time to each of the plurality of material video signals, and selectively switching one of the material video signals output from the plurality of delay circuits in accordance with the switching signal. And a switching control circuit that generates and outputs a switching signal in response to pressing of a selection button provided corresponding to a plurality of material video signals. The delay time of the delay circuit is set to a time from when the selection button is pressed to when the switching circuit switches and outputs the corresponding material video signal.

In such a video adjusting apparatus, a delay circuit is provided for each of a plurality of input material video signals, and after a selection button corresponding to each material video signal is pressed, the video switching circuit outputs the corresponding material video signal. A delay time equal to the time until switching and outputting is given to each material video signal. Thereby, the corresponding material video signal can be switched and output at a timing coincident with the material video signal at the time when one of the plurality of material video signals input by the operator and the selection button is pressed down. Thus, the adjustment result intended by the operator is obtained.

[0011]

In the above-described conventional automatic program transmission system, the processing time from when the video equipment is controlled to when the video is transmitted and the selection switching is completed after the video switch receives the control. Therefore, it is difficult to match these timings. The timing at which the video equipment sends out the video and the timing at which the video switch switches the video are performed at the blanking timing on the video signal, but the timing at which the automatic program transmission system outputs the control is synchronized with the blanking timing. Not.

For this reason, when the control signal is output at a time very close to the blanking timing, there is a disadvantage that the internal processing of the video switch or the video equipment may not be in time and the control processing may be delayed by 1V. there were.

Further, in the conventional apparatus described in the above-mentioned publication, the operator monitors a plurality of material images which are transmitted in a fluid manner, and intuitively captures the material image thought "here" and presses a selection button. Press to switch. Therefore, the switching timing is left to the judgment of the material video and the operator, and there is a disadvantage that the material video cannot be switched in real time based on the program data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to provide a circuit for adjusting timing so as to enable a control output synchronized with a vertical synchronizing signal. It is an object of the present invention to provide an automatic program transmission system capable of eliminating the variation in the processing time between a video switch and a video switch, and adjusting the control processing timing of both.

[0015]

An automatic program transmission system according to the present invention comprises a plurality of program transmission means for transmitting a program in response to an enable signal input at a timing corresponding to a time at which a program is to be transmitted. An output switching means for selectively transmitting a program transmitted from a plurality of program transmission means, wherein the automatic signal transmission system is provided for each of the plurality of program transmission means, and the enable signal is provided for a predetermined time. It is characterized by including a plurality of delay means for delaying and inputting to a corresponding program transmission means.

In this automatic program transmission system, a clock generation circuit for generating a clock signal whose phase is shifted from the vertical synchronization signal by approximately 1/2, and a control signal to a video switch output in synchronization with the second pulse And a shift register that delays a control signal to the video device by the number of clocks set in advance by a switch and outputs the shift signal. By doing so, the output timing of the control signal to the video switch and the output timing of the control signal to the video device are adjusted, and the timing at which the video switch is switched and the timing at which the video device sends out the video coincide.

Further, since the phase of the clock signal of the shift register is shifted from the phase of the vertical synchronizing signal by approximately 周期 cycle, the control signal is always output at an intermediate timing between adjacent blanking timings. Therefore, even when the control signal is output at a time very close to the blanking timing, there is no delay in the control processing by 1 V due to the internal processing of the video switch or the video equipment not being in time.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an automatic program transmission system according to the present invention, and the same parts as those in FIG. 5 are denoted by the same reference numerals.

In this figure, in the present system, the vertical synchronizing signal fetched from the vertical synchronizing signal
A clock generation circuit 305 for generating a clock signal 400 shifted by two phases;
From 02, the switching control signals 311 to 31n and the device control signals 321 to 32n output in synchronization with the second pulse 100 of the clock device 101 are provided in correspondence with the switching control signals 311 to 32n, and the control signals are delayed by a preset number of clocks and output. It comprises shift registers 341-34n and 351-35n. Further, the present system includes a shift register 34.
Switches 361-3 for setting the number of clocks for delaying the control signal in 1-34 n and 351-35 n
6n and 371 to 37n.

In such a configuration, at present, the video switch 1
It is assumed that the output video of the video device 131 is selected by 03 and the output video of the video device 132 is switched. At this time, the video switch 103
Switching at blanking timing after V
Reference numeral 2 denotes that video is transmitted at a blanking timing of 4 V after receiving the control.

In this case, as shown in FIG. 2 which is a time chart showing the operation of the automatic program transmission system in FIG. 1, the APS 302 sends the video switch 103 and the video switch 103 one second before the actual control time. A switching control signal 312 and a device control signal 322 are output to the device 132, respectively. Such output one second before is output to the AP based on the programming data.
By registering in advance in S, it is realized by software control inside the APS. The output is made one second before because the maximum time of the shift operation of each shift register is considered. If a shift register capable of performing a shift operation for a longer time is provided, it is possible to output even earlier than the control time.

Switching control signal 312, device control signal 322
The shift registers 342 and 352 receiving the switch 3
The control signals 328 and 392 are output after being delayed by the number of clocks set in 62 and 372.

In this case, if the switches 362 and 372 are set so that the shift register 342 delays the output of 57 clocks and the shift register 352 delays the output of 55 clocks, the video switching device and the video device can have the same blanking timing (time Switching can be performed at t3).

In the time chart of FIG. 2, the phase of the clock signal 400 with respect to the vertical
/ 2 cycles, and the control signal is always output in the middle of the adjacent blanking timing. Therefore, even when the control signal is output at a time very close to the blanking timing, the internal processing of the video switching device or the video device cannot be delayed and the control process is not delayed by 1V.

Here, each shift register 341 in FIG.
The configuration of to 34n and 351 to 35n will be described with reference to FIG.

As shown in FIG. 3A, a shift register 3 capable of externally setting the number of shifts is used for each shift register in FIG. That is, the shift register 3 is provided with terminals L1 to L6 for setting the number of shifts, and the levels of these terminals L1 to L6 are controlled by the corresponding switches 4. In the figure,
Only the switch corresponding to the terminal L2 is closed to set the terminal to the low level. Thus, a shift register with two clock shifts can be realized. Note that the shift register 3 is provided with an input terminal IN and an output terminal OUT.

According to such a configuration, as shown in FIG. 2B, the input from the input terminal IN to the output terminal OU
The time from T to the output is 2 clocks or more and less than 3 clocks. That is, the output from the output terminal OUT rises approximately two clocks after the input to the input terminal IN rises. If a switch corresponding to another terminal is closed, a shift register with an arbitrary clock shift can be realized.

As described above, each of the shift registers 341 to 341
Switches 361 to 3n corresponding to 4n and 351 to 35n
For 6n and 371 to 37n, an appropriate number of clocks is determined in advance according to the internal control processing time of the video devices 131 to 13n.

Next, the configuration of the clock generation circuit 305 will be described with reference to FIG. As shown in FIG. 1A, a clock generation circuit 3 is programmed using a programmable pulse generator 5 having a reset terminal (RESET).
05. In this case, one cycle of the clock signal 400 is set to one by setting the control terminals CTL1 to CTL6 of the pulse generator 5 to high level or low level.
Set to 6.7 [ms] (repetition frequency 60 [Hz]).

The vertical synchronizing signal 200 is input to the reset terminal via the inverting circuit 6. Thus, the clock signal 40 is output at the falling timing of the vertical synchronization signal 200.
This means that the clock signal 400 is calibrated by resetting 0.

According to this configuration, as shown in FIG. 2B, the vertical synchronization signal 200 is input to the reset terminal, and the clock signal 400 is reset at the falling timing of the vertical synchronization signal 200. , The clock signal 400 is calibrated. Further, even if the vertical synchronization signal is interrupted, the clock signal 400 runs on its own.

In short, the control by the conventional device can only perform the control output in units of seconds and cannot finely control the timing of the video switch and the video equipment. However, in this device, the control output timing adjustment circuit synchronized with the vertical synchronizing signal Is provided, the adjustment can be performed in units of one cycle of the vertical synchronization signal, that is, in units of 1V.

The present invention can take the following aspects in connection with the description of the claims.

(4) Each of the plurality of delay means is a shift register that performs a shift operation of a predetermined number of stages in synchronization with the second synchronization signal. Program transmission system.

(5) The automatic program transmission system according to claim 3 or 4, wherein the program is a video program, and the first synchronization signal is a vertical synchronization signal.

[0037]

As described above, the present invention provides a clock generation circuit for generating a clock signal whose phase is shifted by approximately 1/2 with respect to a vertical synchronization signal, and a video switch which is output in synchronization with a second pulse. And a shift register that delays the control signal to the video device and the control signal to the video device by the number of clocks set in advance by a switch, and outputs the control signal to the video switch and the output timing of the control signal to the video device. This makes it possible to adjust the timing at which the video switch is switched and the timing at which the video device transmits the video.

Also, by shifting the phase of the clock signal of the shift register by approximately 1/2 cycle with respect to the phase of the vertical synchronizing signal, the control signal is always output at an intermediate timing between adjacent blanking timings. Also, even when the control signal is output at a time very close to the blanking timing, there is an effect that the control processing is not delayed because the internal processing of the video switch or the video equipment is not in time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an automatic program transmission system according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation of the automatic program transmission system of FIG. 1;

3A is a block diagram illustrating a configuration example of each shift register in FIG. 1, and FIG. 3B is a time chart illustrating an operation of each unit in FIG.

4A is a block diagram illustrating an example of a configuration of a clock generation circuit in FIG. 1, and FIG. 4B is a time chart illustrating an operation of each unit in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional automatic program transmission system.

FIG. 6 is a time chart showing the operation of the automatic program transmission system of FIG.

[Explanation of symbols]

 102, 302 APS 103 Video switch 104 Vertical synchronization signal generator 131-13n Video equipment 305 Clock generation circuit 341-34n, 351-35n Shift register 361-36n, 371-37n Switch

Claims (3)

[Claims] 1. A plurality of program transmitting means for transmitting a program in response to an enable signal input at a timing corresponding to a time at which a program is to be transmitted, and a program transmitted from the plurality of program transmitting means is selected. And an output switching means for transmitting the enable signal, wherein the plurality of program transmission means are provided in correspondence with each of the plurality of program transmission means and delay the enable signal by a predetermined time and input the enable signal to the corresponding program transmission means. An automatic program transmission system comprising delay means. 2. The method according to claim 1, wherein the predetermined time delayed by the delay unit is:
2. The automatic program transmission system according to claim 1, wherein the automatic program transmission system is set in advance according to a processing time from an enable signal input timing to a program transmission timing in the program transmission means corresponding to the delay means. 3. The plurality of program transmission units transmits a program in synchronization with a first synchronization signal, and the plurality of delay units include a first synchronization signal having a phase that differs from the first synchronization signal by a substantially half period. 2
3. The automatic program transmission system according to claim 1, wherein said enable signal is input to a corresponding program transmission means in synchronization with said synchronization signal.