JPH1079518A - Tunnel transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in element characteristics by reducing residual impurities due to processing of a jointing surface of a drain layer and a channel layer for forming an inter-band tunnel joint. SOLUTION: On a substrate 1 having a step, drain layers 2, insulatian layers 3, channel layers 4 and gate insulation layers 5 are laminated, respectively, and the drain layer 2 and the channel layer 4 are jointed to each other, so that an inter-band tunnel joint is farmed in the jointing surface. At this time, the step of the substrate 1 and the thickness of the insulation layers 3 are so set that the drain layer 2 among the drain layers 2, which is formed on the higher part because of step of the substrate 1, and the channel layer 4 among the channel layers 4, which is formed on the lower part because of the step of the substrate 1, so as to contact each other at the side surfaces.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a transistor utilizing a tunnel phenomenon, which can be highly integrated and multifunctional, and a method of manufacturing the transistor.

[0002]

2. Description of the Related Art Conventionally, p ⁺ -n ⁺
A tunnel transistor has been proposed as a transistor which can be highly integrated and multifunctional by utilizing a tunnel phenomenon at a junction.

[0003] The present applicant has disclosed, for example, Japanese Patent Application Laid-Open No. 8-1862.
No. 73 proposes a tunnel transistor which can configure a functional circuit with a small number of elements and enables high integration.

FIG. 3 is a schematic structural view showing an example of a conventional tunnel transistor.

In this conventional example, as shown in FIG.
a substrate made of aAs and a drain layer 1 made of degenerated p ⁺ -GaAs formed on a part of the substrate 101
02 and i-G formed on a part of the drain layer 102.
an insulating layer 103 of aAs, a portion of the substrate 101 where the drain layer 102 is not formed, a channel layer 104 of degenerated n ⁺ -GaAs formed on the insulating layer 103, and a portion of the channel layer 104 I- formed in
A gate insulating layer 105 of Al _0.3 Ga _0.7 As, a gate electrode 106 of an Al film formed on the gate insulating layer 105, and a part of a part of the drain layer 102 where the insulating layer 103 is not formed. AuZn / Au
A drain electrode 107 made of a film and a source electrode 108 made of an AuGe / Au film formed on a part of the channel layer 104 where the gate insulating layer 105 is not formed. Here, i described above is an abbreviation that means a non-doped semiconductor that can be regarded as intrinsic or substantially intrinsic.

Hereinafter, the operation of the tunnel transistor configured as described above will be described.

The source electrode 108 is used as a ground electrode, and a voltage is applied between the source and the drain.

Then, the channel layer 104 and the drain layer 1
A junction (tunnel junction) similar to the Ezaki diode (tunnel diode) is formed at the portion where the contact is made with 02, and as a result, a tunnel current flows between the source and the drain due to a tunnel effect.

In particular, when a positive voltage is applied to the drain electrode 107, the Esaki diode becomes forward-biased, so that a differential negative resistance appears in its current-voltage characteristics. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the channel, this differential negative resistance characteristic is controlled by the voltage applied to the gate electrode 106, and the operation of the transistor having the function is reduced. can get.

Hereinafter, a method for manufacturing the above-described tunnel transistor will be described.

First, the temperature of the substrate 101 is set to 520 ° C., and a 20 nm-thick p ⁺ -GaAs drain layer 102 (concentration of 5 nm) is formed on the substrate 101 by molecular beam epitaxy (hereinafter referred to as MBE). × 10 ¹⁹ cm ^-3 Be
Is formed as a dopant), and an insulating layer 103 made of i-GaAs having a thickness of 30 nm is formed on a part of the drain layer 102.

Next, the drain layer 102 other than the portion to be the drain region is removed.

Next, a channel layer 10 made of n ⁺ -GaAs having a thickness of 12 nm is formed on the portion of the substrate 1 where the drain layer 102 is not formed and on the insulating layer 103 by MBE.
4 (containing 1 × 10 ¹⁹ cm ⁻³ of Si as a dopant), and a 20 nm thick i-Al
_The gate insulating layers 105 made of _0.3 Ga _0.7 As are regrown.

At this time, an interband tunnel junction is formed on the exposed side surface of the drain layer 102.

Next, on the gate insulating layer 105, a thickness of 50
nm Al film is deposited, and the Al film and the gate insulating film 10 are deposited.
By processing No. 5, a gate electrode 106 is formed.

Thereafter, AuZn /
A drain electrode 107 made of Au and a source electrode 108 made of an AuGe / Au multilayer film are formed.

[0017]

However, in the above-described conventional tunnel transistor, the junction between the drain layer and the channel layer for forming the band-to-band tunnel junction is formed after the drain layer is processed. Is formed by regrowth, there is a possibility that residual impurities may be present at the time of processing the drain layer at the junction surface, and the element characteristics may be degraded.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has been made to reduce the amount of residual impurities at a junction surface where a band-to-band tunnel junction is formed, and to improve device characteristics. An object is to provide an excellent tunnel transistor.

[0019]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a first semiconductor layer made of a semiconductor having a first conductivity on a substrate having a gap; A first insulating layer, a second semiconductor layer having a conductivity different from that of the first semiconductor layer, and a second semiconductor layer having an insulating property.
And a drain electrode formed on a first semiconductor layer formed in a portion of the first semiconductor layer which is higher due to the difference in the substrate, and a second semiconductor layer. A tunnel transistor, comprising: a source electrode formed on a second semiconductor layer formed in a portion lowered by a difference in the substrate; and a gate electrode formed on the second insulating layer. And a first semiconductor layer formed in a portion of the first semiconductor layer which is higher due to the difference in the substrate and a second semiconductor layer formed in a portion of the second semiconductor layer which is lower due to the difference in the substrate. And the second semiconductor layer is in contact with each other on the side surfaces.

Further, a second semiconductor layer made of a semiconductor having a second conductivity, an insulating layer having an insulating property, and a conductive property different from that of the second semiconductor layer are formed on the substrate having the difference. A first semiconductor layer comprising: a gate electrode formed on a first semiconductor layer formed in a portion of the first semiconductor layer which is higher due to the difference in the substrate; A drain electrode formed on the first semiconductor layer formed in a portion of the first semiconductor layer which is lowered due to the difference between the substrates, and a drain electrode formed on the second semiconductor layer which becomes higher due to the difference between the substrates; And a source electrode formed on a second semiconductor layer formed in a portion of the first semiconductor layer, the tunnel transistor being formed in a portion of the first semiconductor layer which becomes lower due to a difference in the substrate. A first semiconductor layer and the second semiconductor A second semiconductor layer is characterized in that in contact with the side surface of another formed becomes higher portion by the cross-sectional difference between the substrate of the.

A step of forming a first semiconductor layer having a first conductivity on a substrate having a gap; and a step of forming a first insulating layer having an insulating property on the first semiconductor layer. Forming a second semiconductor layer having a conductivity different from that of the first semiconductor layer on the first insulating layer; and forming a second insulating layer having an insulating property on the second semiconductor layer. A step of forming a layer, a step of forming a gate electrode on the second insulating layer, and a step of forming a gate electrode on the first semiconductor layer formed in a portion of the first semiconductor layer which is higher due to a difference between the substrates. Forming a drain electrode on the second semiconductor layer, and forming a source electrode on a second semiconductor layer formed on a portion of the second semiconductor layer which is lower due to the difference in the substrate, and By joining the first semiconductor layer and the second semiconductor layer A method of manufacturing a tunnel transistor for forming an inter-band tunnel junction at the junction surface, wherein the first semiconductor layer formed in a portion of the first semiconductor layer which is higher due to the difference in the substrate and the second semiconductor layer are formed. And the thickness of the first insulating layer are set such that the second semiconductor layer formed in a portion of the semiconductor layer that is lowered due to the difference in the substrate is in contact with each other on the side surfaces. It is characterized by the following.

A step of forming a second semiconductor layer having a second conductivity on a substrate having a gap; a step of forming an insulating layer having an insulating property on the second semiconductor layer;
Forming a first semiconductor layer having conductivity different from that of the second semiconductor layer on the insulating layer; and forming a first semiconductor layer in a portion of the first semiconductor layer which is higher due to a difference between the substrates. Forming a gate electrode on one semiconductor layer;
Forming a drain electrode on a first semiconductor layer formed in a portion of the first semiconductor layer which is lowered by the difference in the substrate; and forming a drain electrode on the first semiconductor layer in the second semiconductor layer. Forming a source electrode on the second semiconductor layer formed at the higher portion in order, and bonding the first semiconductor layer and the second semiconductor layer to each other to form a band between the bands at the bonding surface. A method for manufacturing a tunnel transistor for forming a tunnel junction, comprising:
A first semiconductor layer formed in a portion of the semiconductor layer that becomes lower due to the difference in the substrate, and a second semiconductor layer formed in a portion of the second semiconductor layer that becomes higher due to the difference in the substrate And the thickness of the insulating layer is set so that the two sides are in contact with each other.

(Function) In the present invention configured as described above, the first semiconductor layer, the first insulating layer, the second semiconductor layer, and the second insulating layer are formed on the substrate having the gap. By laminating the first semiconductor layer and the second semiconductor layer, a band-to-band tunnel junction is formed at the bonding surface. At this time, the substrate of the first semiconductor layer is cut. The first and second semiconductor layers formed in a portion that is higher due to the difference and the second semiconductor layer that is formed in a portion of the second semiconductor layer that is lower due to the difference between the substrates are in contact with each other on the side surfaces of the substrate. Since the difference and the thickness of the first insulating layer are set, the bonding surface between the first semiconductor layer and the second semiconductor layer is not processed for bonding, and the remaining bonding surface is not processed. No impurities are generated.

As a result, the negative resistance characteristic is improved, and the range of application as a functional element is expanded.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a tunnel transistor according to a first embodiment of the present invention.

In this embodiment, as shown in FIG.
A substrate 1 made of semi-insulating GaAs; a drain layer 2 formed on the substrate 1 as a first semiconductor layer made of degenerated first conductive p ⁺ -GaAs; I-GaAs formed on a part of the drain layer 2 formed in a part which becomes higher due to the difference and a drain layer 2 formed in a part which becomes lower due to the difference
s, a first insulating layer 3 made of s, a channel layer 4 which is a second semiconductor layer made of degenerated n ⁺ -GaAs formed on the insulating layer 3, and a part of the channel layer 4 A gate insulating layer 5 as a second insulating layer made of i-Al _0.3 Ga _0.7 As, a gate electrode 6 made of an Al film formed on the gate insulating layer 5, and an insulating layer on the drain layer 2. A formed on a part of the portion where the layer 3 is not formed
A drain electrode 7 made of a uZn / Au film and a part of a part of the channel layer 4 where the gate insulating layer 5 is not formed on the drain layer 4 formed in a part which is lowered due to the difference of the substrate 1. And a source electrode 8 made of an AuGe / Au film. Here, i described above is an abbreviation that means a non-doped semiconductor that can be regarded as intrinsic or substantially intrinsic.

The difference between the thickness of the insulating layer 3 and the thickness of the drain layer 2 is higher than that of the drain layer 2 and the channel layer 4. The channel layer 4 formed in a portion that is lowered due to the difference is set to be in contact with each other on the side surfaces.

In the tunnel transistor having the above-described structure, the drain layer 2 and the channel layer 4 formed in the portion of the drain layer 2 which are higher due to the difference between the substrates 1 become lower due to the difference between the substrate 1 and the channel layer 4. The channel layer 4 formed in this portion is joined to each other at the side surfaces, and an interband tunnel junction is formed at the joining surface, and n ⁺ -GaAs
By controlling the concentration by the gate voltage using the channel layer 4 composed of a channel as a channel, a transistor operation having a differential negative resistance characteristic can be obtained.

Hereinafter, a method for manufacturing the above-described tunnel transistor will be described.

First, a 200 nm high step structure is formed on the substrate 1. At this time, the shape of the side wall is set to 90 degrees by dry etching using chlorine gas or anisotropic etching using the difference in etching rate between different crystal planes so that film formation is not performed on the side wall surface of the difference structure. A steep shape having an angle close to or a reverse sheath shape. In addition,
In this embodiment, patterning is performed on a (100) GaAs substrate, and anisotropic etching is performed using a mixed solution of sulfuric acid, hydrogen peroxide, and water (volume ratio 1: 1:10).
The (111) A surface was exposed to form an inverted sheath structure. On the other hand, in the above-described conventional example, since the channel layer needs to be formed on the side wall of the gap formed in the drain region, the shape is a regular sheath shape.

Next, a thickness of 2
Drain layer 2 (concentration 5 consisting of p ⁺ -GaAs of 0nm
× 10 ¹⁹ cm ^-3 Be is contained as a dopant)
And a drain layer 2 formed on a portion of the drain layer 2 which is higher due to the difference in the substrate 1 and a drain layer 2 formed on a portion which is lower due to the difference in a thickness of 200 nm. an insulating layer 3 made of i-GaAs, and a channel layer 4 made of n ⁺ -GaAs (containing Si having a concentration of 1 × 10 ¹⁹ cm ⁻³ as a dopant) having a thickness of 12 nm on the insulating layer 3. Further, a gate insulating layer 5 made of i-Al _0.3 Ga _0.7 As and having a thickness of 20 nm is sequentially grown on a part of the channel layer 4.

At this time, in each layer, a portion which becomes higher due to the difference and a portion which becomes lower are cut at the difference, and the drain layer 2 is formed at a portion which becomes higher due to the difference of the substrate 1. The gap of the substrate 1 and the thickness of the insulating layer 3 are set so that the drain layer 2 and the channel layer 4 formed in the portion of the channel layer 4 which are lowered due to the gap of the substrate 1 are in contact with each other on the side surfaces. I have.

Thus, the drain layer 2 formed in the portion of the drain layer 2 which is higher due to the difference in the substrate 1 and the channel layer 4 formed in the portion of the channel layer 4 which is lower due to the difference in the substrate 1 Are bonded on the side surfaces of each other, and an interband tunnel junction is formed at the bonding surface.

Next, on the gate insulating layer 5, a thickness of 50 nm
The gate electrode 6 is formed by depositing an Al film and processing the Al film and the gate insulating film 5.

Here, in the gate electrode 6, the substrate 1
Are formed so that the lower portion and the higher portion are connected to each other, and the surfaces have the same height.

Thereafter, a drain electrode 7 made of AuZn / Au is formed on a part of the drain layer 2 formed on a part of the drain layer 2 which is higher due to the difference in the substrate 1 by a lift-off method, and the channel layer 4 is formed. The source electrode 8 made of an AuGe / Au multilayer film is respectively formed on a part of the channel layer 4 formed in a portion which becomes higher due to the difference in the substrate 1.

In the tunnel transistor manufactured by the above-described series of steps, a processing process for exposing the junction surface to form a tunnel junction is not required, and a high-quality junction interface can be obtained. As a result, the excess current which causes the deterioration of the negative resistance characteristic is reduced by one digit or more compared to the conventional example.

(Second Embodiment) FIG. 2 is a sectional view showing a tunnel transistor according to a second embodiment of the present invention.

In the present embodiment, as shown in FIG.
A substrate 11 made of semi-insulating GaAs, and n ⁺ -GaAs having a degenerated second conductivity formed on the substrate 11
A channel layer 14 which is a second semiconductor layer made of a semiconductor layer, and a portion of the channel layer 14 formed on a portion of the channel layer 14 which is higher due to the difference between the substrate 11 and a portion which is lower due to the difference. the gate insulating layer 15 made of i-Al _0.3 Ga _{0 .7} As respectively formed on the channel layer 14
And the degenerated p ⁺ -G formed on the gate insulating layer 15.
a drain layer 12 which is a first semiconductor layer made of aAs
And Al formed on the drain layer 12 formed in a portion of the drain layer 12 which becomes higher due to the difference of the substrate 11.
A gate electrode 16 made of a film, a drain electrode 17 made of an AuZn / Au film formed on a part of the drain layer 12 formed on a part of the drain layer 12 which is lowered due to a difference between the substrates 11, and a channel layer. And a source electrode 18 made of an AuGe / Au film formed on a part of the part where the gate insulating layer 5 is not formed on the channel layer 14 formed on the part of the channel layer 14 which is lowered due to the difference of the substrate 11. Have been. Here, i described above is an abbreviation that means a non-doped semiconductor that can be regarded as intrinsic or substantially intrinsic.

Further, the difference between the substrate 11 and the gate insulating layer 1
At a thickness of 5, the drain layer 12 formed in a portion of the drain layer 12 which is lowered due to the difference in the substrate 11 and the channel layer 14 formed in a portion of the channel layer 14 which is increased due to the difference in the substrate 1 Are set to be in contact with each other on the sides.

In the tunnel transistor configured as described above, the drain layer 12 formed in a portion of the drain layer 12 which becomes lower due to the difference between the substrates 11 and the channel layer 14 becomes higher due to the difference between the substrates 11. The channel layer 14 formed in the portion is joined to each other at the side surfaces, and an interband tunnel junction is formed at the joining surface, and n
By controlling the concentration by the gate voltage using the channel layer 14 made of ⁺ -GaAs as a channel, a transistor operation having a differential negative resistance characteristic can be obtained.

Hereinafter, a method for manufacturing the above-described tunnel transistor will be described.

First, a cut structure having a height of 70 nm and an angle close to 90 degrees or a side surface of an inverted sheath structure is formed on the substrate 11.

Then, a channel layer 14 (containing Si of a concentration of 1 × 10 ¹⁹ cm ^-3 as a dopant) made of n ⁺ -GaAs having a thickness of 12 nm is formed on the substrate 11 by the MBE method. The thickness on the channel layer 14 formed on the portion of the layer 14 which becomes higher due to the difference of the substrate 11 and the thickness on the channel layer 14 formed on the portion of the channel layer 14 which becomes lower due to the difference of the substrate 11 50nm i
A gate insulating layer 15 made of -Al _0.3 Ga _0.7 As, and ap ⁺ -GaAs having a thickness of 20 nm on the gate insulating layer 15.
s drain layer 2 (a concentration of 5 × 10 ¹⁹ cm ⁻³ Be)
Is sequentially grown.

At this time, in each layer, a portion which becomes higher due to the difference and a portion which becomes lower are cut at the difference, and the drain layer 12 is formed in a portion which becomes lower due to the difference in the substrate 11. The gap of the substrate 11 and the thickness of the gate insulating layer 15 are set such that the drain layer 12 and the channel layer 14 formed in a portion of the channel layer 14 which are higher due to the gap of the substrate 11 are in contact with each other on the side surfaces. ing.

Thus, the substrate 1 of the drain layer 12
Drain layer 1 formed in a portion which becomes lower due to the difference of 1
2 and the channel layer 14 formed in the portion of the channel layer 14 which is higher due to the difference in the substrate 11 are joined to each other on the side surfaces, and an interband tunnel junction is formed at the joint surface.

Thereafter, the gate electrode 6 made of an Al film is formed on the drain layer 12 formed in a portion of the drain layer 12 which is higher due to the difference of the substrate 11 by a lift-off method.
And A on a part of the drain layer 12 formed on a part of the drain layer 12 which becomes lower due to the difference of the substrate 11.
a drain electrode 17 made of uZn / Au, and a source electrode 18 made of an AuGe / Au multilayer film on a portion of the channel layer 14 formed on a portion of the channel layer 14 which is higher due to the difference of the substrate 11. Form.

In the tunnel transistor manufactured by the above-described series of steps, a high-quality junction interface can be obtained without the need for a process for exposing the junction surface to form a tunnel junction. As a result, the excess current which causes the deterioration of the negative resistance characteristic is reduced by one digit or more compared to the conventional example.

In the first and second embodiments described above, the case where the drain region is p-type has been described. However, the present invention can be applied to the case where the drain region is n-type.

The materials used include a substrate,
Although GaAs is used for the drain layer and the channel layer, and AlGaAs is used for the insulating layer and the gate insulating layer, the present invention is not limited to this, and other materials can be used.

For example, as the drain layer and the channel layer, in addition to a single semiconductor such as Si, Ge, GaAs, and InP, GaAs / AlGaAs, Ge / SiGe, Si /
SiGeC, Si / GaP, Ge / GaAs, InAs
P / GaAs, InGaAs / InAlAs, InGa
As / InP, GaSb / AlGaSb, InAs / A
lGaSb, InSb / InAs, HgCbTe / Cb
A semiconductor having a heterojunction such as Te can be used. As the insulating layer, in addition to AlGaAs, other semiconductors having a wide band gap such as SiO ₂ , Si ₃ N ₄ , silicon oxynitride, Al ₂ O ₃ , TiO ₃ , PbZrTiO ₃ , C
aF or the like can be used.

In the above embodiment, the source electrode is directly drawn from the channel layer. However, the source electrode may be drawn through a degenerated semiconductor region having the same conductivity as the channel layer. Further, in the second embodiment, the gate electrode is formed on the drain layer, but may be formed on the gate insulating layer.

[0054]

Since the present invention is constructed as described above, it has the following effects.

According to the first and third aspects, the first semiconductor layer, the first insulating layer, the second semiconductor layer, and the second insulating layer are formed on the substrate having the difference. By laminating and bonding the first semiconductor layer and the second semiconductor layer, an inter-band tunnel junction is formed at the bonding surface. The substrate is cut such that the first semiconductor layer formed in the higher portion and the second semiconductor layer formed in the lower portion of the second semiconductor layer of the second semiconductor layer are in contact with each other on the side surfaces. Since the difference and the thickness of the first insulating layer are set, the bonding surface between the first semiconductor layer and the second semiconductor layer is not processed for bonding, and an interband tunnel junction is formed. Reducing the amount of residual impurities at the junction surface It can be.

As a result, the negative resistance characteristics are improved, the application range as a functional element is expanded, and a tunnel transistor having excellent element characteristics can be provided.

According to the second and fourth aspects of the present invention, the second semiconductor layer, the insulating layer and the first semiconductor layer are respectively laminated on the substrate having the difference, and the first semiconductor layer By bonding to the second semiconductor layer, an inter-band tunnel junction is formed at the bonding surface. At this time, the first semiconductor layer is formed in a portion which is lower due to the difference in the substrate. The gap between the substrate and the thickness of the insulating layer is set so that the first semiconductor layer and the second semiconductor layer of the second semiconductor layer, which are formed in a portion higher due to the gap between the substrates, are in contact with each other on the side surfaces. Therefore, the same effect as above can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a tunnel transistor according to the present invention.

FIG. 2 is a sectional view showing a second embodiment of the tunnel transistor of the present invention.

FIG. 3 is a schematic structural view showing an example of a conventional tunnel transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,11 Substrate 2,12 Drain layer 3 Insulating layer 4,14 Channel layer 5,15 Gate insulating layer 6,16 Gate electrode 7,17 Drain electrode 8,18 Source electrode

Claims (4)

[Claims] 1. A first semiconductor layer made of a semiconductor having a first conductivity, a first insulating layer having an insulating property, and a first semiconductor layer formed on a substrate having a step. A second semiconductor layer having a different conductivity and a second insulating layer having an insulating property are sequentially stacked, and formed in a portion of the first semiconductor layer which is higher due to a difference between the substrates. A drain electrode formed on a first semiconductor layer; a source electrode formed on a second semiconductor layer formed in a portion of the second semiconductor layer that is lowered due to a difference in the substrate; A tunnel transistor having a gate electrode formed on a second insulating layer, wherein the first semiconductor layer is formed in a portion of the first semiconductor layer which is higher due to a difference between the substrates. Low due to the difference between the substrate and the second semiconductor layer. Tunnel transistor and the second semiconductor layer is characterized in that in contact with the side surface of another formed becomes part. 2. A second semiconductor layer made of a semiconductor having a second conductivity, an insulating layer having an insulating property, and a conductive property different from that of the second semiconductor layer on a substrate having a difference. A gate electrode formed on a first semiconductor layer formed in a portion of the first semiconductor layer that is higher due to the difference in the substrate; A drain electrode formed on a first semiconductor layer formed in a portion of the first semiconductor layer which is lowered due to the difference between the substrates; and a drain electrode formed on the second semiconductor layer which is higher due to the difference between the substrates. And a source electrode formed on a second semiconductor layer formed on a portion of the first semiconductor layer, wherein the first semiconductor layer is formed on a portion of the first semiconductor layer which becomes lower due to a difference between the substrates. A first semiconductor layer and the second semiconductor layer Tunnel transistor and the second semiconductor layer is equal to or in contact with the side surface of each other, which among formed becomes higher portion by the cross-sectional difference in the substrate. 3. A step of forming a first semiconductor layer having a first conductivity on a substrate having a step, and forming a first insulating layer having an insulating property on the first semiconductor layer. A step of forming a second semiconductor layer having a different conductivity from the first semiconductor layer on the first insulating layer; and a second insulating layer having an insulating property on the second semiconductor layer. A step of forming a layer; a step of forming a gate electrode on the second insulating layer; and a step of forming a gate electrode on the second semiconductor layer, the first semiconductor layer being formed on a portion of the first semiconductor layer which is higher due to a gap between the substrates. Forming a drain electrode on the second semiconductor layer, and forming a source electrode on a second semiconductor layer formed on a portion of the second semiconductor layer that is lower due to the cross-section of the substrate. By joining the first semiconductor layer and the second semiconductor layer A method for manufacturing a tunnel transistor for forming an inter-band tunnel junction at the junction surface, comprising: a first semiconductor layer formed in a portion of the first semiconductor layer which is higher due to a difference between the substrates; And the thickness of the first insulating layer are set such that the second semiconductor layer formed in a portion of the semiconductor layer that is lowered due to the difference in the substrate is in contact with each other on the side surfaces. A method for manufacturing a tunnel transistor. A step of forming a second semiconductor layer having a second conductivity on a substrate having a difference; a step of forming an insulating layer having an insulating property on the second semiconductor layer; Forming a first semiconductor layer having conductivity different from that of the second semiconductor layer on the insulating layer; and forming a first semiconductor layer formed in a portion of the first semiconductor layer which is higher due to a difference between the substrates. Forming a gate electrode on the first semiconductor layer; forming a drain electrode on a first semiconductor layer formed in a portion of the first semiconductor layer that is lowered due to the difference in the substrate; Forming a source electrode on a second semiconductor layer formed in a portion of the second semiconductor layer which is higher due to the difference between the substrates, wherein the first semiconductor layer and the second semiconductor By joining the layers, at the joining surface A method of manufacturing a tunnel transistor for forming a band-to-band tunnel junction, comprising: forming a first semiconductor layer and a second semiconductor layer formed in a portion of the first semiconductor layer that is reduced by a difference in the substrate. Wherein the thickness of the substrate and the thickness of the insulating layer are set so that the second semiconductor layer formed in a portion which is higher due to the difference between the substrates is in contact with each other on the side surfaces. Manufacturing method.