JPH1079484A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a filter capacitor of a large capacitance to be manufactured with superior conformity with a memory cell region process by a capacitive coupling between a conductive layer and a diffusion layer patterned on a nitride film of an element-forming region, through nitride film covering a semiconductor substrate in which an impurity diffusion layer has been formed. SOLUTION: N-type diffusion layers DA2 are formed on both sides of a gate electrode in an active region of a memory cell part and on the surface regions of a semiconductor substrate 101 of an active region of a peripheral circuit part. A BPSG film 108 is deposited on a silicon nitride film 107 formed on the active regions, and a contact pattern is formed. A polysilicon film 121 is formed on the memory cell part, including a contact hole 108a from which a part of the silicon nitride film 107 on the impurity diffusion layer DA2 is exposed, and a contact hole 108b from which the silicon nitride film 107 on the active region of the peripheral circuit part is exposed and the entire peripheral circuit part. The silicon nitride film 107 functions as a dielectric, thereby performing a capacitive coupling between the impurity diffusion layer DA2 and the polysilicon layer 121.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a filter capacitor having high efficiency and high reliability and a method of manufacturing the same.

[0002]

2. Description of the Related Art Usually, a DRAM (Dynamic Random Acceses) is used.
In a semiconductor device such as a semiconductor device such as a transistor installed in a memory cell region and a peripheral circuit region, an instantaneous high voltage due to external power supply voltage noise or the like separates from a highly integrated memory cell region. To protect the device,
It is necessary to form a large-capacity capacitor as a filter capacitor in the peripheral circuit area.

As an example of the filter capacitor, there is a device using a field shield device isolation structure in which a shield gate electrode is buried in a silicon oxide film formed on a semiconductor substrate as an element isolation structure.

That is, this filter capacitor is formed by piercing an interlayer insulating film and a silicon oxide film (cap insulating film) on a shield gate electrode formed on the entire surface of an element forming region including a field shield element isolation structure. An opening for exposing a part of the surface of the electrode is formed, and a lead electrode is formed by patterning on an interlayer insulating film including the inside of the opening, and the semiconductor substrate and the shield gate electrode are formed by this shield. Capacitively coupled via a silicon oxide film (field shield gate oxide film) under the gate electrode.

[0005]

However, in the prior art described above, a field shield gate oxide film of a field shield element isolation structure, which is a silicon oxide film, is used as a dielectric film of a filter capacitor, so that a high capacitance cannot be obtained. There is a problem that high reliability cannot be obtained as a capacitor.

Further, in the prior art, when a contact hole for establishing conduction between an upper wiring and an impurity diffusion layer formed in a semiconductor substrate is formed after a filter capacitor is formed, misalignment of a resist pattern occurs. As a result, if the silicon oxide film (sidewall protective film) formed on the side of the field shield element isolation structure is etched together with the interlayer insulating film, there is a problem that the upper layer wiring and the shield gate electrode are short-circuited. .

[0007] In order to avoid this,
Since it was necessary to form a buried electrode of a polycrystalline silicon film from above the impurity diffusion layer to above the field shield element isolation structure, and to reduce the misalignment of the resist pattern, the manufacturing process was complicated.

Accordingly, it is an object of the present invention to provide a semiconductor device having a high-capacity filter capacitor, which can be manufactured by simple steps with good consistency with the process in the memory cell region, and an object of the present invention.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising a memory cell portion and a peripheral circuit portion each having an element formation region defined by forming an element isolation film on a semiconductor substrate, wherein the semiconductor substrate in the element formation region of the peripheral circuit portion is provided. An impurity diffusion layer formed by introducing an impurity into a surface region of the semiconductor substrate; a nitride film formed so as to cover at least a surface of the semiconductor substrate on which the impurity diffusion layer is formed; A conductive layer formed in a pattern on the nitride film in the element formation region; and the impurity diffusion layer and the conductive layer are capacitively coupled via the nitride film.

One embodiment of the semiconductor device according to the present invention is a semiconductor device in which each memory cell of the memory cell section includes an access transistor and a memory capacitor, wherein the memory capacitor is substantially higher than a bit line. The conductive layer of the peripheral circuit portion is formed of a conductive film of the same material as the bit line at a hierarchical position corresponding to the bit line of the memory cell portion.

One embodiment of the semiconductor device of the present invention is a semiconductor device in which each memory cell of the memory cell section includes an access transistor and a memory capacitor, wherein the memory capacitor is substantially lower than a bit line. And the conductive layer of the peripheral circuit portion is formed of a conductive film of the same material as the lower electrode at a hierarchical position corresponding to a lower electrode serving as a storage node of the memory capacitor of the memory cell portion. ing.

In one embodiment of the semiconductor device according to the present invention, the nitride film is a silicon nitride film.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a memory cell section and a peripheral circuit section on a semiconductor substrate, wherein each element isolation film is formed on the semiconductor substrate. A first step of defining an element formation region of each of the memory cell portion and the peripheral circuit portion, and introducing an impurity into a surface region of the semiconductor substrate in the element formation region of the memory cell portion and the peripheral circuit portion. A second step of forming each of the impurity diffusion layers, a third step of forming a nitride film so as to cover at least the surface of the semiconductor substrate on which the impurity diffusion layers are formed in the peripheral circuit portion, and the memory cell Forming a conductive layer on the entire surface of the portion and the peripheral circuit portion.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, an insulating layer is formed on the entire surface of the memory cell section and the peripheral circuit section after the third step and before the fourth step. A fifth step to be performed, and after the fifth step and before the fourth step, in the memory cell portion, the insulating layer is formed so that a part of a predetermined surface of the impurity diffusion layer is exposed. A sixth step of forming an opening and exposing the nitride film formed in the element formation region in the peripheral circuit portion;
After the fourth step, a seventh step of patterning the conductive layer in a bit line shape in the memory cell portion and patterning the conductive layer in a shape of an upper electrode of a capacitor in the peripheral circuit portion It further has.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, after the third step and before the fourth step, a predetermined impurity diffusion layer is formed in the memory cell portion. After the eighth step of removing a part of the nitride film so that a part of the surface is exposed, and after the fourth step, the conductive layer functions as a storage node of a memory capacitor in the memory cell portion. A ninth step of patterning the conductive layer in the shape of the lower electrode and patterning the conductive layer in the shape of the upper electrode of the capacitor in the peripheral circuit portion.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a tenth step of forming a dielectric film on the entire surface of the memory cell section and the peripheral circuit section after the ninth step; An eleventh step of forming an upper conductive layer over the entire surface of the memory cell part and the peripheral circuit part after a tenth step; and, after the eleventh step, the upper conductive layer is formed in the memory cell part. An eleventh step of patterning on each of the conductive layers via the dielectric film into a shape of a cell plate of the memory capacitor, and removing the upper conductive layer in the peripheral circuit portion.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a silicon nitride film is used as the nitride film.

The method of manufacturing a semiconductor device according to the present invention includes a first step of forming an element isolation film on a semiconductor substrate, a second step of forming a diffusion layer in an element active region of the semiconductor substrate, After the first and second steps, a third step of forming a nitride film on the semiconductor substrate, a fourth step of forming an insulating film on the nitride film, and partially removing the insulating film A fifth step, and after the fifth step, a sixth step of forming a conductive layer in the element active region.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, after the sixth step, a seventh step of forming an insulating film on the semiconductor substrate and the insulating step so that the conductive layer is exposed. An eighth step of forming an opening in the film and a ninth step of forming a wiring layer on the insulating film and in the opening are provided.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, after the third step, the first step of removing the nitride film formed in an element active region of a memory cell portion of the semiconductor substrate is performed.
0, and after the fourth step, in the memory cell portion, the conductive layer is processed into a bit line or capacitor lower electrode shape, and in the peripheral circuit portion, the conductive layer is formed as a filter capacitor. An eleventh step for processing into an upper electrode shape is further provided.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a silicon nitride film is used as the nitride film.

[0022]

In the semiconductor device of the present invention, the impurity diffusion layer formed on the semiconductor substrate in the element formation region of the peripheral circuit portion and the conductive layer formed via the nitride film are capacitively coupled to form a filter capacitor. ing. Therefore, since a filter capacitor can be obtained without using an electrode or the like in the element isolation film, it is not necessary to form a buried electrode serving as a pad when conducting conduction between the impurity diffusion layer and the upper layer wiring. It has a simple structure and high reliability.

In the method of manufacturing a semiconductor device according to the present invention, a conductive layer is formed in a memory cell portion and a peripheral circuit portion, and a memory cell portion is formed in a subsequent step in accordance with a memory cell structure (COB structure or CUB structure). In the above, the conductive layer is patterned into the shape of a bit line or a storage node of a memory capacitor, and in the peripheral circuit portion, the conductive layer is patterned into the shape of an upper electrode of a filter capacitor to form an impurity diffusion layer and a nitride film of a semiconductor substrate. To form a filter capacitor including the upper electrode. As described above, since the filter capacitor can be formed at the same time as the formation of the bit line and the storage node, the manufacturing process is significantly reduced.

According to another feature of the present invention, since a silicon nitride film is used as a dielectric film of a filter capacitor, a semiconductor device having a highly reliable filter capacitor can be manufactured. Become.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below in detail with reference to the drawings together with a method of manufacturing the same.

(First Embodiment) First, a first embodiment will be described. Here, as the semiconductor device, a DRAM in which a memory cell portion includes a memory cell having an access transistor and a memory capacitor is illustrated, and in particular, a configuration of a DRAM in which a filter capacitor is formed in a peripheral circuit portion is illustrated along with a manufacturing method thereof. . The DRAM according to the first embodiment has a COB (Capacitor Over Bitline) structure in which a memory capacitor is formed substantially above a bit line in a memory cell portion. 1 and 2 are schematic cross-sectional views showing a method of manufacturing a DRAM in the order of steps.
2 shows the memory cell section on the left side and the peripheral circuit section on the right side, and FIG. 2B shows only the peripheral circuit section.

First, as shown in FIG. 1A, a field shield is formed on a main surface of a semiconductor silicon substrate 101 in which a P-type diffusion layer (P-type well) DA1 is formed in each of a memory cell portion and a peripheral circuit portion. Isolation film 1 by the method
02 are respectively formed in the memory cell portion to form an active region AC.
1. The active area AC2 is defined in the peripheral circuit section. here,
The insulating film 103 and the conductive film 1 that constitute the element isolation film 102
For example, a thermal oxide film (about 40 nm in thickness), a polycrystalline silicon film (about 150 nm), a silicon oxide film (about 300 nm) formed by a low-pressure CVD method, and 200n
m).

Subsequently, the semiconductor substrate 10 in the active region AC1
After a gate oxide film 112 is formed on the gate oxide film 112 by, for example, a thermal oxidation method, a polycrystalline silicon film and a silicon oxide film are sequentially formed on the gate oxide film 112 by a CVD method or the like. The film and the silicon oxide film are subjected to photolithography and subsequent dry etching to form a gate electrode 113 and a cap insulating film 1 on the gate oxide film 112 in the active region AC1.
14 is patterned. Here, the gate oxide film 112
Is removed except for those under the gate electrode 113. Here, in FIG. 1, not only the gate electrode 113 of the active region AC1 but also the gate electrode 113 and the cap insulating film 114 formed on the active region AC1 (not shown) extend over the element isolation film 102. It shows the situation.

Subsequently, a silicon oxide film is deposited and formed on the entire surface of the active region AC1 including the element isolation film 102 by a CVD method or the like, and the silicon oxide film is subjected to anisotropic dry etching to form the gate electrode 113 (and A side wall protective film 115 is formed on the side portions of the gate oxide film 112 and the cap insulating film 114 while leaving the silicon oxide film.

Subsequently, the semiconductor substrate 10 on both sides of the gate electrode 113 is used for the active region AC1 in the memory cell portion using the cap insulating film 114 and the side wall protective film 115 as a mask.
In the surface region of the semiconductor substrate 101, the active region AC2 of the peripheral circuit portion is formed by using the element isolation film 102 as a mask.
An N-type impurity is ion-implanted into the surface region to form N-type diffusion layers DA2. Here, in the memory cell portion, the gate electrode 113 and the impurity diffusion layers D on both sides thereof are formed.
A2 forms an access transistor.

Next, as shown in FIG. 1B, a silicon nitride film 107 is formed on the entire surfaces of the active regions AC1 and AC2 including the memory cell portion and the peripheral circuit portion on the element isolation films 102 by the CVD method. The film is formed to a thickness of about 150 nm.

Then, as shown in FIG. 1C, a BPSG film 108 is deposited to a film thickness of about 500 nm on the silicon nitride film 107 in the memory cell portion and the peripheral circuit portion by normal pressure CVD, and is reflowed by heat treatment. BPSG film 1
08 is flattened.

Subsequently, B of the memory cell portion and the peripheral circuit portion
A resist 109 is applied on the PSG film 108, and a contact pattern is formed on the resist 109 by photolithography.

Next, as shown in FIG. 1D, dry etching is performed on the BPSG film 108 using the resist 109 as a mask and the silicon nitride film 107 as an etching stopper to form an opening following the contact pattern. At this time, the impurity diffusion layer D between the respective gate electrodes 113 formed in the active region AC1 is provided in the memory cell portion.
A contact hole 108a exposing a part of the silicon nitride film 107 on A2 is formed, and a contact hole 108b exposing the silicon nitride film 107 on the active region AC2 is formed in the peripheral circuit portion.

Subsequently, the resist 109 is ashed and removed by a dry ashing method. Next, a resist pattern 110 is formed by photolithography so as to cover only the peripheral circuit portion, and the silicon nitride film 107 at the bottom of the contact hole 108a is removed by dry etching.

Then, as shown in FIG. 2A, after the resist 110 is ashed and removed by dry ashing, the entire surface of the memory cell portion including the contact holes 108a and 108b and the peripheral circuit portion is formed by CVD. The polycrystalline silicon film 121 is formed to a thickness of, for example, about 200 nm.

Subsequently, the polycrystalline silicon film 121 is patterned by photolithography and subsequent dry etching, and processed into the shape of a bit line in the memory cell portion and the shape of the upper electrode of the filter capacitor in the peripheral circuit portion. . At this time, in the peripheral circuit portion, the impurity diffusion layer DA2, the silicon nitride film 10
7 and the polycrystalline silicon film 121, a filter capacitor is formed, and the silicon nitride film 107 functions as a dielectric, so that the impurity diffusion layer DA2 and the polycrystalline silicon film 111 are capacitively coupled.

Thereafter, although not shown, in the memory cell portion, the polycrystalline silicon film 12 serving as a bit line is formed.
A storage node made of a polycrystalline silicon film, a dielectric film made of an ONO film or the like, and a cell plate made of a polycrystalline silicon film are formed in a pattern on the upper layer portion 1 to form a memory capacitor.

In the peripheral circuit section, FIG.
As shown in FIG.
Then, photolithography and subsequent dry etching are performed on the interlayer insulating film 122 to expose the surface of the polycrystalline silicon film 121. Then, a conductive layer 123 is formed on the entire surface, and the conductive layer 123 is subjected to photolithography and subsequent dry etching to be processed into a shape of a lead electrode of an upper electrode made of the polycrystalline silicon film 121.

Next, a second embodiment of the present invention will be described. Here, similarly to the first embodiment, a DRA in which a filter capacitor is formed in a peripheral circuit portion is provided.
M will be exemplified together with its manufacturing method. The DRAM according to the first embodiment has a CUB (Capacitor Under Bitline) structure in which a memory capacitor is formed substantially above a bit line in a memory cell portion. 3 and 4 are schematic cross-sectional views showing a method of manufacturing the DRAM in the order of steps. The left side of each figure represents a memory cell portion, and the right side represents a peripheral circuit portion.

First, as shown in FIG. 3A, a field shield is formed on a main surface of a semiconductor silicon substrate 201 in which a P-type diffusion layer (P-type well) DA1 is formed in each of a memory cell portion and a peripheral circuit portion. Isolation film 2 by the method
02 are respectively formed in the memory cell portion to form an active region AC.
1. The active area AC2 is defined in the peripheral circuit section. here,
The insulating film 203 and the conductive film 2 that constitute the element isolation film 202
For example, a thermal oxide film (about 40 nm thick), a polycrystalline silicon film (about 150 nm), a silicon oxide film (about 300 nm) formed by a low-pressure CVD method, and 200n
m).

Subsequently, the semiconductor substrate 20 in the active region AC1
After a gate oxide film 212 is formed on the gate oxide film 212 by, for example, a thermal oxidation method, a polycrystalline silicon film and a silicon oxide film are sequentially deposited and formed on the gate oxide film 212 by a CVD method or the like. The film and the silicon oxide film are subjected to photolithography and subsequent dry etching to form a gate electrode 213 and a cap insulating film 2 on the gate oxide film 212 in the active region AC1.
14 is patterned. Here, the gate oxide film 212
Are removed except for those under the gate electrode 213.

Subsequently, a silicon oxide film is deposited and formed on the entire surface of the active region AC1 including the element isolation film 202 by a CVD method or the like, and the silicon oxide film is subjected to anisotropic dry etching to form the gate electrode 213 (and A side wall protective film 215 is formed leaving a silicon oxide film on the side of the gate oxide film 212 and the cap insulating film 214).

Subsequently, the semiconductor substrate 20 on both sides of the gate electrode 213 is used for the active region AC1 in the memory cell portion using the cap insulating film 214 and the side wall protective film 215 as a mask.
1 for the active region AC2 of the peripheral circuit portion using the element isolating film 202 as a mask.
An N-type impurity is ion-implanted into the surface region to form N-type diffusion layers DA2. Here, in the memory cell portion, the gate electrode 213 and the impurity diffusion layers D on both sides thereof are formed.
A2 forms an access transistor.

Next, as shown in FIG. 3 (b), a silicon nitride film 207 is formed on the entire surface of the active regions AC1 and AC2 including the memory cell portion and the peripheral circuit portion on the element isolation films 202 by a CVD method to a thickness of 150 nm. A film is formed to a degree.

Next, as shown in FIG. 3C, a resist 208 is applied and formed on the entire surface of the memory cell portion and the peripheral circuit portion, and a contact pattern is formed only on the memory cell portion by photolithography.

Subsequently, using the resist 208 as a mask, the silicon nitride film 207 in the memory cell portion is subjected to dry etching to form an opening following the contact pattern.
At this time, a contact hole 207a exposing a part of the surface of the impurity diffusion layer DA2 between the gate electrode 213 formed in the active region AC1 and the isolation film 202 is formed in the memory cell portion.

Subsequently, a silicon oxide film is deposited and formed on the entire surface of the memory cell portion by the CVD method, and anisotropic dry etching is performed on the entire surface to form a side wall protective film 210 on the side wall surface of the contact hole 207a.

Next, as shown in FIG. 3D, a polycrystalline silicon film 221 is deposited on the entire surface of the memory cell portion and the peripheral circuit portion to a thickness of, for example, about 200 nm by the CVD method. 221 is subjected to photolithography and subsequent dry etching to pattern the polycrystalline silicon film 221 in the memory cell portion into a storage node shape and the polycrystalline silicon film 221 in the peripheral circuit portion into an upper electrode shape of a filter capacitor.

Next, as shown in FIG. 4A, an oxide film, a nitride film, and an oxide film are sequentially formed on the entire surface of the memory cell portion and the peripheral circuit portion by the CVD method to form a three-layer O.
An NO film 209 is formed.

Subsequently, as shown in FIG. 4B, a polycrystalline silicon film 222 is deposited and formed on the entire surface of the memory cell portion and the peripheral circuit portion by the CVD method, and a maskless state is formed on the peripheral circuit portion. The polycrystalline silicon film 221 is subjected to photolithography and subsequent dry etching to form the polycrystalline silicon film 221 in a cell plate shape in the memory cell portion and to dry-etch the ONO film 209 in the peripheral circuit portion. The polycrystalline silicon film 221 is removed as a stopper.

At this time, in the memory cell portion, the storage node made of the polycrystalline silicon film 221 and the ONO
A memory capacitor is formed from a cell plate including the film 209 and the polycrystalline silicon film 222, and the ONO film 209 is formed.
Function as a dielectric, and the storage node and the cell plate are capacitively coupled. On the other hand, in the peripheral circuit portion, a filter capacitor is formed from an impurity diffusion layer DA2, an upper electrode formed of the silicon nitride film 207 and the polycrystalline silicon film 221, and the silicon nitride film 207 functions as a dielectric to form the impurity diffusion layer DA2. Capacitive coupling will occur with the upper electrode.

Subsequently, although not shown, a BPSG film is formed on the entire surface of the memory cell portion and the peripheral circuit portion by the CVD method, and reflowed by heat treatment to flatten the surface. Thereafter, the BPSG film is subjected to photolithography and subsequent dry etching to form a semiconductor substrate 201 between the gate electrodes 213 in the memory cell portion.
A contact hole for exposing the surface of the impurity diffusion layer DA2 formed on the substrate is formed, and the BPS including the inside of the contact hole is formed.
A bit line made of a polycrystalline silicon film is patterned on the G film. On the other hand, in the peripheral circuit portion, a connection hole exposing at least a part of the surface of the polycrystalline silicon film 222 serving as an upper electrode of the filter capacitor is formed in the BPSG film and the ONO film 209, and the BPSG including the connection hole is formed.
A conductive layer is formed on the G film, and the conductive layer is patterned into a shape of a lead electrode of the upper electrode.

As described above, in the first and second embodiments, since the silicon nitride films 107 and 207 are used as the dielectric films of the filter capacitors, misalignment of the resist 109 or 209 occurs. Also, since the silicon nitride film 107 or 207 serves as an etching stopper, a short circuit between the upper wiring and the shield electrode of the field shield element isolation film can be prevented.

In the first and second embodiments described above, the N-type impurity diffusion layer DA2 is formed in the well of the P-type impurity diffusion layer DA1. A well may be formed, and a P-type diffusion layer may be formed therein.

[0056]

According to the present invention, as described above, since a nitride film is used as a dielectric of a filter capacitor, a filter capacitor having a large capacity and high reliability can be manufactured. Further, since it is not necessary to form a buried electrode made of polycrystalline silicon or the like in the storage contact and the bit contact portion, the process can be shortened simultaneously.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 element isolation film 103 insulating film (oxide film) 104 conductive film (polycrystalline silicon film) 105 insulating film (oxide film) 106 sidewall film 107 silicon nitride film 108 BPSG film 121 polycrystalline silicon film 201 semiconductor substrate Reference Signs List 202 element isolation film 203 insulating film (oxide film) 204 conductive film (polycrystalline silicon film) 205 insulating film (oxide film) 206 sidewall film 207 silicon nitride film 209 ONO film 221, 222 polycrystalline silicon film

Claims (13)

[Claims] 1. A semiconductor device comprising: a memory cell portion and a peripheral circuit portion each having an element formation region defined by forming an element isolation film on a semiconductor substrate; An impurity diffusion layer formed by introducing an impurity into a surface region of the semiconductor substrate; a nitride film formed so as to cover at least a surface of the semiconductor substrate on which the impurity diffusion layer is formed; A conductive layer patterned on the nitride film in at least the element formation region of the portion, wherein the impurity diffusion layer and the conductive layer are capacitively coupled via the nitride film. Semiconductor device. 2. A semiconductor device in which each memory cell of the memory cell section includes an access transistor and a memory capacitor, wherein the memory capacitor is formed substantially at a position higher than a bit line. 2. The semiconductor device according to claim 1, wherein the conductive layer of the circuit section is formed of a conductive film of the same material as the bit line at a hierarchical position corresponding to the bit line in the memory cell section.
3. The semiconductor device according to claim 1. 3. A semiconductor device in which each memory cell of the memory cell section includes an access transistor and a memory capacitor, wherein the memory capacitor is formed substantially below a bit line. 3. The semiconductor device according to claim 1, wherein the conductive layer of the circuit unit is formed of a conductive film of the same material as the lower electrode at a hierarchical position corresponding to a lower electrode serving as a storage node of the memory capacitor of the memory cell unit. 2. The semiconductor device according to 1. 4. The semiconductor device according to claim 1, wherein said nitride film is a silicon nitride film. 5. A method of manufacturing a semiconductor device having a memory cell portion and a peripheral circuit portion on a semiconductor substrate, wherein each element isolation film is formed on the semiconductor substrate to form the memory cell portion and the peripheral circuit portion. A first step of defining an element formation region, and a second step of introducing an impurity into a surface region of the semiconductor substrate in the element formation region of the memory cell portion and the peripheral circuit portion to form an impurity diffusion layer, respectively. A third step of forming a nitride film so as to cover a surface of the semiconductor substrate on which the impurity diffusion layer is formed in at least the peripheral circuit section; and a conductive layer formed on the entire surface of the memory cell section and the peripheral circuit section. And a fourth step of forming a layer. 6. A fifth step of forming an insulating layer on the entire surface of the memory cell section and the peripheral circuit section after the third step and before the fourth step; Thereafter, before the fourth step, an opening is formed in the insulating layer so that a part of the surface of the predetermined impurity diffusion layer is exposed in the memory cell portion, and in the peripheral circuit portion, A sixth step of exposing the nitride film formed in the element formation region, and after the fourth step, in the memory cell portion, the conductive layer is patterned into a bit line shape and the peripheral circuit is formed. 6. The method according to claim 5, further comprising a seventh step of patterning the conductive layer into a shape of an upper electrode of a capacitor in the portion. 7. After the third step and before the fourth step, a part of the nitride film is removed so that a part of a predetermined surface of the impurity diffusion layer is exposed in the memory cell portion. An eighth step of removing; and after the fourth step, in the memory cell portion, the conductive layer is patterned into a shape of a lower electrode functioning as a storage node of a memory capacitor;
The method according to claim 5, further comprising: ninth step of patterning the conductive layer in the peripheral circuit portion into a shape of an upper electrode of a capacitor. 8. A first step of forming a dielectric film over the entire surface of the memory cell section and the peripheral circuit section after the ninth step.
0 step; an eleventh step of forming an upper conductive layer over the entire surface of the memory cell section and the peripheral circuit section after the tenth step; and a step of forming an upper conductive layer in the memory cell section after the eleventh step. An eleventh step of patterning the upper conductive layer on each of the conductive layers via the dielectric film into a shape of a cell plate of the memory capacitor, and removing the upper conductive layer in the peripheral circuit portion 8. The method of manufacturing a semiconductor device according to claim 7, further comprising: 9. The method for manufacturing a semiconductor device according to claim 5, wherein a silicon nitride film is used as said nitride film. 10. A first step of forming a device isolation film on a semiconductor substrate, and a second step of forming a diffusion layer in a device active region of the semiconductor substrate.
And after the first and second steps, a third step of forming a nitride film on the semiconductor substrate, a fourth step of forming an insulating film on the nitride film, A method for manufacturing a semiconductor device, comprising: a fifth step of partially removing; and, after the fifth step, a sixth step of forming a conductive layer in the element active region. 11. A seventh step of forming an insulating film on the semiconductor substrate after the sixth step, and an eighth step of forming an opening in the insulating film so that the conductive layer is exposed. The method according to claim 10, further comprising: forming a wiring layer on the insulating film and in the opening. 12. The method according to claim 10, further comprising: after the third step, a tenth step of removing the nitride film formed in the element active region of the memory cell portion of the semiconductor substrate. An eleventh step of processing the conductive layer into a bit line or capacitor lower electrode shape in the memory cell portion and processing the conductive layer into a filter capacitor upper electrode shape in the peripheral circuit portion is further provided. The method of manufacturing a semiconductor device according to claim 10. 13. The method for manufacturing a semiconductor device according to claim 10, wherein a silicon nitride film is used as said nitride film.