KR20010039178A - Method for fabricating a fully planarized dram device - Google Patents

Abstract

PURPOSE: A method for fabricating a DRAM is to simply a manufacturing process by excluding a planarizing process of an interlayer dielectric formed for a subsequent metal interconnection process. CONSTITUTION: A plurality of transistors(240) is formed on a semiconductor substrate(200) with a cell region and a core/peri region defined thereon. A contact pad(260) is formed on both sides of the transistor. The first interlayer dielectric(280) is formed on the resultant substructure. A bit line(300) is formed on the first interlayer dielectric. The second interlayer dielectric(320) is formed on the first interlayer dielectric. A contact hole is formed to expose the contact pad by etching the first and second interlayer dielectrics. A polysilicon is deposited and planarized on the second interlayer dielectric to fill in the contact hole, thereby forming a contact plug(340). An etching stop layer(360) is formed on the second interlayer dielectric. A sacrificial oxide layer(380) is formed to determine a height of a capacitor lower electrode. A lower electrode opening is formed to expose the contact plug by etching the sacrificial oxide layer and then removing the etching stop layer.

Description

DRAM manufacturing method of planarized semiconductor device {METHOD FOR FABRICATING A FULLY PLANARIZED DRAM DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DRAM fabrication of semiconductor devices, and more particularly, to a DRAM fabrication method of a planarized semiconductor device capable of omitting a planarization process for an interlayer insulating film formed on a capacitor.

Recently, semiconductor devices have been highly integrated in terms of economic cost. In particular, in the case of a memory device such as DRAM (DRAM), increasing the density is an important place. As is well known, increasing the degree of integration of semiconductor devices inevitably reduces the area occupied by the various elements formed on the semiconductor substrate. However, the capacitors that make up a memory device require a minimum constant capacitance for reliable device operation. At least about 25 fF per cell should be maintained to prevent soft errors caused by alpha-particles or errors in stored data due to noise.

Therefore, the method of integrating capacitors having the same capacitance in a small cross-sectional area is one of the important problems in DRAM due to the ultra-high integration that integrates a large number of devices in the same area or the same wafer and the reduction of the minimum line width due to the development of semiconductor processing technology. Can be. As is well known, the capacitance of a capacitor (C) = εx A / d. Where ε is the dielectric constant of the dielectric film formed between the two electrodes of the capacitor, A is the capacitor electrode area, and d is the thickness of the dielectric film, respectively.

Therefore, as a method of increasing capacitance within a given cell area, a method of using a material having high dielectric constant as a dielectric film, forming a thin dielectric film, or increasing an area of a capacitor electrode can be considered. Most of dielectric films are under development except NO film and ONO film, and there are still many problems to be solved such as reliability problem when applied to products. Another method is to increase the surface area of the capacitor electrode. To this end, the capacitor structure is complicated from a planar cell structure to a three-dimensional cylindrical structure, a trench structure, and a cell structure, and the cell structure is also a capacitor over bit in a capacitor under bit line (CUB). line). In the case of trench capacitors, the area of the lower electrode can be large, but there are problems such as isolation and complexity of the process technology. Accordingly, in recent years, cylindrical capacitors have been widely used. In this case, the step between the cell region and the peripheral region becomes large, the focus margin of the photolithography may decrease, and the metal wiring may be thinned or broken, and problems such as bridges may occur.

In the case of forming a cylindrical capacitor having such a COB structure, a step difference between the cell region and the core or the peripheral region occurs as much as the cell capacitor. It will be described in more detail with reference to Fig. 1a 1c.

1A to 1C are cross-sectional views showing a part of a DRAM manufacturing process according to a conventional method for explaining a problem of the planarization process. First, referring to FIG. 1A, an interlayer insulating film 20 having a contact plug 10 for a capacitor lower electrode is formed in a cell region of a semiconductor substrate (not shown). Next, a sacrificial oxide film is formed on the entire surface of the resultant, and selectively etched to form an opening for the capacitor lower electrode exposing the contact plug 10. Subsequently, the conductive film for the lower electrode is deposited, the lower electrode is separated by a cell unit, and the sacrificial oxide film is removed not only in the cell region but also in the core / peripheral region by a wet process, thereby completing the cylindrical lower electrode 30. Then, the capacitor dielectric film 40 and the upper electrode film 50 are formed and patterned to complete the capacitor. However, as shown, since the sacrificial oxide film is removed not only in the cell region but also in the core / peripheral region, a height difference (step difference) of approximately the height of the cell capacitor is generated between the cell region and the core / peripheral region. A second interlayer insulating film 60 is then formed on the resultant. As shown in the drawing, the step between the cell region and the core / peripheral region also causes a step difference between the second interlayer insulating layer 60.

This step is a major cause of reducing process margins in the subsequent process of connecting and wiring unit devices. Therefore, in order to reduce such a step, the planarization or ultimate planarization using various kinds of oxide films is generally performed by applying a chemical mechanical polishing process after forming a cell capacitor, as shown in FIGS. 1B and 1C. , Completely flatten the surrounding area. The fully planarization process is difficult to maintain a stable process because a large amount of oxide etching is performed when forming a metal contact, which is a subsequent process.

Accordingly, a partial planarization process is generally applied, which also causes a problem that the process is complicated and the process margin is narrow, making it difficult to bring a stable process.

Accordingly, an object of the present invention is to provide a DRAM manufacturing method capable of eliminating the planarization process of an interlayer insulating film formed after completion of a capacitor as proposed to solve the above-mentioned problems.

1A to 1C are cross-sectional views schematically showing a DRAM manufacturing method of a planarized semiconductor device by a conventional method;

2A to 2I are cross-sectional views schematically illustrating a DRAM manufacturing method of a flattened semiconductor device according to the present invention in a process sequence.

* Explanation of symbols for the main parts of the drawings

200: semiconductor substrate 220: device isolation region

240: transistor 260: contact pad

280,320 Insulation film 300: Bit line

340: capacitor lower electrode contact 360: etch stop layer

380: sacrificial oxide film 400: opening for the lower electrode

420: conductive film for lower electrode 440: planarization insulating film

460 photoresist 470 lower electrode

480: capacitor dielectric film 500: capacitor upper electrode

520: interlayer insulating film 540: via contact

560: metal wiring

A preferred configuration for achieving the object of the present invention is to form a first interlayer insulating film having at least a buried plug for a capacitor lower electrode in the cell substrate and a core / peripheral region defined therein, the first interlayer insulating film having the cell region; Forming a mold oxide film on the interlayer insulating film to determine the height of the capacitor lower electrode, etching the mold oxide film on the cell region to form an opening for the lower electrode exposing the buried plug, and opening Forming a first conductive film for a capacitor lower electrode on the mold oxide film to partially fill it, removing the first conductive film and leaving only the inside of the opening until the upper portion of the mold oxide film is exposed, and the cell region Selectively remove only the mold oxide film until the first interlayer insulating film of Forming an electrode in the cell region, the capacitor lower electrode having the same height as a mold oxide film in the core / peripheral region, and forming a capacitor dielectric layer and a capacitor upper electrode in the cell region to complete the capacitor; And forming a second interlayer dielectric layer on the capacitor upper electrode of the cell region and the mold oxide layer of the core / peripheral region.

In a preferred embodiment of the above method, removing the first conductive film and leaving only the inside of the opening until the upper portion of the mold oxide film is exposed, partially filling the opening with the first conductive film and then forming the mold. Forming an insulating film on the oxide film so as to completely fill the opening, and planarizing the insulating film and the first conductive film on both sides of the opening until the upper portion of the mold oxide film appears. Selectively removing only the mold oxide film until the interlayer insulating film appears to form the capacitor lower electrode in the cell region may include removing the insulating film.

In a preferred embodiment of the method, selectively etching the second interlayer insulating film to form a via contact exposing the capacitor upper electrode and forming a conductive material on the via contact and the second interlayer insulating film. And patterning the metal wirings.

According to the above-described preferred process configuration of the present invention, the height difference does not occur between the cell region and the core / peripheral region because the sacrificial oxide film is simultaneously removed not only in the cell region but also in the core / peripheral region. Therefore, the planarization process for the subsequent interlayer insulating film can be omitted.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention. In the drawings, regions, films, and the like, which are formed, are exaggerated for clarity and clarity.

2A to 2I are cross-sectional views sequentially illustrating a DRAM manufacturing process of a planarized semiconductor device according to an exemplary embodiment of the present invention. 2A is a schematic cross-sectional view of a portion of a semiconductor substrate in which a plurality of processes are already performed according to an embodiment of the present invention. As is well known, a DRAM device is divided into a cell array area in which a plurality of cells for storing data are formed and a core / peripheral area for controlling and driving the cell array area. First, an isolation region 220 is formed on a semiconductor substrate 200 in which a cell region and a core / peripheral region are defined to form an active region. A plurality of transistors 240 formed of a gate and a source / drain region are formed on the semiconductor substrate 200. In order to ensure process margins, contact pads 260 are typically formed at both sides of the transistor in the cell array region. Since the formation of the transistor and the formation of the contact pad are well known in the art, description thereof is omitted. Next, a first interlayer insulating film 280 is formed on the resultant as an oxide film, for example, an undoped oxide film or a borophospho silicate glass film such as an undoped silicate glass layer. Next, a bit line 300 is formed on the first interlayer insulating film 280. Although not shown on the surface, the bit line 300 may be formed by first etching the first interlayer insulating layer 280 to form a bit line contact exposing some of the contact pads on both sides of the transistor, and then depositing a conductive layer. And patterned to form.

Next, a second interlayer insulating layer 320 is formed on the first interlayer insulating layer 280 on which the bit line 399 is formed. The second interlayer insulating layer 320 may be formed by depositing a BPSG film and then reflowing at a predetermined temperature, or by performing an etch back process after depositing a USG film.

The next process is to form the storage contact plug 340. The second interlayer insulating layer 320 and the first interlayer insulating layer 280 are etched to form contact holes exposing the contact pads 260 on both sides of the transistor. Next, a conductive material, for example, polysilicon is deposited on the second interlayer insulating layer 320 and planarized to completely fill the contact hole, thereby completing the contact plug 340.

Next, a capacitor lower electrode forming process is performed. First, as illustrated in FIG. 2B, an etch stop layer is formed on the second interlayer insulating layer 320 including the contact plug 40. The etch stop layer 360 serves as an etch stop layer in the sacrificial oxide etching process for forming the opening for the lower electrode. The etch stop layer 360 may be formed of an oxide layer, which is the second interlayer insulating layer 320, and a material having an etching selectivity, for example, a silicon nitride layer. Next, a sacrificial oxide film 380 is formed to determine the height of the capacitor lower electrode.

Next, a photoresist film (not shown) is spin coated and patterned on the sacrificial oxide film 380 to define a capacitor lower electrode formation region. The sacrificial oxide film 380 is etched using the patterned photoresist film and then the etch stop film 360 is removed so that the opening 400 for the lower electrode exposes at least the contact plug 340. It is formed as shown.

Next, referring to FIG. 2D, the conductive film 420 for the capacitor lower electrode is formed on the opening 400 and the sacrificial oxide film 380. Then, the planarization process is performed to separate the lower electrode by cell unit. For this purpose, the planarization insulating layer 440 is formed on the conductive layer 420 to completely fill the wing opening. Then, the planarization process is performed until the upper portion of the sacrificial oxide film 380 appears by CMP or etch back (see FIG. 2E).

Next, a sacrificial oxide film removing process is performed to expose the inside and the outside of the lower electrode. According to the present invention, only the sacrificial oxide film in the cell region in which the lower electrode is formed is removed as shown in FIG. 2F. That is, the photoresist pattern 460 is formed to cover the core / peripheral region, and the lower electrode 470 is completed by removing the sacrificial oxide layer and the planarization insulating layer remaining in the opening of the cell region using the photoresist pattern 460 as an etch stop layer. Therefore, according to the present invention, a step does not occur between the cell region and the core / peripheral region.

Thereafter, the capacitor dielectric layer 480 and the conductive layer 500 for the upper electrode are formed to complete the cylindrical capacitor. Next, a third interlayer insulating film 520 is formed on the entire surface of the resultant product to insulate the capacitor after the upper electrode. In this case, as shown in FIG. 2G, the step difference between the cell region and the core / peripheral region is substantially not as high as the thickness of the capacitor upper electrode. Accordingly, the third interlayer insulating film 520 also has a substantially flat surface topology and does not need to be separately planarized as in the conventional method.

The next process is a metal wiring process. First, a via contact 540 is formed as shown in FIG. 2I to selectively etch the third interlayer insulating film to expose the upper electrode 520. Thereafter, the conductive material is deposited and patterned to complete the metal wiring 560.

Although the present invention has been described with reference to preferred embodiments, the scope of the present invention is not limited thereto. Rather, various modifications and similar arrangements are included. Therefore, the true scope and spirit of the claims of the present invention should be interpreted broadly to encompass such modifications and similar arrangements.

According to the features of the present invention as described above, since the sacrificial oxide film is kept in the core / periphery region, no step is generated between the cell region and the core / peripheral region after capacitor formation, and thus is formed for the subsequent metal wiring process. The planarization process for the interlayer insulating film can be omitted, which simplifies the process, reduces the process cost, and facilitates process control.

In addition, since the planarization process is excluded, the thickness of the interlayer dielectric layer for the metal wiring is reduced, and thus, the amount of the interlayer dielectric layer etched when the metal contact is formed may be reduced, thereby forming a stable metal contact.

Claims (3)

In the manufacture of planarized semiconductor devices, Forming a first interlayer insulating film having at least a buried plug for a capacitor lower electrode and said cell region on a semiconductor substrate having a cell region and a core / peripheral region defined therein; Forming a mold oxide film on the first interlayer insulating film to determine a height of a capacitor lower electrode; Etching the mold oxide film on the cell region to form an opening for a lower electrode exposing the buried plug; Forming a first conductive film for a capacitor lower electrode on the mold oxide film to partially fill the opening; Removing the first conductive film and leaving only the inside of the opening until the upper portion of the mold oxide film is exposed; Selectively removing only a mold oxide layer until the first interlayer dielectric layer of the cell region appears to form a capacitor lower electrode in the cell region, wherein the capacitor lower electrode has the same height as the mold oxide layer in the core / peripheral region. Has; Forming a capacitor dielectric layer and a capacitor upper electrode in the cell region to complete a capacitor; And And forming a second interlayer dielectric layer on the capacitor upper electrode of the cell region and the mold oxide layer of the core / peripheral region. The method of claim 1, Removing the first conductive film and leaving only the inside of the opening until the upper portion of the mold oxide film is exposed may include: partially filling the opening with the first conductive film and then completely filling the opening on the mold oxide film. Forming a film, and planarizing the insulating film and the first conductive film on both sides of the opening until an upper portion of the mold oxide film appears. Selectively removing only a mold oxide layer until the first interlayer dielectric layer of the cell region appears to form a capacitor lower electrode in the cell region, wherein the insulating layer includes removing the insulating layer. Manufacturing method. The method of claim 1, Selectively etching the second interlayer insulating film to form a via contact exposing the capacitor upper electrode; And And forming a metal material by forming and patterning a conductive material on the via contact and the second interlayer insulating layer.