JPH1074841A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, mounting a ring oscillator circuit which can monitoring the gate lag in a semiconductor chip with high accuracy by slightly increasing the area of an I/O buffer, without requiring inner cell and without setting a regulation of oscillation frequency for each design of user circuit. SOLUTION: Gate lag circuits 25 are arranged surrounding a semiconductor chip 100 with one gate lag circuit 25 substituting for an oscillation control circuit 22. Further, interconnections for two adjacent gate lag circuits 25 are provided at four corners A, thus constituting a ring oscillator circuit. Oscillation of the ring oscillator circuit is controlled through an oscillation control input buffer 20, the oscillation control circuit 22 and an oscillation control ring interconnection 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a ring oscillator circuit mounted on a same semiconductor substrate.

[0002]

2. Description of the Related Art Recently, with the miniaturization of semiconductor processes,
2. Description of the Related Art The speed of semiconductor devices is rapidly increasing, and higher-speed and higher-precision designs are required. Therefore, it is necessary to test the semiconductor integrated circuit with high accuracy in order to guarantee the operation of the semiconductor integrated circuit.

Therefore, an ASIC (Application Specification) such as a gate array and a cell-based IC has been proposed.
c) In order to perform a test of IC) with high accuracy, a method of measuring the AC characteristics of an ASIC using a tester is used in a semiconductor manufacturing line.

This method is roughly classified into two methods. The first method uses a circuit designed by a circuit designer and measures a delay time from an input terminal to an output terminal of the circuit. The second method is a method of preparing a circuit for exclusively measuring a delay time using a basic cell such as a NAND, NOR, or flip-flop provided by a semiconductor manufacturer to a circuit designer.

In the first method, it is not easy to determine the guaranteed standard value of the delay value because the circuit configuration is various for each product and the threshold voltage and other parameters of the MOS transistor greatly vary. In addition, if the method of determining the guaranteed standard value is incorrect, there is a problem that the yield of the ASIC is reduced.

As a second method, an inverter, a NAN
A ring oscillator circuit is widely used in which basic cells such as D and NOR are connected in series in an odd number of stages, and the output is fed back to the input terminal of the first basic cell to oscillate to form a rounded input waveform.

The method of measuring the delay time using the ring oscillator circuit does not have the problem that the delay time to be measured differs greatly for each product which is a problem in the first method, and the basic method of forming the ring oscillator circuit By fixing the number of cell stages, a constant oscillation frequency can be obtained, so that the guaranteed standard value of the delay value that reflects the process capability of the semiconductor manufacturing line can be easily determined.

A conventional delay time measuring circuit using a ring oscillator circuit includes a ring oscillator circuit 1 and an NA controlling the oscillation of the ring oscillator circuit 1 as shown in FIG.
An oscillation control circuit 2 composed of an ND gate 7, a gate delay circuit 3 in which an even number of inverters 8 are connected in series, bonding pads 4 and 4 ', an oscillation control input buffer 5, and an oscillation monitor output buffer 6 Be composed.

Next, the basic operation of the delay time measuring circuit using the conventional ring oscillator circuit 1 will be described.

When the control signal a input from the external terminal of the ASIC to the bonding pad 4 is at a low level, one of the NAND gates 7 constituting the oscillation control circuit 2 is fixed at a low level. b is fixed at a high level. Therefore, in this case, the ring oscillator circuit 1 stops the oscillating operation, and no current consumption flows. That is, the control signal a is set to the high level only when the oscillation frequency of the ring oscillator circuit 1 is measured, and is fixed to the low level in other cases.

Next, when the oscillation control signal a is set to the high level, one of the gates of the NAND gate 7 is set to the high level and the other gate is set to the high level or the low level according to the output signal c of the gate delay circuit 3. 7
Changes to a high level or a low level according to a change in the signal c. Therefore, the inverter 8 forming the NAND gate 7 and the gate delay circuit 3 forms a feedback circuit composed of an odd number of basic cells, and the oscillation is determined by the delay time of the NAND gate 7 and the inverter 8 and the number of inverter stages of the gate delay circuit 3. Oscillates at the frequency. Also,
The delay value of the NAND gate 7 or the inverter 8 can be easily obtained from the oscillation frequency of the ring oscillator circuit 1.

The oscillation monitor output buffer 6 receives the oscillation output of the ring oscillator circuit 1 and outputs it to the bonding pad 4 '. Therefore, by observing an external terminal (not shown) connected to the bonding pad 4 'with a tester, the oscillation frequency of the ring oscillator circuit 1 linked to the delay time of the internal circuit of the ASIC can be measured.

A conventional ring oscillator circuit 1 shown in FIG.
A well-known example of a delay time measuring circuit formed on a gate array substrate based on a delay time measuring circuit using a semiconductor device is disclosed in
No. 28353 and Japanese Utility Model Laid-Open No. 63-128735. The gate array device described in JP-A-3-228353 will be described with reference to FIG.
Reference numeral 1 denotes an input / output buffer area, 12 denotes a basic cell row constituting the ring oscillator circuit 1, 13 denotes an input buffer unit of the delay measurement circuit, 14 denotes an output buffer unit of the delay measurement circuit,
Reference numerals 5 and 16 denote corner portions of the gate array chip 9.

The input buffer unit and the output buffer unit of the delay measuring circuit are arranged at four corners on the chip, and the ring oscillator circuit 1 is arranged using the uppermost column or the lowermost column among the internal basic cell columns. ing.

The ring oscillator circuit 1 is connected to the basic cell row 10
There are a method of performing manual design and a method of performing automatic design using a computer as a method of arranging and wiring between basic cells. In the case of manual design, the basic cells are arranged relatively uniformly in the basic cell row and the wiring length connecting the basic cells is short, so the aluminum wiring capacitance and wiring resistance added to the output of the basic cells are constant. The advantage is that the oscillation frequency of the ring oscillator circuit 1 can be kept constant without depending on the design of each product of the gate array.

However, the circuit element designed by the circuit designer cannot be arranged in the area where the ring oscillator circuit 1 is arranged in the basic cell row, and the arrangement efficiency of the circuit element is reduced. There's a problem.

On the other hand, in the case of automatic design using a computer, there is an advantage that the basic cells can be arranged and the wiring between the basic cells can be performed in a short time, but the basic cells are arranged at an arbitrary position in the basic cell row 10. In addition, the length of the aluminum wiring connecting the basic cells is not constant, and the aluminum wiring capacitance and the wiring resistance that differ for each product of the gate array are different from those of the ring oscillator circuit 1.
, The delay time of the gate delay circuit 3 is not constant, and the oscillation frequency of the ring oscillator circuit differs for each product of the gate array.

In the conventional example disclosed in Japanese Utility Model Laid-Open Publication No. 63-128735, the oscillation control input buffer 5 and the oscillation monitor output buffer 6 are disclosed in Japanese Patent Laid-Open No. 3-228353.
The ring oscillator circuit 1 including the gate delay circuit 3 and the oscillation control circuit 2 is disposed in the chip external region in advance by a master slice method, as in the same manner as in Japanese Patent Application Laid-Open No. H10-157572. . In this case, the oscillation frequency of the ring oscillator circuit 1 formed on the master slice substrate is always constant irrespective of the product of the master slice, and the basic cells constituting the ring oscillator circuit 1 do not use the internal area. The feature is that the internal cell array can be used effectively.

[0019]

As described above, the ring oscillator circuit 1 is occupied by the delay time measuring circuit described in JP-A-3-228353 in which the ring oscillator circuit 1 is arranged in the basic cell row 10. Circuit elements cannot be arranged in the region of the basic cell row 10
Not only does the number of base cells that can be placed substantially decrease,
Circuit elements must be arranged in the basic cell row 10 avoiding the ring oscillator circuit 1 already arranged in the basic cell row 10, so that the degree of freedom in layout design is reduced, and the circuit elements are not arranged or not wired. Is more likely to occur.

When the ring oscillator circuit 1 is laid out by automatic design using a computer, basic cells such as inverters and NANDs constituting the ring oscillator circuit 1 can be placed at any position in the basic cell row 10 every time the layout is designed. In addition, the wiring length of the wiring connecting the basic cells also changes for each product. Therefore, the wiring capacitance and the wiring resistance associated with the wiring also change, and the oscillation frequency of the ring oscillator circuit 1 changes for each product, making it difficult to determine a test standard value of the oscillation frequency.

In the delay time measuring circuit described in Japanese Utility Model Laid-Open No. 63-128735, a ring oscillator circuit 1 is mounted in a small area located in a semiconductor chip corner or a chip external area inside a bonding pad. Since they are arranged, there is a problem that manufacturing variations in a semiconductor chip cannot be sufficiently grasped.

For example, when monitoring the in-chip manufacturing variation of the logical threshold value of the inverter, the wafer size is set to 6 inches (= 25.4 mm × 6), the chip size is set to 15 mm square, and the inverter size in the 6-inch wafer plane is changed. Assuming that the variation of the logic threshold is 15% in absolute value, the variation of the logic threshold of the inverter in the chip is 15% × 15 mm１５ (25.4 mm × 6) ≒ 1.
5%. Further, assuming that the layout area of ring oscillator circuit 1 is 0.15 mm □, the variation of the logic threshold value of the inverter in this region is 15% × 0.1
5 mm ÷ (25.4 mm × 6) ≒ 0.01%. This indicates that the ring oscillator circuit 1 only monitors a partial area of the semiconductor chip, and cannot grasp delay variations in the semiconductor chip.

An object of the present invention is to provide a semiconductor integrated circuit capable of measuring a delay time without using an internal area of a semiconductor chip on which circuit elements are arranged.

Another object of the present invention is to provide a semiconductor integrated circuit which generates a constant delay time independent of products.

Still another object of the present invention is to provide a semiconductor integrated circuit capable of monitoring delay time variations in a semiconductor chip.

[0026]

Therefore, a semiconductor integrated circuit according to the present invention comprises a plurality of bonding pads provided on an end side of a semiconductor substrate and a plurality of input / output buffers arranged inside these bonding pads. And an oscillation control ring wiring arranged inside the input / output buffer along the arrangement direction of these input / output buffers, and inverting an input signal by wiring between circuit elements constituting the input / output buffer. A gate delay circuit having an even number of output inverting circuits connected thereto, an oscillation control input buffer for outputting a control signal input from the bonding pad to the oscillation control ring wiring, and an output of the gate delay circuit when activated by the control signal An oscillation control circuit for inverting and outputting a signal, wherein the gate delay circuit is an even number And sequentially connected to constitute a delay circuit array,
The output terminal of the last gate delay circuit of this delay circuit row is connected to the input terminal of the oscillation control circuit, and the output terminal of the oscillation control circuit is connected to the input terminal of the first gate delay circuit of the delay circuit row. Forming a ring oscillator circuit, connecting the oscillation control ring wiring and the output terminal of the oscillation control input buffer and the input terminal of the oscillation control circuit,
The oscillation of the ring oscillator circuit is controlled by an output signal of the oscillation control input buffer.

[0027]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of a semiconductor chip showing a first embodiment of the present invention, and FIG. 2 is based on the arrangement of elements constituting a circuit corresponding to the region 23 of FIG. It is a circuit diagram expressed.

In the semiconductor integrated circuit according to the present embodiment, as shown in FIG. 1, internal cells 19 are arranged in a grid in an internal region of a semiconductor chip 100, and an input / output buffer 18 is fixed around the internal cells. An oscillation control input buffer 20 and an oscillation monitor output buffer 21 which form a circuit by using a part of elements such as transistors and resistors constituting the input / output buffer 18 and wiring between these elements.
Are arranged, and a bonding pad 17 is further arranged outside.

An oscillation control ring wiring 24 is arranged between the internal cell 19 and the input / output buffer 18 so as to go around the semiconductor chip 100, and a part of the elements constituting the input / output buffer 18 is used to connect these elements. Is arranged at a position near the internal cell 19 of the input / output buffer 18, and the gate delay circuit 25 is similarly arranged inside the oscillation control input buffer 20. In the input / output buffer 18 in which the oscillation monitor output buffer 21 is formed, an oscillation control circuit 22 is arranged using a part of the elements constituting the input / output buffer 18.

The four corners A of the horizontal delay circuit 25 and the vertical delay circuit 25 have delay circuits 2
Wirings that connect the five are arranged, so
Delay circuit 2 arranged along oscillation control ring wiring 24
5, one oscillation control circuit 22, and four wirings (not shown) arranged at the corner A constitute the ring oscillator circuit 1.

Further, an oscillation control circuit 22 disposed inside the oscillation monitor output buffer 21 and connected by an oscillation control ring wiring 24 and a wiring 27, and an oscillation control ring wiring 2
The oscillation of the ring oscillator circuit 1 is controlled by the oscillation control input buffer 20 connected to the wiring 4 by the wiring 26.

The positions where the oscillation control input buffer 20, the oscillation monitor output buffer 21, and the oscillation control circuit 22 are arranged are formed by wiring the elements in which these circuits are arranged in the input / output buffer 18. Therefore, it is not limited to the position shown in FIG. 1 but can be arranged at any position as long as the input / output buffer 18 is arranged. Therefore, by using the input / output buffer 18 which is not used in the circuit operation, the ring oscillator circuit 1 can be controlled and the oscillation output can be monitored without increasing the number of external pins of the semiconductor integrated circuit.

The layout areas of the oscillation control circuit 22 and the gate delay circuit 25 are the input / output buffer 18, the oscillation control input buffer 20 or the oscillation monitor output buffer 2 respectively.
1, the area of the oscillation control circuit 22 and the gate delay circuit 25 is added even when the chip size of the semiconductor chip 100 is 4 mm square, which is a practical minimum size. The area ratio occupied by the semiconductor chip 100 is as small as about 0.2% at most, and the ring oscillator circuit 1 and the delay time measurement circuit using the same are mounted on the semiconductor chip without increasing the area of the semiconductor chip 100. Can be mounted.

Next, a semiconductor integrated circuit according to an embodiment of the present invention will be described in more detail with reference to FIG. In addition,
Circuit elements and wiring corresponding to the region shown in FIG.
The corresponding reference numerals of the above are marked with 'to clarify the correspondence.

The gate delay circuit 25 'constituting the unit delay circuit of the ring oscillator circuit 1 has two inverters 2
8 and a gate delay circuit 2 adjacent in the horizontal or vertical direction
5 ', and signal wirings 30A and 30B for transmitting signals to 5'.

The oscillation control circuit 22 'is composed of a NAND gate 29 and signal wirings 31A and 31B for transmitting a signal to a horizontally or vertically adjacent gate delay circuit 25' like the gate delay circuit 25 '. , Signal wiring 3
1A and 31B are designed to be automatically connected to the signal lines 30A and 30B in the adjacent gate delay circuit 25 '.

Next, the operation of the oscillation control circuit 22 'will be described. The oscillation control signal input from the bonding pad 17 to the oscillation control input buffer 20' is transmitted to the oscillation control ring wiring 24 '. ′ Is input to one input terminal of the NAND gate 29 to control the oscillation of the ring oscillator circuit 1. Also,
The oscillation signal of the ring oscillator circuit 1
And output to the bonding pad 17 connected to the external terminal of the semiconductor integrated circuit via the oscillation monitor output buffer 21 '. Therefore, the oscillation output of the ring oscillator can be tested by observing the external terminal using the tester.

In the embodiment of the present invention, since the gate delay circuit 25 is arranged so as to go around the semiconductor chip 100, four different delay values are taken in the left side, right side, upper side, and lower side of the semiconductor chip 100, respectively, and the test is performed. can do.

Since the oscillation control input buffer 20 'is normally clamped to a low level by a resistor or a transistor, the oscillation of the ring oscillator circuit 1 is automatically performed when no input signal enters the oscillation control input buffer 20'. Designed to stop at.

In the embodiment of the present invention, the gate delay circuit 25 forming the ring oscillator circuit 1 is formed by using a part of the input / output buffer 18, and the wiring connecting the gate delay circuits 25 is the same as that of the semiconductor chip 100. Since it is fixedly provided so as to have the minimum length on the substrate, the delay caused by the wiring changes for each product, and the delay value of the gate delay circuit 25 differs for each product. There is no problem that the oscillation frequency fluctuates.

Next, a second embodiment of the present invention will be described with reference to FIGS.

FIG. 3 is a schematic view of a semiconductor chip showing a second embodiment of the present invention, and FIG. 4 takes into account the arrangement and wiring information of elements constituting a circuit corresponding to the region 33 of FIG. It is a circuit diagram expressed.

The semiconductor integrated circuit according to the embodiment of the present invention includes an input / output buffer 18, a gate delay circuit 25, an oscillation control circuit 22, an oscillation control input buffer 200 along a lower side 111 of a semiconductor chip 110. An oscillation monitor output buffer 210 and wirings 26 and 27 are arranged.

The gate delay circuits 25 are arranged in a two-stage configuration adjacent to each other in the vertical direction. As can be seen from FIG. 4, the direction of each inverter is laid out in the opposite direction.
Further, similarly to the first embodiment, the semiconductor chip 110
, An oscillation control ring wiring 24 is arranged, and an input / output buffer 18 is arranged on the upper side, the left side, and the right side.

In the arrangement of the gate delay circuit 25 having a two-stage configuration, in the arrangement of the gate delay circuit 25 on the outer side (closer to the bonding pad 17), the inverter 28 and the wirings 30A and 30B are arranged from right to left. When the signal is transmitted to the left end via the wiring 34 and the signal is transmitted to the inner gate delay circuit 25 via the wiring 34, the NAND gate 29 is turned on from the left to the right via the inverter 28 and the wirings 30A and 30B. A signal is transmitted to the gate. NA
Signal wiring 27 'connected to another gate of ND gate 29
Is at a high level, the signal from the signal line 31A connected to one gate of the NAND gate 29
The signal is transmitted to the output of the ND gate 29 and transmitted to the adjacent gate delay circuit 25 via the signal wiring 31B.

As described above, when a signal is transmitted from the left side to the right side through the inner gate delay circuit 25 and the signal is transmitted to the right end gate delay circuit 25, the wiring paired with the wiring 34 (FIG. A signal is transmitted from the inner gate delay circuit 25 to the outer gate delay circuit 25 via a not shown). Therefore, an even number of inverters 28 and one NAND
The ring oscillator circuit 1 including the gate 29 is formed and oscillates.

In the present embodiment, the ring oscillator circuit 1 is formed by using the input / output buffer 18 disposed on the lower side and not using the input / output buffer 18 disposed on the upper side, the right side, and the left side. , Input / output buffer 18
When a special buffer requiring a large number of elements is used by using the elements arranged in the semiconductor chip, the special buffer is arranged by using arbitrary input / output buffers 18 on the upper side, the right side 112 and the left side of the semiconductor chip. There is an advantage that can be.

Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 5 is a schematic diagram of a semiconductor chip showing a third embodiment of the present invention.

The semiconductor integrated circuit according to the present embodiment includes an input / output buffer 18, a gate delay circuit 25, and a portion of the lower side 111 and the right side 112 of the semiconductor chip 120.
An oscillation control circuit 22, an oscillation control input buffer 200,
An oscillation monitor output buffer 210 and wirings 26 and 27 are arranged, and the gate delay circuit 25 is extended to a part of the right side 112 in the second embodiment of the present invention.

Therefore, the gate delay circuits 25 along the lower side 111 are vertically arranged adjacently in two stages, and the gate delay circuits 25 along the right side 112 are horizontally adjacently arranged in two stages. In the corner B, the lower side 111
Of the delay circuit 25 arranged along the right side, and the delay circuit 25 arranged along the right side 112
Are provided for connection to the delay circuit 25 at the lower end.

Also in the present embodiment, when a special buffer is used as in the second embodiment, an arbitrary input / output buffer 18 of a part of the upper side, the left side, and the right side 112 of the semiconductor chip is used. There is an advantage that a special buffer can be arranged.

Note that the second embodiment may be applied to other sides of the semiconductor chip. For example, a ring oscillator circuit to which the second embodiment of the present invention is applied may be independently disposed on each of the upper side, lower side 111, right side 112, and left side of the semiconductor chip. In this case, there is an advantage that the delay values near the upper side, lower side 111, right side 112, and left side of the semiconductor chip can be independently monitored.

[0055]

As described above, the semiconductor integrated circuit according to the present invention forms a ring oscillator circuit without using internal cells, so that all of the internal cells can be used as circuit elements. Also, the change in the conventional input / output buffer causes a very small increase in the area so that the oscillation control circuit and the gate delay circuit can be provided in the input / output buffer.

Further, the ring oscillator circuit mounted on the conventional semiconductor integrated circuit has a different oscillation frequency for each product, and it is difficult to determine a test standard for the oscillation frequency. In the mounted ring oscillator circuit, if the chip size of the semiconductor chip is determined, the number and arrangement of the gate delay circuits constituting the ring oscillator circuit, the wiring connecting the gate delay circuits, the gate delay circuit and the oscillation control circuit Are designed optimally, the oscillation frequency of the ring oscillator circuit is constant regardless of the product, and the test standard for the oscillation frequency can be easily determined.

Further, since the ring oscillator circuit mounted on the semiconductor integrated circuit of the present invention is arranged in a wide area along the bonding pad of the semiconductor chip,
The gate delay value fluctuating in the semiconductor chip can be accurately monitored.

The oscillation control input buffer, the oscillation monitor output buffer, and the oscillation control circuit formed in the same input / output buffer as the oscillation monitor output buffer may be located at a position where the input / output buffer is located. Can be placed at any position. Therefore, by using an input / output buffer that is not used in the circuit operation, the ring oscillator circuit can be controlled and the oscillation output can be monitored without increasing the number of external pins of the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram expressing the arrangement and wiring information of elements constituting a circuit corresponding to a region 23 in FIG. 1 in consideration.

FIG. 3 is a schematic view of a semiconductor chip showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram expressing the arrangement and wiring information of elements constituting a circuit corresponding to a region 33 in FIG. 3 in consideration.

FIG. 5 is a schematic diagram of a semiconductor chip showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a delay time measurement circuit including a ring oscillator circuit with a control circuit.

FIG. 7 is a schematic view of a conventional semiconductor chip.

[Explanation of symbols]

1 Ring oscillator circuit 2, 22, 22 'Oscillation control circuit 3, 25, 25' Gate delay circuit 4, 4 ', 17 Bonding pad 5, 20, 20', 200, 200 'Oscillation control input buffer 6, 21, 21 ', 210, 210' Oscillation monitor output buffer 7, 29 NAND gate 8, 28, 31, 32 Inverter 9 Gate array chip 10 Basic cell array 11 Input / output buffer area 12 Basic cell array constituting ring oscillator circuit 13 Delay measurement circuit Input buffer section 14 Output buffer section of delay measurement circuit 15, 16 Corner section of gate array chip 18 Input / output buffer 19 Internal cell 24, 24 'Oscillation control ring wiring 100, 110, 120 Semiconductor chip

Claims (4)

[Claims] 1. A plurality of bonding pads provided on an end side of a semiconductor substrate, a plurality of input / output buffers arranged inside these bonding pads, and input / outputs along an arrangement direction of the input / output buffers. An oscillation control ring wiring disposed inside the buffer, and a gate delay circuit having an even number of inverting circuits connected to circuit elements constituting the input / output buffer to invert and output an input signal, and An oscillation control input buffer for outputting a control signal input from a bonding pad to the oscillation control ring wiring and an oscillation control circuit for inverting and outputting an output signal of the gate delay circuit when activated by the control signal. In a semiconductor integrated circuit, an even number of the gate delay circuits are sequentially connected to form a delay circuit row, and the last of the delay circuit row An output terminal of the gate delay circuit is connected to an input terminal of the oscillation control circuit, and an output terminal of the oscillation control circuit is connected to an input terminal of the first gate delay circuit of the delay circuit row to form a ring oscillator circuit. Connecting the oscillation control ring wiring to the output terminal of the oscillation control input buffer and the input terminal of the oscillation control circuit, and controlling the oscillation of the ring oscillator circuit by the output signal of the oscillation control input buffer. Semiconductor integrated circuit. 2. The semiconductor device according to claim 1, wherein the gate delay circuit is arranged around the semiconductor chip.
A semiconductor integrated circuit as described in the above. 3. The ring oscillator circuit sequentially connects a delay circuit having a pair of a gate delay circuit disposed closer to the bonding pad and a gate delay circuit disposed farther from the bonding pad. 2. The semiconductor integrated circuit according to claim 1, wherein a delay circuit array is formed. 4. The semiconductor integrated circuit according to claim 3, wherein said delay circuit row is arranged over one side or a plurality of sides of the semiconductor chip.