JPH1074799A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH1074799A
JPH1074799A JP22888896A JP22888896A JPH1074799A JP H1074799 A JPH1074799 A JP H1074799A JP 22888896 A JP22888896 A JP 22888896A JP 22888896 A JP22888896 A JP 22888896A JP H1074799 A JPH1074799 A JP H1074799A
Authority
JP
Japan
Prior art keywords
resin
insulating resin
semiconductor device
insulating
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22888896A
Other languages
Japanese (ja)
Other versions
JP2957955B2 (en
Inventor
Tsukasa Shiraishi
司 白石
Yoshihiro Bessho
芳宏 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22888896A priority Critical patent/JP2957955B2/en
Publication of JPH1074799A publication Critical patent/JPH1074799A/en
Application granted granted Critical
Publication of JP2957955B2 publication Critical patent/JP2957955B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Abstract

PROBLEM TO BE SOLVED: To improve the wuality of the electrical connection between the semiconductor element and circuit board of a semiconductor device in which the element is mounted on the circuit board at a prescribed position in a face-down state and to improve the productivity of the device by filling up the clearance between the element and board with an insulating resin positioned to an area which does not come into contact with a coupling layer near the central part on the surface of the element and another insulating resin positioned to the surrounding area of the firstmentioned resin. SOLUTION: The insulating resin used for filling up the clearance between a semiconductor element l mounted on a circuit board 4 and the board 4 is composed of two different kinds of resins of an insulating resin A8 positioned to an area which does not come into contact with an electrical coupling layer 7 near the central part of the element l and another insulating 'resin B9 positioned to the surround'area of the resin A8. When the resin Y39 is cured, the element l is fixed to the board 4 after the element l is stuck to the board 4 by the cure shrinkage force of the resin 9. Therefore, the mechanical strength of the connection between the element l and board 4 can be improved and the element l can be mounted on the board 4 stably.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置及びその
製造方法に関し、特にフリップチップ実装技術を用いた
半導体装置及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a flip chip mounting technique and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】近年、半導体素子の集積度が高くなり、
半導体装置の小型化及び接続端子の狭ピッチ化が進み、
そのためフリップチップ実装技術用いた半導体装置の開
発が盛んに行われている。以下図面を参照しながら、従
来のフリップチップ実装技術を用いた半導体装置の一例
について説明する。2. Description of the Related Art In recent years, the degree of integration of semiconductor elements has increased,
As the miniaturization of semiconductor devices and the narrower pitch of connection terminals have progressed,
For this reason, semiconductor devices using flip chip mounting technology have been actively developed. Hereinafter, an example of a semiconductor device using a conventional flip chip mounting technique will be described with reference to the drawings.

【０００３】図５に従来のフリップチップ実装技術を用
いた半導体装置の平面図、及び図６に図５のII-II 線の
断面図を示す。半導体素子１０１の素子形成面上にはア
ルミ電極端子１０２が形成されている。アルミ電極端子
１０２面上には、Ａｕ、Ｃｕ等の導電性金属材料からな
る突起電極１０３が形成されている。一方、樹脂、セラ
ミックス、ガラス等の絶縁物からなる回路基板１０４の
主面上には、所望の配線パターン及び電極端子１０５が
形成されている。電極端子１０５は配線パターンに接続
され、フリップチップ実装の際、半導体素子１０１と電
気的接続を行う。突起電極１０３と電極端子１０５と
は、導電性接着剤１０６により電気的に接続されてい
る。導電性接着剤１０６はＡｇ、Ｃｕ、Ｎｉ等の導電性
金属材料の粉体を樹脂中に含んだ接着剤であり、突起電
極１０３と共に電気的結合層１０７を形成する。半導体
素子１０１と回路基板１０４の間の隙間部は絶縁樹脂１
０８が充填されている。絶縁樹脂１０８が硬化される
と、その硬化収縮応力により半導体素子１０１と回路基
板１０４を接着した後、強力に引きつけて固定する。そ
のため、半導体装置における半導体素子１０１と回路基
板１０４の接続の機械的強度を高められ、安定を保たれ
る。FIG. 5 is a plan view of a semiconductor device using a conventional flip-chip mounting technique, and FIG. 6 is a sectional view taken along the line II-II of FIG. An aluminum electrode terminal 102 is formed on the element forming surface of the semiconductor element 101. On the surface of the aluminum electrode terminal 102, a protruding electrode 103 made of a conductive metal material such as Au or Cu is formed. On the other hand, a desired wiring pattern and electrode terminals 105 are formed on the main surface of the circuit board 104 made of an insulating material such as resin, ceramics, and glass. The electrode terminal 105 is connected to a wiring pattern, and electrically connects to the semiconductor element 101 during flip chip mounting. The protruding electrode 103 and the electrode terminal 105 are electrically connected by a conductive adhesive 106. The conductive adhesive 106 is an adhesive containing a powder of a conductive metal material such as Ag, Cu, Ni or the like in a resin, and forms an electric coupling layer 107 together with the protruding electrodes 103. The gap between the semiconductor element 101 and the circuit board 104 is insulating resin 1
08 are filled. When the insulating resin 108 is cured, the semiconductor element 101 and the circuit board 104 are adhered by the curing shrinkage stress, and then strongly attracted and fixed. Therefore, the mechanical strength of the connection between the semiconductor element 101 and the circuit board 104 in the semiconductor device can be increased and stability can be maintained.

【０００４】以上のように構成された従来の半導体装置
の製造方法を図７を用いて説明する。まず、通常の半導
体プロセスにおいて所望の素子や配線及び絶縁膜を形成
した半導体素子１０１を多数個形成した半導体ウエハを
作製する。次に、アルミ電極端子１０２にプローブを接
触させ電気的検査を行い半導体素子１０１の良否を判定
したうえで、突起電極１０３を形成する。さらに、半導
体ウエハを個々の半導体素子１０１に切断加工する。一
方、予めＡｕやＣｕ等の導電性金属材料を用いて、絶縁
物からなる回路基板１０４上に所望の配線パターンや電
極端子１０５を形成しておく。この回路基板１０４上の
半導体素子１０１搭載面に、必要量の未硬化絶縁樹脂１
１２をディスペンサ等により塗布した上で、導電性接着
剤１０６を介して所定の電極端子１０５と突起電極１０
３が当接して、電気的接続が行えるように加圧加熱ヘッ
ド１１０を用いて半導体素子１０１をフェースダウンに
て配置する。その際、未硬化の絶縁樹脂１１２は半導体
素子１０１全面に押し広げられる。その後、加圧加熱ヘ
ッド１１０により必要量の加圧を半導体素子１０１裏面
より加えながら、加圧加熱ヘッド１１０及び加熱ステー
ジ１１１により所定の加熱を行い導電性接着剤１０６及
び未硬化の絶縁樹脂１１２を硬化させる。以上のように
してフリップチップ実装技術を用いた半導体装置を製造
していた。A method for manufacturing a conventional semiconductor device configured as described above will be described with reference to FIG. First, a semiconductor wafer on which a number of semiconductor elements 101 on which desired elements, wirings, and insulating films are formed in a normal semiconductor process is formed. Next, a probe is brought into contact with the aluminum electrode terminal 102 and an electrical test is performed to determine the quality of the semiconductor element 101, and then the protruding electrode 103 is formed. Further, the semiconductor wafer is cut into individual semiconductor elements 101. On the other hand, using a conductive metal material such as Au or Cu, a desired wiring pattern or electrode terminal 105 is formed on a circuit board 104 made of an insulating material. A required amount of the uncured insulating resin 1 is provided on the mounting surface of the semiconductor element 101 on the circuit board 104.
12 is applied by a dispenser or the like, and a predetermined electrode terminal 105 and a protruding electrode 10 are connected via a conductive adhesive 106.
The semiconductor element 101 is arranged face down by using the pressurizing and heating head 110 so that the semiconductor element 101 can be electrically connected to the semiconductor element 101 by contact. At this time, the uncured insulating resin 112 is spread over the entire surface of the semiconductor element 101. Thereafter, while applying a required amount of pressure from the back surface of the semiconductor element 101 by the pressure heating head 110, predetermined heating is performed by the pressure heating head 110 and the heating stage 111 to remove the conductive adhesive 106 and the uncured insulating resin 112. Let it cure. As described above, the semiconductor device using the flip chip mounting technology has been manufactured.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら上記のよ
うな従来の構成及び方法では、未硬化の絶縁樹脂が押し
広げられる際に、導電性接着剤を押し流したり、あるい
は導電性接着剤と電極端子の接着界面に絶縁樹脂が入り
込んだりして接続抵抗不良が発生するので半導体装置の
品質を著しく落とすという問題を有していた。However, in the above-described conventional structure and method, when the uncured insulating resin is spread, the conductive adhesive is swept away, or the conductive adhesive and the electrode terminals are separated. There is a problem that the quality of the semiconductor device is remarkably deteriorated because the connection resistance failure occurs due to the insulating resin entering the bonding interface.

【０００６】本発明は上記従来の問題点を解決するため
になされたものであり、半導体素子と回路基板とをより
確実に安定して電気的に接続することで、極めて品質の
安定した、生産性の良い半導体装置を提供することを目
的としている。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is possible to more reliably and stably electrically connect a semiconductor element and a circuit board to achieve extremely stable and stable production. It is an object to provide a semiconductor device with good performance.

【０００７】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明の半導体装置は、回路基板上の所定の位置に
半導体素子をフェースダウン方式で実装し、その電気的
接合は半導体素子のアルミ電極端子部に形成した導電性
金属材料からなる突起電極とこれに接する導電性接着剤
からなる結合層を介して行う半導体装置において、前記
半導体素子と回路基板間の隙間部全体が、半導体素子面
の中心部付近で前記結合層に到達しない領域に位置する
絶縁樹脂Ａと、前記絶縁樹脂Ａを外縁状に取り囲んだ領
域に位置する絶縁樹脂Ｂにより充填されていることを特
徴とする。In order to achieve the above object, a semiconductor device according to the present invention has a semiconductor element mounted in a predetermined position on a circuit board in a face-down manner, and its electrical connection is made by aluminum of the semiconductor element. In a semiconductor device formed through a protruding electrode made of a conductive metal material formed on an electrode terminal portion and a bonding layer made of a conductive adhesive in contact with the protruding electrode, the entire gap between the semiconductor element and the circuit board is formed on a semiconductor element surface. Is filled with an insulating resin A located in a region that does not reach the bonding layer near the center and an insulating resin B located in a region surrounding the insulating resin A in an outer edge shape.

【０００８】前記半導体装置においては、絶縁樹脂Ａ及
びＢに無機フィラーを含み、前記絶縁樹脂Ａに含まれる
無機フィラーの量が、絶縁樹脂Ｂに含まれる無機フィラ
ーの量と比較して、それと同等かまたはそれ以下である
ことが好ましい。In the semiconductor device, the insulating resins A and B contain an inorganic filler, and the amount of the inorganic filler contained in the insulating resin A is equivalent to the amount of the inorganic filler contained in the insulating resin B. Preferably it is less than or equal to.

【０００９】また前記半導体装置においては、絶縁樹脂
Ａに含まれる無機フィラーの量が０重量％を越え、８０
重量％以下の範囲であり、絶縁樹脂Ｂに含まれる無機フ
ィラーの量が３０重量％以上８０重量％以下の範囲であ
ることが好ましい。In the semiconductor device, the amount of the inorganic filler contained in the insulating resin A exceeds 0% by weight,
% By weight and the amount of the inorganic filler contained in the insulating resin B is preferably in the range of 30% by weight to 80% by weight.

【００１０】また前記半導体装置においては、無機フィ
ラーが、重量平均粒子直径０．０１〜１０μｍの範囲の
シリカ、酸化チタン、アルミナを含む酸化化合物、窒化
アルミを含む窒化化合物、炭化珪素を含む炭化化合物、
及び珪素化合物から選ばれる少なくとも一つのフィラー
であることが好ましい。In the semiconductor device, the inorganic filler may have a weight average particle diameter in a range of 0.01 to 10 μm, such as silica, titanium oxide, an oxide compound containing alumina, a nitride compound containing aluminum nitride, and a carbon compound containing silicon carbide. ,
And at least one filler selected from silicon compounds.

【００１１】また前記半導体装置においては、絶縁樹脂
Ａが、エポキシ樹脂、ポリイミド樹脂、アクリル樹脂、
ユリア樹脂、ポリウレタン樹脂から選ばれる少なくとも
一つの樹脂で、かつ絶縁樹脂Ｂが、エポキシ樹脂、ポリ
イミド樹脂、アクリル樹脂、ユリア樹脂、ポリウレタン
樹脂を含む架橋型反応性樹脂から選ばれる少なくとも一
つの樹脂であることが好ましい。In the semiconductor device, the insulating resin A may be made of an epoxy resin, a polyimide resin, an acrylic resin,
Urea resin, at least one resin selected from polyurethane resins, and insulating resin B is at least one resin selected from cross-linkable reactive resins including epoxy resin, polyimide resin, acrylic resin, urea resin, and polyurethane resin. Is preferred.

【００１２】また前記半導体装置においては、絶縁樹脂
Ａが、Ｂステージ（半硬化または部分硬化）特性を有す
る硬化性樹脂シートであることが好ましい。また前記半
導体装置においては、絶縁樹脂Ａが、熱可塑性の電気絶
縁性樹脂であることが好ましい。例えばホットメルト型
の熱可塑性ポリエステル樹脂や、ポリエステル樹脂に高
沸点希釈剤を混合し、硬化剤を用いないタイプの接着剤
があげられる。このタイプの熱可塑性の電気絶縁性樹脂
は、とくにリペア工法が簡便になる。In the semiconductor device, the insulating resin A is preferably a curable resin sheet having B-stage (semi-cured or partially cured) characteristics. In the semiconductor device, the insulating resin A is preferably a thermoplastic electric insulating resin. For example, a hot-melt type thermoplastic polyester resin or a type of adhesive obtained by mixing a high boiling point diluent with a polyester resin and using no curing agent is used. For this type of thermoplastic electrically insulating resin, the repair method is particularly simple.

【００１３】また前記半導体装置においては、絶縁樹脂
Ａが、紫外線照射及び加熱の両方で完全に硬化する樹脂
であることが好ましい。また前記半導体装置において
は、回路基板を構成する材料が、絶縁樹脂Ａと同じ種類
の樹脂材料であることが好ましい。Further, in the semiconductor device, it is preferable that the insulating resin A is a resin which is completely cured by both irradiation with ultraviolet rays and heating. Further, in the semiconductor device, it is preferable that the material forming the circuit board is the same kind of resin material as the insulating resin A.

【００１４】次に本発明の半導体装置の製造方法は、回
路基板上の所定の位置に半導体素子をフェースダウン方
式にて実装し、その電気的接合は半導体素子のアルミ電
極端子部に形成した導電性金属材料からなる突起電極と
これに接する導電性接着剤からなる結合層を介して行う
半導体装置の製造方法において、前記半導体素子と回路
基板間の隙間部全体は、半導体素子面の中心部付近で前
記結合層に到達しない領域に位置する絶縁樹脂Ａと、前
記絶縁樹脂Ａを外縁状に取り囲んだ領域に位置する絶縁
樹脂Ｂにより充填し、かつ前記絶縁樹脂Ａを硬化処理し
た後に、前記絶縁樹脂Ｂを注入することを特徴とする。Next, according to a method of manufacturing a semiconductor device of the present invention, a semiconductor element is mounted at a predetermined position on a circuit board by a face-down method, and an electrical connection is made between conductive electrodes formed on aluminum electrode terminals of the semiconductor element. In the method of manufacturing a semiconductor device performed through a protruding electrode made of a conductive metal material and a bonding layer made of a conductive adhesive in contact with the protruding electrode, the entire gap between the semiconductor element and the circuit board is located near the center of the semiconductor element surface. After filling the insulating resin A located in a region that does not reach the bonding layer with the insulating resin B located in a region surrounding the insulating resin A in an outer edge shape and curing the insulating resin A, the insulating resin A It is characterized by injecting resin B.

【００１５】前記方法においては、絶縁樹脂Ａ及びＢ
が、未硬化時では絶縁樹脂Ｂの流動性の方が絶縁樹脂Ａ
より良好であることが好ましい。また前記方法において
は、絶縁樹脂Ａに含まれる無機フィラーの量が０重量％
を越え、８０重量％以下の範囲であり、絶縁樹脂Ｂに含
まれる無機フィラーの量が３０重量％以上８０重量％以
下の範囲であることが好ましい。In the above method, the insulating resins A and B
However, when uncured, the fluidity of the insulating resin B is better than that of the insulating resin A.
Preferably, it is better. In the above method, the amount of the inorganic filler contained in the insulating resin A is 0% by weight.
And in the range of not more than 80% by weight, and the amount of the inorganic filler contained in the insulating resin B is preferably in the range of not less than 30% by weight and not more than 80% by weight.

【００１６】また前記方法においては、無機フィラー
が、重量平均粒子直径０．０１〜１０μｍの範囲のシリ
カ、酸化チタン、アルミナを含む酸化化合物、窒化アル
ミを含む窒化化合物、炭化珪素を含む炭化化合物、及び
珪素化合物から選ばれる少なくとも一つのフィラーであ
ることが好ましい。In the above method, the inorganic filler may have a weight average particle diameter in a range of 0.01 to 10 μm, such as silica, titanium oxide, an oxide compound containing alumina, a nitride compound containing aluminum nitride, and a carbon compound containing silicon carbide; And at least one filler selected from silicon compounds.

【００１７】また前記方法においては、絶縁樹脂Ａが、
エポキシ樹脂、ポリイミド樹脂、アクリル樹脂、ユリア
樹脂、ポリウレタン樹脂から選ばれる少なくとも一つの
樹脂で、かつ絶縁樹脂Ｂが、エポキシ樹脂、ポリイミド
樹脂、アクリル樹脂、ユリア樹脂、ポリウレタン樹脂を
含む架橋型反応性樹脂から選ばれる少なくとも一つの樹
脂であることが好ましい。In the above method, the insulating resin A is
At least one resin selected from an epoxy resin, a polyimide resin, an acrylic resin, a urea resin, and a polyurethane resin, and the insulating resin B is a cross-linked reactive resin including an epoxy resin, a polyimide resin, an acrylic resin, a urea resin, and a polyurethane resin. It is preferably at least one resin selected from the group consisting of:

【００１８】また前記方法においては、絶縁樹脂Ａが、
Ｂステージ（半硬化または部分硬化）特性を有する硬化
性樹脂シートであることが好ましい。また前記方法にお
いては、絶縁樹脂Ａが、熱可塑性の電気絶縁樹脂である
ことが好ましい。In the above method, the insulating resin A is
It is preferably a curable resin sheet having B-stage (semi-cured or partially cured) characteristics. In the above method, the insulating resin A is preferably a thermoplastic electric insulating resin.

【００１９】また前記方法においては、絶縁樹脂Ａは、
紫外線照射及び加熱の両方の処理を行うことにより完全
に硬化する樹脂であることが好ましい。また前記方法に
おいては、回路基板を構成する材料が、絶縁樹脂Ａと同
じ種類の樹脂材料であることが好ましい。In the above method, the insulating resin A is
It is preferable that the resin is completely cured by performing both the ultraviolet irradiation and the heating. Further, in the above method, it is preferable that the material forming the circuit board is the same kind of resin material as the insulating resin A.

【００２０】前記した本発明の半導体装置及びその製造
方法によれば、導電性接着剤が回路基板の電極端子と接
着硬化した後に、絶縁樹脂Ｂにより結合層が存する領域
が充填されるため、導電性接着剤が押し流されたり、あ
るいは導電性接着剤と電極端子の接着界面に絶縁樹脂が
入り込んだりすることがなくなるので、これらの要因に
よる接続不良は発生しなくなる。According to the semiconductor device and the method of manufacturing the same of the present invention described above, after the conductive adhesive is bonded and cured to the electrode terminals of the circuit board, the region where the bonding layer exists is filled with the insulating resin B. Since the conductive adhesive is not washed out or the insulating resin does not enter the bonding interface between the conductive adhesive and the electrode terminal, connection failure due to these factors does not occur.

【００２１】[0021]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

（実施の形態１）以下本発明の半導体装置の第１の実施
形態について、図１〜図３を参照しながら説明する。(Embodiment 1) Hereinafter, a first embodiment of a semiconductor device of the present invention will be described with reference to FIGS.

【００２２】図１は本発明の第１の実施形態に係る半導
体装置の構成を示す平面図、及び図２は図１のI-I 線の
断面図である。図１〜２に示すように、半導体素子１の
素子形成面上にはアルミ電極端子２が形成されており、
このアルミ電極端子２上には、Ａｕ、Ｃｕ等の導電性金
属材料からなる突起電極３が形成されている。一方、樹
脂、セラミックス、ガラス等の絶縁物からなる回路基板
４上には所望の回路パターン及び電極端子５が形成され
ている。本実施の形態においては、回路基板４としてガ
ラスエポキシ基板を用いた。FIG. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line II in FIG. As shown in FIGS. 1 and 2, an aluminum electrode terminal 2 is formed on an element formation surface of a semiconductor element 1.
On this aluminum electrode terminal 2, a protruding electrode 3 made of a conductive metal material such as Au or Cu is formed. On the other hand, a desired circuit pattern and electrode terminals 5 are formed on a circuit board 4 made of an insulating material such as resin, ceramics, and glass. In the present embodiment, a glass epoxy substrate is used as the circuit board 4.

【００２３】電極端子５は回路パターンに接続され、フ
リップチップ実装の際、半導体素子１との電気的接続を
行う。導電性接着剤６はＡｇ、Ｃｕ、Ｎｉ等の導電性金
属材料の粉体を樹脂中に７０〜９５重量％程度とエポキ
シ樹脂との接着剤であり、突起電極３と共に電気的結合
層７を形成する。半導体素子１と回路基板５の間の隙間
部には電気絶縁樹脂が充填されているが、この電気絶縁
樹脂は半導体素子１と回路基板５間の隙間部全体におい
て、半導体素子１中心部付近で電気的結合層７と接しな
い領域に位置する電気絶縁樹脂Ａ８と、前記電気絶縁樹
脂Ａ８を取り囲んだ領域に位置する電気絶縁樹脂Ｂ９の
異なる２種類の電気絶縁樹脂にて構成される。電気絶縁
樹脂９が硬化されると、その硬化収縮力により半導体素
子１と回路基板４を接着した後、強力に引きつけて固定
する。そのため、半導体装置における半導体素子１と回
路基板４の接続の機械的強度が高められ、安定が保たれ
る。The electrode terminals 5 are connected to a circuit pattern and make an electrical connection with the semiconductor element 1 during flip-chip mounting. The conductive adhesive 6 is an adhesive of about 70 to 95% by weight of a powder of a conductive metal material such as Ag, Cu, and Ni in the resin and the epoxy resin. Form. The gap between the semiconductor element 1 and the circuit board 5 is filled with an electric insulating resin. The electric insulating resin fills the entire gap between the semiconductor element 1 and the circuit board 5 near the center of the semiconductor element 1. It is composed of two different types of electrical insulating resin, an electrical insulating resin A8 located in a region not in contact with the electrical coupling layer 7 and an electrical insulating resin B9 located in a region surrounding the electrical insulating resin A8. When the electrical insulating resin 9 is cured, the semiconductor element 1 and the circuit board 4 are adhered by the curing shrinkage force, and then are strongly attracted and fixed. Therefore, the mechanical strength of the connection between the semiconductor element 1 and the circuit board 4 in the semiconductor device is increased, and stability is maintained.

【００２４】本実施の形態においては、電気絶縁樹脂Ａ
８として重量平均粒子直径０．１〜１μｍのシリカを５
０〜６０重量％程度含む酸無水型エポキシ樹脂を用い、
電気絶縁樹脂Ｂ９として重量平均粒子直径１〜１０μｍ
のシリカを５０〜６０重量％程度含むフェノールノボラ
ック型エポキシ樹脂を用いた。電気絶縁樹脂Ａに酸無水
型エポキシ樹脂を用い、電気絶縁樹脂Ｂにフェノールノ
ボラック型エポキシ樹脂を用いたのは、一般的特性とし
て、酸無水型型エポキシ樹脂の方がガラス転移点Ｔｇが
高く、耐熱性に優れるため、先に電気絶縁樹脂Ａを熱硬
化した後、電気絶縁樹脂Ｂを硬化させるために加熱処理
しても影響が少なく特性の劣化が見られないためであ
る。また、フェノールノボラック型エポキシ樹脂は耐水
性に優れるため、外縁状周囲に存在することで外部から
の湿度の侵入を防ぐ作用がある。In the present embodiment, the electric insulating resin A
8 as silica having a weight average particle diameter of 0.1 to 1 μm;
Using an acid anhydride type epoxy resin containing about 0 to 60% by weight,
Weight average particle diameter of 1 to 10 μm as electric insulating resin B9
A phenol novolak type epoxy resin containing about 50 to 60% by weight of the above silica was used. The use of an acid anhydride type epoxy resin for the electric insulating resin A and the use of a phenol novolak type epoxy resin for the electric insulating resin B is a general characteristic that the acid anhydride type epoxy resin has a higher glass transition point Tg, This is because, because of excellent heat resistance, even if the electric insulating resin A is heat-cured first and then heat treatment is performed to harden the electric insulating resin B, the influence is small and no deterioration in characteristics is observed. Further, since the phenol novolak type epoxy resin is excellent in water resistance, the phenol novolak type epoxy resin has an action of preventing the invasion of humidity from the outside by being present around the outer edge.

【００２５】次に、本発明の第１の実施形態の製造方法
について図３を参照しながら説明する。図３において１
０は加圧加熱ヘッドで１１は加熱ステージである。ま
た、１２は未硬化の絶縁樹脂Ａである。その他は図１〜
２と同じである。まず、通常の半導体プロセスにおいて
所望の素子や配線及び絶縁膜を形成した半導体素子１を
多数個形成した半導体ウエハを作製する。次に、アルミ
電極端子２にプローブを接触させ電気的検査を行い半導
体素子１の良否を判定したうえで、突起電極３を形成す
る。さらに、半導体ウエハを個々の半導体素子１に切断
する。一方、予めＡｕやＣｕ等の導電性金属材料を用い
て、絶縁物からなる回路基板４上に所望の配線パターン
や電極端子５を形成しておく。この回路基板４上の半導
体素子１搭載面に、必要量の未硬化絶縁樹脂Ａ１２をデ
ィスペンサ等により塗布した上で、導電性接着剤６を介
して所定の電極端子５と突起電極３が当接して、電気的
接続が行えるように加圧加熱ヘッド１０を用いて半導体
素子１をフェースダウンにて配置する。その際、未硬化
の絶縁樹脂Ａ１２は半導体素子１の中心部付近で結合層
７と接しない領域内にて押し広げられる。その後、加圧
加熱ヘッド１０により必要量の加圧を半導体素子１裏面
より加えながら、同時に加圧加熱ヘッド１０及び加熱ス
テージ１１により所定の加熱処理（例えば１８０〜２５
０℃の温度で加熱）を行い導電性接着剤６及び未硬化の
絶縁樹脂Ａ１２を硬化させる。加熱硬化後、加圧及び加
熱を停止してから絶縁樹脂Ｂを毛細管現象を利用して半
導体素子１と回路基板の間に注入した後、再度加熱を施
し硬化させることにより、絶縁樹脂Ａを取り囲む半導体
素子１全体に絶縁樹脂Ｂが充填されることとなり、２種
類の絶縁樹脂にて隙間部全体が充填される。Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIG. In FIG.
0 is a pressure heating head and 11 is a heating stage. Reference numeral 12 denotes an uncured insulating resin A. Others are shown in Figure 1
Same as 2. First, a semiconductor wafer in which a large number of semiconductor elements 1 on which desired elements, wirings, and insulating films are formed in a normal semiconductor process is manufactured. Next, a probe is brought into contact with the aluminum electrode terminal 2 and an electrical inspection is performed to determine the quality of the semiconductor element 1, and then the protruding electrode 3 is formed. Further, the semiconductor wafer is cut into individual semiconductor elements 1. On the other hand, using a conductive metal material such as Au or Cu, a desired wiring pattern and electrode terminals 5 are previously formed on the circuit board 4 made of an insulator. A required amount of uncured insulating resin A12 is applied to the mounting surface of the semiconductor element 1 on the circuit board 4 by a dispenser or the like, and then the predetermined electrode terminals 5 and the protruding electrodes 3 contact with each other via the conductive adhesive 6. Then, the semiconductor element 1 is arranged face down using the pressurizing and heating head 10 so that electrical connection can be made. At this time, the uncured insulating resin A12 is spread out in a region not in contact with the bonding layer 7 near the center of the semiconductor element 1. Thereafter, while applying a required amount of pressure from the back surface of the semiconductor element 1 by the pressure heating head 10, a predetermined heat treatment (for example, 180 to 25) is simultaneously performed by the pressure heating head 10 and the heating stage 11.
Then, the conductive adhesive 6 and the uncured insulating resin A12 are cured. After the heating and curing, the pressure and the heating are stopped, and then the insulating resin B is injected between the semiconductor element 1 and the circuit board by utilizing the capillary phenomenon, and then heated and cured again to surround the insulating resin A. The entire semiconductor element 1 is filled with the insulating resin B, so that the entire gap is filled with two types of insulating resins.

【００２６】本実施形態によると、導電性接着剤６が回
路基板の電極端子５と接着硬化した後に、絶縁樹脂Ｂ９
により結合層７の存する領域が充填されるため、導電性
接着剤６を押し流したり、あるいは導電性接着剤６と電
極端子５の接触界面に絶縁樹脂Ｂ９が入り込んだりする
ことがなくなるので、これらの要因による接続不良は発
生しなくなる。According to the present embodiment, after the conductive adhesive 6 is bonded and cured to the electrode terminals 5 of the circuit board, the insulating resin B9
This fills the area where the bonding layer 7 is present, so that the conductive adhesive 6 is not washed out, or the insulating resin B9 does not enter the contact interface between the conductive adhesive 6 and the electrode terminal 5, so that these The connection failure due to the factor does not occur.

【００２７】また、未硬化の絶縁樹脂Ａ１２の材料及び
量を最適化することで、接着強度を自由に設定できるの
で、絶縁樹脂Ｂ９充填までに要する必要な強度を保ち、
かつ不良と判明した半導体素子を簡単に取り外すことが
可能な範囲に設定することにより、絶縁樹脂Ｂ９注入前
に電気検査を実施し、不良となった半導体素子１を交換
して修正することが可能となる。この際、不良半導体素
子１を取り外した後に残る絶縁樹脂Ａ８は、必要に応じ
物理的、化学的な方法を用いて削る。By optimizing the material and amount of the uncured insulating resin A12, the adhesive strength can be freely set, so that the necessary strength required for filling the insulating resin B9 can be maintained.
In addition, by setting the semiconductor element determined to be defective in a range where the semiconductor element can be easily removed, an electric test can be performed before the insulating resin B9 is injected, and the defective semiconductor element 1 can be replaced and corrected. Becomes At this time, the insulating resin A8 remaining after the defective semiconductor element 1 is removed is removed by a physical or chemical method as necessary.

【００２８】なお、本発明の半導体装置の経時的な劣化
に対しては、絶縁樹脂Ｂ９の性能が与える影響の方がは
るかに大きいので適切な絶縁樹脂Ｂ９を用いることによ
り、例えば絶縁樹脂Ａ８の接着能力が不十分であって
も、後に市場において半導体装置の品質が問題となるこ
とはない。The performance of the insulating resin B9 has a much greater effect on the deterioration of the semiconductor device of the present invention over time. Therefore, by using an appropriate insulating resin B9, for example, the performance of the insulating resin A8 can be reduced. Even if the bonding ability is insufficient, the quality of the semiconductor device will not be a problem in the market later.

【００２９】（実施の形態２）以下本発明の半導体装置
の第２の実施形態について説明する。本実施形態におい
ては、第１の実施形態における未硬化時の電気絶縁樹脂
Ｂ９の流動性の方が電気絶縁樹脂Ａ８の流動性より良好
である樹脂を用いた構成である。流動性は、粘度及びチ
クソトロピー指数と相関がある。従って、電気絶縁樹脂
Ｂ９は電気絶縁樹脂Ａ８と比較すると粘度及びチクソト
ロピー指数が低いことが必要である。具体的には、粘度
１００Ｐａ・ｓ以下でかつチクソトロピー指数が１．１
以下であると実用的に好ましい。これは、絶縁樹脂Ａ８
の流動性が大であると、濡れ広がりや半導体素子１を配
置した直後の毛細管現象により未硬化の絶縁性樹脂Ａ８
が結合層７に到達してしまう可能性が大きくなり、製造
管理が厳しく困難になり、また、逆に未硬化時の絶縁樹
脂Ｂ９の流動性が小であると注入が遅く作業性が悪くな
るので、相対的に未硬化時において絶縁樹脂Ｂ９の流動
性の方が絶縁樹脂Ａ８の流動性より良好である構成とす
ることで、工程管理が容易となり、かつ生産時間の短縮
化が図られるので、本発明の半導体装置の生産性を高め
ることとなる。(Embodiment 2) A semiconductor device according to a second embodiment of the present invention will be described below. In the present embodiment, a resin is used in which the fluidity of the uncured electrical insulating resin B9 in the first embodiment is better than the fluidity of the electrical insulating resin A8. Fluidity correlates with viscosity and thixotropic index. Therefore, the electric insulating resin B9 needs to have a lower viscosity and a lower thixotropic index than the electric insulating resin A8. Specifically, the viscosity is 100 Pa · s or less and the thixotropy index is 1.1.
The following is practically preferable. This is insulating resin A8
If the fluidity of the insulating resin A8 is large, the uncured insulating resin A8 may be spread due to wet spreading or a capillary phenomenon immediately after the semiconductor element 1 is arranged.
Is likely to reach the bonding layer 7, making the production control strict and difficult. Conversely, if the fluidity of the uncured insulating resin B9 is low, the injection is slow and the workability is poor. Therefore, by adopting a configuration in which the fluidity of the insulating resin B9 is relatively better than the fluidity of the insulating resin A8 when it is relatively uncured, the process management becomes easy and the production time is shortened. Thus, the productivity of the semiconductor device of the present invention is improved.

【００３０】（実施の形態３）以下本発明の半導体装置
の第３の実施形態について説明する。本実施形態におい
ては、第１の実施形態における電気絶縁樹脂Ａ８に含有
する無機フィラー量は、電気絶縁樹脂Ｂ９に含有する無
機フィラー量と比較して同等以下である構成としてい
る。絶縁樹脂Ａは、重量平均粒子直径０．１〜１μｍの
シリカを２０〜３０重量％程度含む酸無水型エポキシ樹
脂を用い、電気絶縁樹脂Ｂ９として重量平均粒子直径１
〜１０μｍのシリカを５０〜６０重量％程度含むフェノ
ールノボラック型エポキシ樹脂を用いた。(Embodiment 3) Hereinafter, a third embodiment of the semiconductor device of the present invention will be described. In the present embodiment, the amount of the inorganic filler contained in the electric insulating resin A8 in the first embodiment is equal to or less than the amount of the inorganic filler contained in the electric insulating resin B9. As the insulating resin A, an acid anhydride type epoxy resin containing about 20 to 30% by weight of silica having a weight average particle diameter of 0.1 to 1 μm is used.
A phenol novolak type epoxy resin containing about 50 to 60% by weight of silica of 10 to 10 μm was used.

【００３１】通常、このような絶縁樹脂には、（１）膨
張係数低下、（２）耐湿性能向上の目的からシリカを中
心とした無機フィラーを含有させている。しかし、絶縁
樹脂Ａ８に含まれる無機フィラーは、半導体素子１裏面
より加圧して絶縁樹脂Ａ８を押し広げる際、半導体素子
１表面を傷つけ形成してある素子にダメージを与える。
従って、必要最小限の量に留めるのが良い。また、絶縁
樹脂Ｂ９は外気と接した構成となっているので、湿度進
入を防ぐためには許容範囲内で極力多くの無機フィラー
を含有する必要がある。従って、相対的にみると絶縁樹
脂Ａ８に含有する無機フィラー量は、絶縁樹脂Ｂ９に含
有する無機フィラー量と比較して同等以下とした構成と
することで、本発明の半導体装置を生産工程における半
導体素子に与えるダメージが少ない生産性に優れた、か
つ耐湿性能に優れたものすることができる。In general, such an insulating resin contains an inorganic filler mainly composed of silica for the purpose of (1) lowering the expansion coefficient and (2) improving the moisture resistance. However, when the inorganic filler contained in the insulating resin A8 is pressed from the back surface of the semiconductor element 1 to spread the insulating resin A8, the surface of the semiconductor element 1 is damaged to damage the formed element.
Therefore, it is better to keep the amount to the minimum necessary. Further, since the insulating resin B9 is in contact with the outside air, it is necessary to contain as much inorganic filler as possible within an allowable range in order to prevent humidity from entering. Therefore, when viewed relatively, the amount of the inorganic filler contained in the insulating resin A8 is set to be equal to or less than the amount of the inorganic filler contained in the insulating resin B9. It is possible to provide a semiconductor device which has less damage to a semiconductor element, has excellent productivity, and has excellent moisture resistance.

【００３２】（実施の形態４）以下本発明の半導体装置
の第４の実施形態について説明する。本実施形態におい
ては、第１の実施形態における未硬化の絶縁樹脂Ａ１２
として、Ｂステージ特性を有する樹脂シートを用いた構
成としている。樹脂シートとしては、例えばスリーボン
ド社製のスリーボンド１６５０や新興化学工業社製のＢ
−ＥＬ１０等がある。(Embodiment 4) A semiconductor device according to a fourth embodiment of the present invention will be described below. In the present embodiment, the uncured insulating resin A12 in the first embodiment is used.
The configuration uses a resin sheet having B-stage characteristics. Examples of the resin sheet include ThreeBond 1650 manufactured by ThreeBond and B
-EL10 and the like.

【００３３】Ｂステージの樹脂シートを用いることによ
り、液状樹脂をディスペンスする場合に比べて、下記の
利点が得られる。 （１）塗布量が温度や湿度に依存せずに一定である。 （２）貼り付けなので、ディスペンサ塗布等に比べ位置
精度が高い。 （３）濡れ広がりがなく、ほぼ貼り付け位置が接着領域
となる。By using the B-stage resin sheet, the following advantages can be obtained as compared with the case where liquid resin is dispensed. (1) The coating amount is constant without depending on the temperature and humidity. (2) Since it is pasted, the positional accuracy is higher as compared with dispenser application or the like. (3) There is no spread of wetness, and the bonding position is almost the bonding area.

【００３４】したがって、絶縁樹脂Ａ８が結合層７に到
達することがほぼ皆無となる。また、量的管理が容易で
接着領域を規定し易いため接着強度の設定が管理し易
く、不良半導体素子１の取り替え時に加える力、加熱温
度等の工程条件が一定となる。このように、未硬化の絶
縁樹脂Ａ１２としてＢステージ特性を有する樹脂シート
を用いることにより、本発明の半導体装置の生産時に受
ける温度や湿度の影響が少なくなりので、生産管理が容
易となり生産性が高まる。Therefore, the insulating resin A8 hardly reaches the bonding layer 7. Further, since the quantitative control is easy and the bonding area is easy to define, the setting of the bonding strength is easy to control, and the process conditions such as the force applied when replacing the defective semiconductor element 1 and the heating temperature become constant. As described above, by using the resin sheet having the B-stage characteristic as the uncured insulating resin A12, the influence of the temperature and humidity during the production of the semiconductor device of the present invention is reduced, so that the production management becomes easy and the productivity is improved. Increase.

【００３５】（実施の形態５）以下本発明の半導体装置
の第５の実施形態について説明する。本実施形態におい
ては、第１の実施形態におけるて電気絶縁樹脂Ａ８とし
て、熱可塑性樹脂としては、ポリイミド樹脂をブチル・
カルビトール・アセテート（ＢＣＡ）等の揮発性の低い
高沸点溶媒で希釈した液状樹脂を使用した。回路基板４
上の所定部に塗布した半導体素子１を搭載後、１２０℃
で２時間程度の熱処理を行い、ＢＣＡ溶媒を蒸発消失さ
せて室温に戻すことにより、接着強度が出現した。この
樹脂を再度１００℃程度まで温度をあげると、一部液状
化して接着強度がなくなる。なお、熱可塑性樹脂として
ホットメルト型の熱可塑性ポリイミド樹脂を使用するこ
ともできる。(Embodiment 5) Hereinafter, a fifth embodiment of the semiconductor device of the present invention will be described. In the present embodiment, as the electrical insulating resin A8 in the first embodiment, as the thermoplastic resin, a polyimide resin is butyl.
A liquid resin diluted with a low-volatile high-boiling solvent such as carbitol acetate (BCA) was used. Circuit board 4
After mounting the semiconductor element 1 applied to the predetermined portion above,
At about 2 hours, the BCA solvent was evaporated and returned to room temperature, and the adhesive strength appeared. When the temperature of the resin is raised again to about 100 ° C., the resin is partially liquefied and the adhesive strength is lost. In addition, a hot melt type thermoplastic polyimide resin can also be used as the thermoplastic resin.

【００３６】このような構成において、絶縁樹脂Ｂ９注
入前の電気的検査の結果、不良と判明すれば加熱した上
で極めて微小な力を加えることにより半導体素子１を取
り外すことができるため、回路基板４等の他の部材に与
えるダメージは少なくてすむ。このように、絶縁樹脂Ａ
８に熱可塑性樹脂を用いることにより、容易かつ極めて
微小な力を加えるだけで不良半導体素子の取り外しを行
うことができるので、本発明の半導体装置の製造工程中
において、より簡単で確率の高い半導体素子交換が行え
る。In such a configuration, if it is determined that the semiconductor element 1 is defective as a result of an electrical inspection before injecting the insulating resin B9, the semiconductor element 1 can be removed by applying a very small force after heating. Damage to other members such as 4 is small. Thus, the insulating resin A
By using a thermoplastic resin for the semiconductor device 8, a defective semiconductor element can be removed easily and by applying only a very small force. Element exchange can be performed.

【００３７】（実施の形態６）以下本発明の半導体装置
の第６の実施形態について説明する。本実施形態におい
ては、第１の実施形態における絶縁樹脂Ａ８として、紫
外線照射及び加熱の両方の処理を行うことにより完全に
硬化するタイプの樹脂を用いた構成としている。完全に
硬化するタイプの樹脂としては、例えば主剤の樹脂がウ
レタン系変性アクリレートで、硬化剤としては変性ビス
フェノールＡ型アクリレートとポリエーテルアクリレー
トの組成物である。この樹脂の硬化条件としては、中心
波長が３６５ｎｍの紫外線光を７５００ｍＪ／ｃｍ2 程
度照射した後、１５０℃で１０分程度の熱処理で完全に
硬化する。(Embodiment 6) Hereinafter, a sixth embodiment of the semiconductor device of the present invention will be described. In the present embodiment, as the insulating resin A8 in the first embodiment, a type of resin that is completely cured by performing both the ultraviolet irradiation and the heating is used. As a completely hardening type resin, for example, a resin of a main component is a urethane-based modified acrylate, and a curing agent is a composition of a modified bisphenol A type acrylate and a polyether acrylate. The curing condition of this resin is that the resin is irradiated with ultraviolet light having a central wavelength of 365 nm at about 7500 mJ / cm 2 and then completely cured by a heat treatment at 150 ° C. for about 10 minutes.

【００３８】このような構成において、半導体素子１を
未硬化の絶縁樹脂Ａ１２を挟んで回路基板５上の所定位
置に配置して加圧した後、導電性接着剤６が硬化するま
で加熱する。この際、絶縁樹脂Ａ８は紫外線照射されて
おらず、硬化としては不十分な状態である。従って、こ
の後の電気的検査の結果、不良と判明すれば容易にかつ
微小な力を加えるだけで特に加熱をしなくても半導体素
子１を取り外すことができる。また、良品である場合は
半導体素子１と回路基板５の隙間部より必要量の紫外線
を絶縁樹脂Ａ８に照射して完全硬化を行う。このよう
に、絶縁樹脂Ａ８に紫外線照射及び加熱の併用処理によ
り完全硬化するタイプの樹脂を用いた構成としたことに
より、本発明の半導体装置の製造工程中において、特に
加熱を必要とせず、微小な力を加えるだけで容易に不良
半導体素子の取り外しを行うことができる。In such a configuration, the semiconductor element 1 is placed at a predetermined position on the circuit board 5 with the uncured insulating resin A12 interposed therebetween, and after being pressurized, heated until the conductive adhesive 6 is cured. At this time, the insulating resin A8 is not irradiated with ultraviolet rays, and is in an insufficiently cured state. Therefore, if it is determined that the semiconductor element 1 is defective as a result of the subsequent electrical inspection, the semiconductor element 1 can be easily removed by applying only a small force without heating. In the case of a non-defective product, a required amount of ultraviolet rays is irradiated to the insulating resin A8 from the gap between the semiconductor element 1 and the circuit board 5 to perform complete curing. As described above, since the insulating resin A8 is made of a type of resin that is completely cured by a combination of ultraviolet irradiation and heating, no special heating is required during the manufacturing process of the semiconductor device of the present invention. The defective semiconductor element can be easily removed simply by applying an excessive force.

【００３９】（実施の形態７）以下本発明の半導体装置
の第７の実施形態について図４を用いて説明する。本実
施形態において、絶縁樹脂Ａ８は回路基板５の構成材料
とした。すなわち、回路基板５はシート状のガラス繊維
を補強材とし、これにビスフェノールＡ系エポキシ樹脂
（硬化剤としてアミン、酸無水物を用いる）を含浸した
ものである。また電気絶縁樹脂Ａ８は回路基板５のエポ
キシ樹脂の一部である。(Embodiment 7) A semiconductor device according to a seventh embodiment of the present invention will be described below with reference to FIG. In the present embodiment, the insulating resin A8 is used as a constituent material of the circuit board 5. That is, the circuit board 5 is a sheet-like glass fiber as a reinforcing material, which is impregnated with a bisphenol A-based epoxy resin (an amine or an acid anhydride is used as a curing agent). The electric insulating resin A8 is a part of the epoxy resin of the circuit board 5.

【００４０】本実施形態においてその製造方法は、半導
体素子１を回路基板５上に実装する際、先ず加熱ステー
ジ１１の表面形状を湾曲としたり加圧量等を適切にした
りすることで、半導体素子１の突起電極３及び回路基板
５の変形を起こし、必要量の半導体素子１の中央部付近
の表面と回路基板５の表面を密着させる。次に、加熱し
て回路基板５の密着面の樹脂を樹脂を軟化させた後、加
熱をゆるめると固化して接着力が出現するので、この部
分の樹脂が絶縁樹脂Ａ８としての機能を果たす。この
際、加熱は半導体素子１側からの方を強く行うことで、
回路基板５全体の中では、回路基板５の密着面に集中し
て熱が伝わるので、条件を適切とすることで樹脂の軟化
は密着面のみに発生するので、回路基板５の品質を損な
うことはない。その後、絶縁樹脂Ｂ９を充填して半導体
装置とする。このようにして得られた半導体装置は、別
途絶縁樹脂Ａ８を用意しなくても良いので、材料及び工
程が省略できる。また、実装の際に変形を利用するの
で、基板の平面精度や突起電極の高さばらつきが矯正さ
れるので、確実に突起電極が電極端子と当接した状態と
するため、より信頼性の高い接続がなされる。従って、
本発明の半導体装置において、生産コストが低減すると
ともに電気的接続の信頼性も向上する。In the present embodiment, when the semiconductor element 1 is mounted on the circuit board 5, the surface shape of the heating stage 11 is first made to be curved or the amount of pressure is appropriately adjusted. The deformation of the protruding electrode 3 and the circuit board 5 is caused, and a required amount of the surface of the semiconductor element 1 near the center and the surface of the circuit board 5 are brought into close contact with each other. Next, after heating to soften the resin on the contact surface of the circuit board 5, the resin is solidified when the heating is loosened and an adhesive force appears, so that the resin at this portion functions as the insulating resin A8. At this time, heating is performed more strongly from the semiconductor element 1 side,
In the entire circuit board 5, heat is concentrated on the contact surface of the circuit board 5, and the resin is softened only on the contact surface by setting appropriate conditions, so that the quality of the circuit board 5 is impaired. There is no. After that, the semiconductor device is completed by filling the insulating resin B9. The semiconductor device obtained in this manner does not require the separate preparation of the insulating resin A8, so that the materials and steps can be omitted. In addition, since deformation is used at the time of mounting, the planar accuracy of the substrate and the variation in height of the protruding electrodes are corrected, so that the protruding electrodes are reliably brought into contact with the electrode terminals, so that higher reliability is achieved. A connection is made. Therefore,
In the semiconductor device of the present invention, the production cost is reduced and the reliability of the electrical connection is improved.

【００４１】[0041]

【発明の効果】以上のように本発明の半導体装置は、回
路基板上の所定の位置に半導体素子をフェースダウン方
式にて実装した半導体装置において、その電気的接合は
半導体素子のアルミ電極端子部に形成した導電性金属材
料からなる突起電極とこれに接する導電性接着剤からな
る結合層を介して行われるが、このような構成の半導体
装置において、前記半導体素子と回路基板間の隙間部全
体は、半導体素子面の中心部付近で前記結合層に到達し
ない領域に位置する絶縁樹脂Ａと、前記絶縁樹脂Ａを外
縁状に取り囲んだ領域に位置する絶縁樹脂Ｂにより充填
されていることを具備し、絶縁樹脂Ａの硬化処理が施さ
れた後に絶縁樹脂Ｂが注入された事を特徴とするもの
で、導電性接着剤が回路基板の電極端子と接着硬化した
後に、絶縁樹脂Ｂにより結合層が存する領域が充填され
るため、導電性接着剤が押し流されたり、あるいは導電
性接着剤と電極端子の接着界面に絶縁樹脂が入り込んだ
りすることがなくなるので、これらの要因による接続不
良は発生しなくなる。また、絶縁樹脂Ａの材料及び量を
最適化することで、接着強度を自由に設定できるので、
絶縁樹脂Ｂ充填までに要する必要な強度を保ち、かつ不
良と判明した半導体素子を簡単に取り外すことが可能な
範囲に設定することで、電気検査の実施と不良半導体素
子の取り替えが可能となる。As described above, according to the semiconductor device of the present invention, in a semiconductor device in which a semiconductor element is mounted at a predetermined position on a circuit board by a face-down method, the electrical connection is made to the aluminum electrode terminal of the semiconductor element. This is performed via a protruding electrode made of a conductive metal material formed on the substrate and a bonding layer made of a conductive adhesive in contact with the protruding electrode. In a semiconductor device having such a configuration, the entire gap between the semiconductor element and the circuit board is formed. Is filled with an insulating resin A located in a region near the center of the semiconductor element surface and not reaching the bonding layer, and an insulating resin B located in a region surrounding the insulating resin A in an outer peripheral shape. Then, the insulating resin B is injected after the insulating resin A is cured, and after the conductive adhesive is adhesively hardened to the electrode terminals of the circuit board, the insulating resin B is applied to the insulating resin B. Since the area where the bonding layer exists is filled, the conductive adhesive is not washed out or the insulating resin does not enter the bonding interface between the conductive adhesive and the electrode terminal, so connection failure due to these factors is prevented. No longer occurs. Also, by optimizing the material and amount of the insulating resin A, the adhesive strength can be freely set,
By maintaining the necessary strength required to fill the insulating resin B and setting the semiconductor element determined to be defective to a range in which the semiconductor element can be easily removed, it is possible to perform an electrical inspection and replace the defective semiconductor element.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の第１の実施形態における半導体装置
の平面図である。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

【図２】 図１のＩ−Ｉ線の断面図である。FIG. 2 is a cross-sectional view taken along line II of FIG.

【図３】 本発明の第１の実施形態の製造方法を説明す
る半導体装置の断面図である。FIG. 3 is a cross-sectional view of the semiconductor device illustrating a manufacturing method according to the first embodiment of the present invention.

【図４】 本発明の第７の実施形態における半導体装置
の断面図である。FIG. 4 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.

【図５】 従来の半導体装置の平面図である。FIG. 5 is a plan view of a conventional semiconductor device.

【図６】 図５のII−II線の断面図である。FIG. 6 is a sectional view taken along line II-II of FIG.

【図７】 従来の半導体装置の製造方法を説明するため
の断面図である。FIG. 7 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

１，１０１ 半導体素子 ２，１０２ アルミ電極端子 ３，１０３ 突起電極 ４，１０４ 回路基板 ５，１０５ 電極端子 ６，１０６ 導電性接着剤 ７，１０７ 電気的結合層 ８ 絶縁樹脂Ａ ９ 絶縁樹脂Ｂ １０８ 絶縁樹脂 １０，１１０ 加圧加熱ヘッド １１，１１１ 加熱ステージ １２ 未硬化の絶縁樹脂Ａ １１２ 未硬化の絶縁樹脂 DESCRIPTION OF SYMBOLS 1, 101 Semiconductor element 2, 102 Aluminum electrode terminal 3, 103 Projection electrode 4, 104 Circuit board 5, 105 Electrode terminal 6, 106 Conductive adhesive 7, 107 Electrical coupling layer 8 Insulating resin A 9 Insulating resin B 108 Insulation Resin 10, 110 Pressurized heating head 11, 111 Heating stage 12 Uncured insulating resin A 112 Uncured insulating resin

Claims (18)

【特許請求の範囲】[Claims] 【請求項１】 回路基板上の所定の位置に半導体素子を
フェースダウン方式で実装し、その電気的接合は半導体
素子のアルミ電極端子部に形成した導電性金属材料から
なる突起電極とこれに接する導電性接着剤からなる結合
層を介して行う半導体装置において、前記半導体素子と
回路基板間の隙間部全体が、半導体素子面の中心部付近
で前記結合層に到達しない領域に位置する絶縁樹脂Ａ
と、前記絶縁樹脂Ａを外縁状に取り囲んだ領域に位置す
る絶縁樹脂Ｂにより充填されていることを特徴とする半
導体装置。A semiconductor element is mounted in a predetermined position on a circuit board by a face-down method, and an electrical connection thereof is in contact with a protruding electrode made of a conductive metal material formed on an aluminum electrode terminal portion of the semiconductor element. In a semiconductor device performed through a bonding layer made of a conductive adhesive, the entirety of the gap between the semiconductor element and the circuit board is located in a region near the center of the semiconductor element surface and not reaching the bonding layer.
And an insulating resin B located in a region surrounding the insulating resin A in an outer peripheral shape. 【請求項２】 絶縁樹脂Ａ及びＢに無機フィラーを含
み、前記絶縁樹脂Ａに含まれる無機フィラーの量が、絶
縁樹脂Ｂに含まれる無機フィラーの量と比較して、それ
と同等かまたはそれ以下である請求項１に記載の半導体
装置。2. The insulating resins A and B contain an inorganic filler, and the amount of the inorganic filler contained in the insulating resin A is equal to or less than the amount of the inorganic filler contained in the insulating resin B. The semiconductor device according to claim 1, wherein 【請求項３】 絶縁樹脂Ａに含まれる無機フィラーの量
が０重量％を越え、８０重量％以下の範囲であり、絶縁
樹脂Ｂに含まれる無機フィラーの量が３０重量％以上８
０重量％以下の範囲である請求項１に記載の半導体装
置。3. The amount of the inorganic filler contained in the insulating resin A is more than 0% by weight and not more than 80% by weight, and the amount of the inorganic filler contained in the insulating resin B is 30% by weight or more and 8% by weight or less.
2. The semiconductor device according to claim 1, wherein the range is 0% by weight or less. 【請求項４】 無機フィラーが、重量平均粒子直径０．
０１〜１０μｍの範囲のシリカ、酸化チタン、アルミナ
を含む酸化化合物、窒化アルミを含む窒化化合物、炭化
珪素を含む炭化化合物、及び珪素化合物から選ばれる少
なくとも一つのフィラーである請求項１に記載の半導体
装置。4. The method according to claim 1, wherein the inorganic filler has a weight average particle diameter of 0.1.
2. The semiconductor according to claim 1, wherein the semiconductor is at least one filler selected from the group consisting of silica, titanium oxide, an oxide compound containing alumina, a nitride compound containing aluminum nitride, a carbide compound containing silicon carbide, and a silicon compound in the range of 01 to 10 μm. apparatus. 【請求項５】 絶縁樹脂Ａが、エポキシ樹脂、ポリイミ
ド樹脂、アクリル樹脂、ユリア樹脂、ポリウレタン樹脂
から選ばれる少なくとも一つの樹脂で、かつ絶縁樹脂Ｂ
が、エポキシ樹脂、ポリイミド樹脂、アクリル樹脂、ユ
リア樹脂、ポリウレタン樹脂を含む架橋型反応性樹脂か
ら選ばれる少なくとも一つの樹脂である請求項１に記載
の半導体装置。5. The insulating resin A is at least one resin selected from an epoxy resin, a polyimide resin, an acrylic resin, a urea resin, and a polyurethane resin.
2. The semiconductor device according to claim 1, wherein the resin is at least one resin selected from a cross-linkable reactive resin including an epoxy resin, a polyimide resin, an acrylic resin, a urea resin, and a polyurethane resin. 【請求項６】 絶縁樹脂Ａが、Ｂステージ（半硬化また
は部分硬化）特性を有する硬化性樹脂シートである請求
項１に記載の半導体装置。6. The semiconductor device according to claim 1, wherein the insulating resin A is a curable resin sheet having B-stage (semi-cured or partially cured) characteristics. 【請求項７】 絶縁樹脂Ａが、熱可塑性の電気絶縁性樹
脂である請求項１に記載の半導体装置。7. The semiconductor device according to claim 1, wherein the insulating resin A is a thermoplastic electric insulating resin. 【請求項８】 絶縁樹脂Ａが、紫外線照射及び加熱の両
方で完全に硬化する樹脂である請求項１に記載の半導体
装置。8. The semiconductor device according to claim 1, wherein the insulating resin A is a resin that is completely cured by both ultraviolet irradiation and heating. 【請求項９】 回路基板を構成する材料が、絶縁樹脂Ａ
と同じ種類の樹脂材料である請求項１に記載の半導体装
置。9. The circuit board is made of an insulating resin A
The semiconductor device according to claim 1, wherein the semiconductor device is a resin material of the same type as that of the semiconductor device. 【請求項１０】 回路基板上の所定の位置に半導体素子
をフェースダウン方式にて実装し、その電気的接合は半
導体素子のアルミ電極端子部に形成した導電性金属材料
からなる突起電極とこれに接する導電性接着剤からなる
結合層を介して行う半導体装置の製造方法において、前
記半導体素子と回路基板間の隙間部全体は、半導体素子
面の中心部付近で前記結合層に到達しない領域に位置す
る絶縁樹脂Ａと、前記絶縁樹脂Ａを外縁状に取り囲んだ
領域に位置する絶縁樹脂Ｂにより充填し、かつ前記絶縁
樹脂Ａを硬化処理した後に、前記絶縁樹脂Ｂを注入する
ことを特徴とする半導体装置の製造方法。10. A semiconductor element is mounted at a predetermined position on a circuit board by a face-down method, and an electrical connection between the semiconductor element and a protruding electrode made of a conductive metal material formed on an aluminum electrode terminal portion of the semiconductor element is provided. In the method of manufacturing a semiconductor device through a bonding layer made of a conductive adhesive that is in contact with the semiconductor device, the entire gap between the semiconductor element and the circuit board is located in a region near the center of the semiconductor element surface and not reaching the bonding layer. And filling the insulating resin A with an insulating resin B positioned in a region surrounding the insulating resin A in an outer edge shape, and curing the insulating resin A, and then injecting the insulating resin B. A method for manufacturing a semiconductor device. 【請求項１１】 絶縁樹脂Ａ及びＢが、未硬化時では絶
縁樹脂Ｂの流動性の方が絶縁樹脂Ａより良好である請求
項１０に記載の半導体装置の製造方法。11. The method according to claim 10, wherein when the insulating resins A and B are not cured, the fluidity of the insulating resin B is better than that of the insulating resin A. 【請求項１２】 絶縁樹脂Ａに含まれる無機フィラーの
量が０重量％を越え、８０重量％以下の範囲であり、絶
縁樹脂Ｂに含まれる無機フィラーの量が３０重量％以上
８０重量％以下の範囲である請求項１０に記載の半導体
装置の製造方法。12. The amount of the inorganic filler contained in the insulating resin A is more than 0% by weight and not more than 80% by weight, and the amount of the inorganic filler contained in the insulating resin B is not less than 30% by weight and not more than 80% by weight. The method of manufacturing a semiconductor device according to claim 10, wherein 【請求項１３】 無機フィラーが、重量平均粒子直径
０．０１〜１０μｍの範囲のシリカ、酸化チタン、アル
ミナを含む酸化化合物、窒化アルミを含む窒化化合物、
炭化珪素を含む炭化化合物、及び珪素化合物から選ばれ
る少なくとも一つのフィラーである請求項１０に記載の
半導体装置の製造方法。13. An inorganic filler comprising silica, titanium oxide, an oxide compound containing alumina, a nitride compound containing aluminum nitride having a weight average particle diameter of 0.01 to 10 μm,
The method for manufacturing a semiconductor device according to claim 10, wherein the method is at least one filler selected from a carbide compound containing silicon carbide and a silicon compound. 【請求項１４】 絶縁樹脂Ａが、エポキシ樹脂、ポリイ
ミド樹脂、アクリル樹脂、ユリア樹脂、ポリウレタン樹
脂から選ばれる少なくとも一つの樹脂で、かつ絶縁樹脂
Ｂが、エポキシ樹脂、ポリイミド樹脂、アクリル樹脂、
ユリア樹脂、ポリウレタン樹脂を含む架橋型反応性樹脂
から選ばれる少なくとも一つの樹脂である請求項１０に
記載の半導体装置の製造方法。14. The insulating resin A is at least one resin selected from an epoxy resin, a polyimide resin, an acrylic resin, a urea resin, and a polyurethane resin, and the insulating resin B is an epoxy resin, a polyimide resin, an acrylic resin,
The method for manufacturing a semiconductor device according to claim 10, wherein the resin is at least one resin selected from a urea resin and a cross-linkable reactive resin including a polyurethane resin. 【請求項１５】 絶縁樹脂Ａが、Ｂステージ（半硬化ま
たは部分硬化）特性を有する硬化性樹脂シートである請
求項１０に記載の半導体装置の製造方法。15. The method according to claim 10, wherein the insulating resin A is a curable resin sheet having B-stage (semi-cured or partially cured) characteristics. 【請求項１６】 絶縁樹脂Ａが、熱可塑性の電気絶縁性
樹脂である請求項１０に記載の半導体装置の製造方法。16. The method for manufacturing a semiconductor device according to claim 10, wherein the insulating resin A is a thermoplastic electric insulating resin. 【請求項１７】 絶縁樹脂Ａは、紫外線照射及び加熱の
両方の処理を行うことにより完全に硬化する樹脂である
請求項１０に記載の半導体装置の製造方法。17. The method for manufacturing a semiconductor device according to claim 10, wherein the insulating resin A is a resin which is completely cured by performing both the ultraviolet irradiation and the heating. 【請求項１８】 回路基板を構成する材料が、絶縁樹脂
Ａと同じ種類の樹脂材料である請求項１０に記載の半導
体装置の製造方法。18. The method of manufacturing a semiconductor device according to claim 10, wherein the material forming the circuit board is the same kind of resin material as the insulating resin A.
JP22888896A 1996-08-29 1996-08-29 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2957955B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001527131A (en) * 1997-12-19 2001-12-25 インフィネオン テクノロジース アクチエンゲゼルシャフト Plastic composite
DE10232636A1 (en) * 2002-07-18 2004-02-12 Delo Industrieklebstoffe Gmbh & Co. Kg Method and adhesive for flip-chip contacting
KR100711377B1 (en) 2004-03-18 2007-04-30 세이코 엡슨 가부시키가이샤 Method for manufacturing substrate joint body, substrate joint body and electrooptical device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001527131A (en) * 1997-12-19 2001-12-25 インフィネオン テクノロジース アクチエンゲゼルシャフト Plastic composite
DE10232636A1 (en) * 2002-07-18 2004-02-12 Delo Industrieklebstoffe Gmbh & Co. Kg Method and adhesive for flip-chip contacting
KR100711377B1 (en) 2004-03-18 2007-04-30 세이코 엡슨 가부시키가이샤 Method for manufacturing substrate joint body, substrate joint body and electrooptical device
CN100364042C (en) * 2004-03-18 2008-01-23 精工爱普生株式会社 Method of manufacturing substrate joint body, substrate joint body and electrooptical device
US7521797B2 (en) 2004-03-18 2009-04-21 Seiko Epson Corporation Method of manufacturing substrate joint body, substrate joint body and electrooptical device

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