JPH1074231A - Multiplication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fix the output signal level of a multiplied result by adjusting the gain of an AGC amplifier circuit corresponding to the output signals of a comparator. SOLUTION: A multiplication circuit 12 multiplies input signals from a terminal 10 and the terminal 11 and generates the multiplied result in the terminals 13 and 14. Also, a level shifting circuit 15 DC-level-shifts the output signal of a higher potential to a non-signal level among the two output signals of mutually opposite phases of the multiplication circuit 12. Then, the comparator 16 compares the levels of the output signal of the level shifting circuit 15 and the other output signal of the multiplication circuit 12. In such a manner, by DC-level-shifting the output signal of the higher potential to the non-signal level among the two output signals of the mutually opposite phases of the multiplication circuit 12, comparing the level with the other output signal of the multiplication circuit 12 and adjusting the gain of the AGC amplifier circuit corresponding to the result, the level of multiplied output signals is fixed without using an HPF requiring a capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplying device having a multiplying function for doubling the frequency of an input signal, and more particularly to a multiplying device having a constant output signal level as a result of multiplication.

[0002]

2. Description of the Related Art In a color signal processing circuit of a home-use VTR of the SECAM system, the level of a multiplied output signal may be constant. An AGC circuit may be used to keep the level of the multiplied output signal constant. FIG. 2 shows such a SEC
1 shows a multiplying device used in a color signal processing circuit of a home VTR of an AM system in which an output signal level of a multiplication result is constant.

The input signal from the input terminal (1) in FIG.
Applied to the AGC amplifier (2). AGC amplifier (2)
, Two output signals having the normal phase and the opposite phase are generated and applied to the multiplication circuit (3) for doubling the frequency of the input signal. The output signal of the multiplication circuit (3) having the frequency of the input signal doubled is led to the output terminal (4). On the other hand, the output signal of the multiplying circuit (3) is blocked by the direct current blocking HPF (5) and the direct current is regenerated to the voltage level of the power supply (6). The signal whose DC level has been reproduced is compared in level with the voltage of the reference power supply (8) by the comparator (7).

For example, if the signal level applied to the comparator (7) is large, an "L" level signal is generated from the comparator (7), and conversely, the comparator (7)
Is low, the comparator (7) generates an "H" level signal. Therefore, if the output signal of the comparator (7) is smoothed by the LPF (9), a detection output signal indicating the output signal level of the multiplier (3) is generated at the output terminal of the LPF (9). The detection output signal is applied to the AGC amplifier (2) as a gain control signal, input to the AGC amplifier (2), and adjusted so that the level of the signal output from the multiplication circuit (3) becomes constant.

Therefore, according to the apparatus shown in FIG. 2, the output signal level as a result of the multiplication can be made constant.
Note that the same signals having opposite phases are generated at the terminals (10) and (11) in FIG.

[0006]

However, in the apparatus shown in FIG. 2, an HPF for blocking the DC component of the detection signal is used.
(5) is required. The HPF (5) requires a large-capacity capacitor, and the presence of the capacitor is a problem in view of the fact that the device of FIG. For this reason, H
There has been a need for a multiplication device that does not require the PF (5) and has a constant output signal level as a result of the multiplication.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has an AGC amplifier circuit for amplifying an input signal and a multiplication circuit for doubling the frequency of an output signal of the AGC amplifier circuit. A level shift circuit for performing a DC level shift on one of the two output signals having the opposite phases to each other and having a higher potential than a no-signal level, and an output signal of the level shift circuit and the multiplier circuit And a comparator for level comparison with the other output signal.

According to the present invention, a multiplying circuit for doubling the frequency of an input signal, an AGC amplifying circuit for amplifying an output signal of the multiplying circuit, and a multiplying circuit having two phases opposite to each other.
A level shift circuit that performs a DC level shift on an output signal having a higher potential than a no-signal level among the two output signals;
A comparator for comparing a level of an output signal of the level shift circuit with an output signal of the multiplication circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a multiplication device according to the present invention in which the output signal level of the multiplication result is made constant. (12) is a terminal (10) and an input from a terminal (11). A multiplication circuit for multiplying the signals and generating the multiplication results at terminals (13) and (14); (15) a potential having a potential with respect to a no-signal level among two output signals of the multiplication circuit (12) having phases opposite to each other; A level shift circuit for DC level shifting one high output signal, and a comparator (16) for comparing the level of the output signal of the level shift circuit (15) with the other output signal of the multiplier circuit (12).

The output signal of the comparator (16) is shown in FIG.
To the LPF (9). 1, the same circuit elements as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, it is assumed that a signal b changing to “L” level is applied to a terminal (10) and a signal a changing to “H” level is applied to a terminal (11). Signal a and signal b
Are the same signals with opposite phases.

In response to signal a, transistor (17) tends to turn on, and in response to signal b, transistor (1)
8) tends to be off. On the other hand, when the signal b changing to the “L” level at the terminal (10) is applied to the base of the transistor (19), a signal b1 is generated at the collector of the transistor (19). When the signal a at the terminal (11) that changes to the “H” level is applied to the base of the transistor (20), a signal a1 is generated at the collector of the transistor (20).

Therefore, a large current flows through the collector-emitter path of the transistor (21) and the collector-emitter path of the transistor (17). Therefore, the voltage of the terminal (14) decreases, and the signal b2 is generated. vice versa,
The current in the collector-emitter path of the transistor (22) decreases, the voltage at the terminal (13) increases, and the signal a2 is generated.

This will be described with reference to FIG. Now, the signal a in FIG. 1 is shown in a period T1 in FIG. FIG.
The signal a in (a) is like the signal a2 in FIG. At the same time, a signal b2 indicated by a dotted line in FIG. 3B is generated at the terminal (14) in FIG. Terminal (13) and terminal (1
Since the DC voltage of 4) is set to have the same level when there is no signal, the signal shown in FIG. 3B is generated.

Next, in a period T2 in FIG. 3, the transistor (17) tends to turn off in response to the signal a, and the transistor (18) tends to turn on in response to the signal b. Then, an operation similar to that of the transistors (21) and (22) is performed by the transistors (23) and (24), and a signal similar to that in the period T1 is generated in the period T2. The signal in FIG.
The frequency is twice as high as the signal of FIG. The signal a2 generated at the terminal (13) in FIG. 1 is supplied to the transistor (25) constituting the level shift circuit (15).
And the level is shifted by the diode (29), the resistors R1 and R2, and is generated at the terminal (26). The signal b2 generated at the terminal (14) is supplied to the level shift circuit (1
The level is shifted to the transistor (27) constituting 5) and is generated at the terminal (28).

Since the resistance ratio between the resistors R1 and R2 is set to be high, the description will be made on the assumption that the amplitude of the signal generated at the emitter of the transistor (25) and the amplitude of the signal generated at the terminal (26) are equal. . FIG. 3C shows a terminal (26).
A2 generated at the terminal (28) and the signal b generated at the terminal (28)
2 is shown. The signal a2 generated at the terminal (26) is level-shifted and goes down. When the signal a2 generated at the terminal (26) shown in FIG. 3C and the signal b2 generated at the terminal (28) are applied to the comparator (16), the output terminal (30) receives the signal shown in FIG. "H" level and "L"
A pulse that changes to a level is generated. In FIG. 3D, the “H” level period is long, and the “L” level period is a short pulse. The ratio between the "H" level and the "L" level is a detection output signal indicating the amplitude of the input signal.

This will be described with reference to FIG. FIG.
(A) shows the same frequency as in FIG. 3 (a) but with a reduced level. When the input signal of FIG. 4A is applied to the terminals (10) and (11) of FIG.
The signal of FIG. 4B is generated at the terminals (13) and (14) of (2). The signal of FIG. 4B is level-shifted by the level shift circuit (15) as in the case of FIG.
Are generated at the terminal (26) and the terminal (28).

The signal in the solid line and the dotted line in FIG. 4C has a shorter intersecting period than that in FIG. 3C. As a result, a pulse that changes between the “H” level and the “L” level in FIG. 4D is generated at the output terminal (30). FIG. 4D shows a pulse having a shorter “H” level period and a longer “L” level period as compared with FIG. 3D. The difference between the lengths of the “H” level period and the “L” level period is the amplitude information.

FIG. 3 (d) and FIG.
The signal (d) is applied to the LPF (9) in FIG. 2 and smoothed, so that a different DC voltage is obtained depending on the difference in pulse width. Therefore, according to the apparatus of FIG. 1, the level of the multiplied output signal can be kept constant without using the HPF that requires a capacitor.

The level shift method shown in FIG. 1 is as follows.
Instead of using diodes, resistors R1 and R2 may be used. In this case, level attenuation occurs simultaneously with the level shift. However, even if the level attenuation occurs, there is no problem in the detection operation. The set amplitude of the AGC can be changed according to the shift amount of the level shift.

[0020]

As described above, according to the present invention, one of the two output signals of the multiplication circuit having the opposite phase to each other has a higher DC potential than the non-signal level, and performs a DC level shift to multiply the output signal. Level comparison with the other output signal of the circuit is performed, and the gain of the AGC amplifier circuit is adjusted according to the result, so that the level of the multiplied output signal is kept constant without using an HPF requiring a capacitor. Can be

Further, according to the present invention, the set amplitude of AGC can be changed according to the shift amount of the level shift, so that the set amplitude can be easily changed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a multiplication device according to the present invention.

FIG. 2 is a circuit diagram showing a conventional multiplication device.

FIG. 3 is a waveform diagram for describing the present invention.

FIG. 4 is a waveform chart for explaining the present invention.

[Explanation of symbols]

 (2) AGC amplifier (12) Multiplication circuit (15) Level shift circuit (16) Comparator

Claims (4)

[Claims] 1. An AGC amplifier circuit for amplifying an input signal, a multiplier circuit for doubling the frequency of an output signal of the AGC amplifier circuit, and a non-signal output signal of two output signals of opposite phases of the multiplier circuit. A level shift circuit that performs a DC level shift on one output signal having a higher potential than a level, and a comparator that compares a level of the output signal of the level shift circuit with the other output signal of the multiplier circuit;
A multiplication device wherein the gain of the AGC amplifier circuit is adjusted according to an output signal of the comparator. 2. A multiplying circuit for doubling the frequency of an input signal; an AGC amplifying circuit for amplifying an output signal of the multiplying circuit;
A level shift circuit for performing a DC level shift on an output signal having a higher potential than a no-signal level; and a comparator for comparing a level of an output signal of the level shift circuit with an output signal of the multiplier circuit. A multiplication device wherein a gain of the AGC amplifier circuit is adjusted according to a signal. 3. A multiplying circuit for doubling the frequency of an input signal, an AGC amplifying circuit for amplifying an output signal of the multiplying circuit, and an output signal of the multiplying circuit having two phases opposite to each other.
A level shift circuit that performs a DC level shift on an output signal having a higher potential than a no-signal level, a comparator that compares the output signal of the level shift circuit with the output signal of the multiplier circuit, With a smoothing LPF,
A multiplication device wherein the gain of the AGC amplifier circuit is adjusted according to the output signal of the LPF. 4. An AGC amplifier circuit for amplifying an input signal, a multiplying circuit for doubling the frequency of an output signal of the AGC amplifying circuit, and a non-signal among two output signals having opposite phases of the multiplying circuit. A level shift circuit that performs a DC level shift on one output signal having a higher potential than a level, a comparator that compares a level of an output signal of the level shift circuit with another output signal of the multiplier circuit, and an output of the comparator. And an LPF for smoothing the signal.
A multiplication device wherein the gain of the AGC amplifier circuit is adjusted according to the output signal of the LPF.