JPH1070549A - Atm cell making and de-cell making device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM cell making and de-cell making device preventing an ATM cell making and de-cell making device from overflow/underflow even when the step-out of a data frame is generated. SOLUTION: When an abnormality monitoring means 2 detects the abnormality of the frame pulse period of STM data, a reading control means 5 reads an ATM cell at reading intervals at a normal time from a cell making buffer 1 in which STM data is written by a writing control means 4, and an abnormality processing means 3 maps an alarming cell to this read ATM cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronou).
s Transfer Mode) The present invention relates to a cell / decellularization device.

[0002] This ATM cell / decellularization apparatus employs a cladding method for dividing CBR (Constant Bit Rate) data handled in a synchronous transfer mode (STM) network and transmitting the data to an ATM network. This is an application of a so-called ATM cell forming method and a decellularizing method of multiplexing ATM cells received from an ATM network to CBR data for transmission to an STM network.

[0003] CBR data refers to B-ISDN (Broadba
nd aspects of Integrated Service Digital Network)
Fixed rate (CBR) service and variable rate (VBR) service are classified into two types in terms of communication speed.
The service is used to realize a fixed-rate service.

[0004] Fixed speed service is communication in which information flows over a line at a constant speed. N-ISDN (Narrowban
d aspects of ISDN) 64-1536 / 1920 / Kbps
Digital communication services are CBR within B-ISDN.
Treated as a service. Whether the service speed can be set arbitrarily, for example, at 42.195 Kbps, or whether a step is provided at an integer multiple of 64 Kbps, is an issue for the future. It should be noted that the digital 2.
The speed of the next group is also treated as one of the steps of the CBR service.

[0005]

2. Description of the Related Art In a conventional ATM cell system, S
The CBR data sent from the TM network is temporarily stored in the cell buffer, and is read out by the ATM network. When a CBR data frame or multi-frame is abnormal, an alarm signal indicating the abnormality is output to the CB.
AT is different from the line through which the R data is transmitted.
M network was notified.

[0006] In the conventional ATM cell decellularization method, the STM network is connected to the AT cell transmitted from the ATM network.
M cells are temporarily stored in a decellularization buffer and read out in accordance with the STM cycle. At this time, by monitoring all of the received ATM cells, the ATM network cells are deflected back and forth and decellularities caused by disturbances in the STM network are observed. Monitoring of the overflow / underflow of the structured buffer.

[0007] The overflow refers to a state in which the cell exceeds the buffer storage capacity. In this case, a state occurs in which the cell is not stored in the buffer device, so that proper data cannot be read. Underflow is a state where the buffer storage amount of a cell becomes zero. In this case, even though the cell is not stored in the buffer device, some data is read out, so that proper data reading is performed. You cannot do it.

[0008]

In the above-described conventional ATM cellization / decellulation method, if a cycle abnormality occurs in a frame or multiframe of CBR data, the cycle of writing CBR data to the celling buffer changes. However, the read cycle of ATM cells from the cell buffer is changed. For this reason, the transmission interval of the ATM cell changes as compared with the normal case, and the data accumulation amount of the decellulation buffer on the receiving side of the ATM cell changes in the overflow or underflow direction, and can be absorbed by the decellulation buffer. There is a problem that the fluctuation absorption width is exceeded.

[0009] Further, when data composed of CBR data frames or multi-frames is out of synchronization, if the ATM cells are transmitted in a phase with the out-of-synchronization and transmitted, the receiving side of the ATM cells also receives the data at the time of the previous transmission. There is a problem that out-of-synchronization causes out-of-synchronization, and the decellularized buffer shifts in a buffer overflow or buffer underflow direction.

Further, when the frame phase is abnormally restored due to a period abnormality, a case may occur in which the previous phase is different from the newly synchronized phase after the recovery. In this case, data is read continuously from the deceleration buffer with a new phase, but the value of the counter for counting and monitoring the accumulated data amount of the deceleration buffer is equal to the actually readable data amount. Differently, the remaining data amount does not match, and there is a problem that even if there is no more data to be read out in the decellularization buffer, deceleration is continued without generating an underflow alarm.

[0011] The present invention has been made in view of such a point, and even if the data frame is out of synchronization, the AT is performed.
It is an object of the present invention to provide an ATM celling / de-celling apparatus which can prevent an M-cell / de-celling buffer from overflowing / underflowing.

[0012]

FIG. 1 shows the principle of the present invention. The ATM cellizing / decellulating apparatus shown in FIG. 1 includes a celling buffer 1 for storing STM data transmitted from a synchronous transfer mode network, an abnormality monitoring means 2 for detecting an abnormality in a frame pulse cycle of STM data, Write control means 4 for writing STM data to the cell buffer 1 in synchronization with the frame pulse; ATM cell read from the cell buffer 1 in synchronization with the cell frame pulse of the ATM cell in the asynchronous transfer mode network; Reading control means 5 for reading out ATM cells at a normal readout interval when an abnormality is detected in abnormality 2 and abnormality processing means for mapping alarm cells to ATM cells read out from cell buffer 1 when abnormality monitoring means 2 detects an abnormality. 3 is provided.

According to such a configuration, even when the period of the frame pulse of the STM data is abnormal, the ATM cells can be read at the normal read interval, so that the overflow / underflow of the cell buffer 1 is prevented. In addition, when a period abnormality occurs, an alarm cell for notifying the abnormality is mapped to the ATM cell, so that the period abnormality can be notified to the asynchronous transfer mode network.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of an ATM cell / decellularization apparatus according to the first embodiment of the present invention.

In the ATM cell / decellularization apparatus shown in FIG. 2, reference numeral 1 denotes a cell buffer, 2 denotes a frame pulse period abnormality monitoring unit, 3 denotes an abnormality processing unit, 4 denotes a writing control unit,
Is a read control unit.

The cell buffer 1 temporarily stores the CBR data D1 transmitted from an STM network (not shown) in order to be converted into ATM cells. The frame pulse period abnormality monitoring unit 2 is operated by a clock CK1 synchronized with the STM network, and monitors the period of the frame pulse FP1 of the CBR data D1 to monitor the period of the frame pulse FP1. When an abnormality is detected, an abnormality processing signal S1 is output to the abnormality processing unit 3, the write control unit 4, and the read control unit 5.

When the abnormal processing signal S1 is not supplied, that is, when the period of the frame pulse FP1 is normal, the write control unit 4 generates a write address and a write enable signal synchronized with the frame pulse FP1 and the clock CK1 to generate a cell. Control is performed to write the CBR data D1 into the buffer 1, and a write completion signal S2 is output to the read control unit 5 each time the CBR data D1 is written. Also, the abnormality processing signal S
When 1 is supplied, that is, when the cycle of the frame pulse FP1 is abnormal, the output of the write completion signal S2 to the read control unit 5 is not performed.

The read controller 5 writes a read address and a read enable signal synchronized with a cell frame pulse FP2 of the ATM cell C1 and a clock CK2 synchronized with an ATM network (not shown) when the abnormality processing signal S1 is not supplied. Generated when the completion signal S2 is input and generated as the cell buffer 1
From the ATM cell C1.

Further, when the abnormality processing signal S1 is supplied, the read address is set to a free run which does not depend on the write completion signal S2. In this case, although the address is not specified, the ATM cell C1 is read from the cellular buffer 1 in the same manner as in the normal state, and transmitted to the ATM network.

When the abnormal processing signal S1 is not supplied, the abnormal processing unit 3 only passes the ATM cell C1 read from the cell buffer 1, but when the abnormal processing signal S1 is supplied, the abnormal processing unit 3 outputs the ATM cell C1. The alarm cell is mapped to the payload and transmitted.

According to such a configuration, the CBR data D
Even when the period of one frame pulse FP1 is abnormal, it is possible to output the ATM cell C1 with the normal phase before the abnormality, so that the overflow / underflow of the cell buffer 1 can be prevented. In the event of an abnormality, it is possible to transfer an alarm cell indicating the abnormality.

When an alarm cell is received by the ATM network, the read control unit 5 receives the AT from the cell buffer 1.
By forcibly stopping the reading of the M cell C1, an underflow is forcibly generated in the decellularization buffer of the ATM network that receives the ATM cell C1, thereby realizing the alarm transfer to the lower order.

Next, an ATM cell forming / de-celling apparatus according to a second embodiment will be described with reference to FIG. However, in the second embodiment shown in FIG. 3, parts corresponding to the respective parts of the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 3, reference numeral 11 denotes a multiplex synchronization detection unit, and 12 denotes a write control unit, which comprises a data bit address generation unit 13 and an address multiplexing unit 14. Reference numeral 15 denotes a read control unit.

The multiplex synchronization detecting section 11 outputs the CBR data D1
In response to the frame pulse FP1 and the clock CK1 synchronized with the STM network, the multi-frame synchronization of the data B having the multi-frame configuration is performed among the data A and the data B each having a different frame configuration multiplexed in the CBR data D1, The frame phase information is stored in the data B address AD1.
As shown in FIG. 4, a frame pattern detection determination unit 18 and a data bit address generation unit 13, an address multiplexing unit 14, and a read control unit 15
Synchronization protection stage number counter 19 and first frame counter 2
0, the second frame counter 21, and the DPRAM (Dual
A multi-processing memory unit 22 using a Port RAM) and a selector (SEL) 23 are provided.

Referring now to FIG. 5, CBR data D1 in which data A and data B are multiplexed and ATM cell C1
A description will be given of the conversion into ATM cells / decellulation, which is a mutual conversion with the above.

As shown in FIG. 5, CBR data D1 is 1
The frame is 125 μs, and a pair of data A
And one channel CH including data B are multiplexed. That is, the first channel CH1 to the k-th channel C
Hk is multiplexed. Data A is 125 μ
s frames, data B is 125 μs n
The frame has a multi-frame configuration.

In the case where such CBR data D1 is converted into ATM cells, k channels multiplexed 125 μs × n frames are considered as one unit, and the number of channels adapted to the speed are mapped into one ATM cell. The channel is divided into j ATM cells # 1 to #j.

In converting the data A and the data B into ATM cells, as shown in FIG. 6, in the cell conversion of a plurality of channels into one ATM cell, the data A is transferred between times t5 and t10 and between times t10 and t10. As shown during t15, consecutive n frames are mapped to one ATM cell, but since data B forms a multi-frame as shown by CH1 to CHm, all channels CH
1 to CHm for each channel CH1 to CHm.
The mapping is performed for each CHm, and the phase is controlled and mapped.

That is, n frames 1F-nF between times t1-t6 of CH1, n frames 1F-nF between times t2-t7 of CH2, and n frames 1F-nF between times t3-t8 of CH3; ..., n between times t2 and t7 of CHm
The frames 1F to nF are in-phase and mapped to the first cell # 1, and the n frames 1F to nF of the CH1 from time t6 to t11, the n frames 1F to nF of the CH2 from time t7 to t12, and CH3 , N frames 1F to nF between times t8 and t13, and n frames 1F to nF between times t7 and t12 of CHm in phase with each other.
2, and thereafter similarly performs a process of sequentially mapping n frames 1F to nF of each of CH1 to CHm to cells.

In the description with reference to FIGS. 5 and 6, the description has been made with reference to the contents described in the prior application, Japanese Patent Application No. Hei 7-182864, “Asynchronous Transfer Apparatus”. Next, the multiplex synchronization detecting section 11 shown in FIG. 4 will be described.

The frame pattern detection / judgment section 18 determines the CBR according to the frame pulse FP1 and the clock CK1.
This is to detect the frame synchronization pattern of the multi-frame data B in the data D1 and determine whether the synchronization pattern is normal or abnormal.

For example, when one of the multi-frames of the data B has an n-frame configuration, the synchronization pattern 1 of the n-frame
For example, two consecutive detections of F to nF determine that one cycle of the multiframe is normal.
1 "is output. If 1F to nF are not detected twice consecutively, it is determined that an abnormality has occurred. At this time," 0 "is output.

The synchronization protection stage number counter 19 outputs a signal indicating multi-frame synchronization / out-of-synchronization by counting the number of synchronization protection stages according to the frame synchronization pattern detection determination result of the frame pattern detection determination unit 18. .

This is because a value obtained by counting "1" indicating the normality of the frame synchronization pattern is stored in the synchronization protection stage number count value storage area of the multiplex processing memory unit 22, and the stored feedback count value is stored next to the stored feedback count value. The input count value of “1” indicating normality is incremented, and this count value is overwritten in the synchronous protection stage number count value storage area of the memory unit 22.

Thereafter, similarly, the counting operation is performed until the count value becomes a predetermined number of synchronization protection stages, for example, “2”. When “0” indicating an abnormality (out of synchronization) is input during the counting, the count value is set to 0. And

The synchronization protection stage number counter 19 outputs a first selection signal for selecting the first count value output from the first frame counter 20 to the selector 23 during the counting operation, and the synchronization protection state is determined. When the synchronous state is restored from the second, a second selection signal for instantaneously selecting the second count value output from the second frame counter 21 is output.

First and second frame counters 20, 21
Is for counting the frame phase of a multi-frame. If the frame synchronization pattern detection determination result of the frame pattern detection determination unit 18 is "1" indicating normality,
Both counters 20 and 21 count "1". Here, the first frame counter 20 multiplexes via the selector 23 which selects the first count value output from the counter 20 when the synchronization signal is supplied. Processing memory unit 2
2 is stored in the first count value storage area, and the stored feedback count value is incremented by the next input count value of “1” indicating normality, and this count value is stored in the memory unit via the selector 23. 22 is overwritten on the first count value storage area.

Further, the second frame counter 21 stores the output second count value in the second count value storage area of the multiplex processing memory unit 22, and the next feedback count value is input to the stored feedback count value. The count value of “1” indicating normality is incremented, and this count value is overwritten in the second count value storage area of the memory unit 22.

The first count value which is sequentially incremented and stored in the first count value storage area of the memory unit 22 is output as an address B1 for data B which is frame phase information.

On the other hand, if the frame synchronization pattern detection determination result becomes "0" indicating an abnormality, that is, if synchronization is lost, the first frame counter 20 continues counting with the previous phase, and the second frame counter Reference numeral 21 is for frame counting for newly establishing synchronization.

For example, when an out-of-synchronization occurs at the timing shown by time t1 in FIG. 7, the first frame counter 20 continues the count operation with the previous frame phase, whereby the first count value becomes 1F, 2F,. It is continuously output with nF and the previous frame phase. On the other hand, the second frame counter 21 counts at the frame phase out of synchronization.

At this time, since the first selection signal is still output from the synchronization protection stage number counter 19, the selector 23 selects the first count value, and the selected first count value is stored in the multiplex processing memory unit 22. Is output as an address B1 for data B through Therefore, the data B address B1 is output at the frame phase before the synchronization is lost.

Thereafter, when the first synchronization protection is taken by the synchronization protection stage number counter 19 at the timing shown by the time t2, and the second synchronization protection is taken by the timing shown by the time t3, the synchronization is detected and the synchronization is restored. Therefore, at this time, the second selection signal is output from the synchronization protection stage number counter 19 to the selector 23 during the time t3 to t4.

As a result, the selector 23 selects the second count value 1F and outputs it to the multiplex processing memory unit 22. Therefore, the selector 23 overwrites the first count value storage area of the multiplex processing memory unit 22 and overwrites it. The second count value 1F is output as data B address B1. That is, a phase jump is performed at time t3.

Since the second count value 1F is also overwritten in the second count value storage area, the values in the first and second count value storage areas become the same value 1F. Accordingly, both counters 20 and 21 perform counting based on the feedback second count value of the memory unit 22 having the same value, so that both count values become equal, and thereafter both counters 20 and 21 similarly perform the counting operation. Do.

After the time t4, the first selection signal is output again from the synchronization protection stage number counter 19, so that the first count value is output as the data B address B1.
As a result, even after restoration, the first count value having the same phase as the frame phase before restoration is output from the multiplex processing memory unit 22 as the data B address B1.

Next, the data bit address generator 13 of the write controller 12 shown in FIG. 3 generates the data A address A1 from the CBR data D1 in accordance with the frame pulse FP1 and the clock CK1, and 14, and outputs a select signal S3 to the address multiplexing unit 14 when the data A address A1 is generated.

The address multiplexing unit 14 stores the data B address B1 output from the multiplex synchronization detecting unit 11 and the data A
The address A1 for data A is alternately multiplexed and output as a write address of the cell buffer 1; the address A1 for data A is output to the cell buffer 1 when the select signal S3 is supplied; B1
Is output.

The address A1 for data A and the address B1 for data B output from the write control unit 12 as described above.
, The data A and the data B of the CBR data D1 are alternately written to the cell buffer 1.

The read control unit 15 receives the cell frame pulse F
In response to P2 and the clock CK2 synchronized with the ATM network, an address for reading data A is output to the cell buffer 1 and, at the time of inputting the address B1 for data B,
An address for reading the data B is output, whereby the ATM cells C in which the data A and the data B are cellized are output.
1 is output to the ATM network.

According to the second embodiment described above, even if the frame synchronization is lost, the CBR is performed in the previous frame phase.
The data D1 can be mapped to the ATM cell C1, and the ATM cell can be transferred at the frame phase before the synchronization is lost.

Therefore, when the data composed of CBR data frames or multi-frames is out of synchronization as in the prior art, the ATM is shifted in phase with the out of synchronization.
When the cell is transmitted, the ATM cell receiving side loses synchronization due to the loss of synchronization at the time of the previous transmission, and the decellularization buffer overflows or overflows.
Transition to the underflow direction is eliminated.

Next, a description will be given of an ATM celling / decellulating apparatus according to a third embodiment with reference to FIG. However, in the third embodiment shown in FIG. 8, parts corresponding to the respective parts of the second embodiment shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 8, reference numeral 30 denotes a decellularized buffer, 31 denotes a write address generation unit, 32 denotes a read address generation unit, 33 denotes a read phase latch unit, and 34 denotes a capacity monitoring unit. It comprises a unit 35 and an up / down counter 36.

The decellularization buffer 30 temporarily stores the ATM cell C1 transmitted from the ATM network in order to decelerate it into CBR data D1. The write address generation unit 31 supplies the cell enable signal S5 transmitted when the ATM cell C1 is appropriate,
In response to the cell frame pulse FP2 of the cell C1 and the clock CK2 synchronized with the ATM network, a write address W1 and a write enable signal WE are output to the decellularization buffer 30 simultaneously with the write address W1, and the write enable signal is also output. WE is output to the counter control unit 35 of the capacity monitoring unit 34.

When the write enable signal WE and the write address W1 are input to the decellularization buffer 30, the ATM cell C1 is written and stored in the storage area of the address. This writing is instantaneous.

The read address generator 32 is provided with the capacity monitor 3
4 when the read permission signal S6 output from the up / down counter 36 is input, according to the frame pulse (or multi-frame pulse) FP2 of the CBR data D1 and the clock CK1 synchronized with the STM network in the second embodiment. When the address of data A is output, and when the address B1 for data B is output from the multiplex synchronization detecting unit 11 described in the second embodiment, the address B for data B is output.
1 and outputs both output addresses to the decellularization buffer 30 as the read address R1. At the same time, the read enable signal RE is output. The read enable signal RE is output to the counter control unit 35 and the read phase latch unit. 33.

When read enable signal RE and read address R1 are input to decellularization buffer 30, data A and data B of the ATM cell stored in the storage area of the address are multiplexed to form an STM network as CBR data D1. Output to

The time required to read the CBR data D1 from the decellularization buffer 30 requires a predetermined time while the time required to write the ATM cell C1 is instantaneous. The capacity monitoring unit 34 monitors the storage capacity of the decellularization buffer 30, and the counter control unit 35 of this component counts up / down counter 36 every time only the write enable signal WE is supplied. Each time only the read enable signal RE is supplied, a predetermined count value is counted down.
When the write enable signal WE and the read enable signal RE are both input, or when both are not input, control is performed to set an uncounted state.

In the up / down counter 36, a count value corresponding to the number of storage cells to be monitored in the decellularization buffer 30 is set in advance, and when the count value reaches the set count value, the read enable signal S6 is sent to the read address generation unit. 32.

As the set count value, for example, since one cell is 48 bytes, 48 counts for one cell are set, and one count value corresponds to one byte.

The read-out phase latch unit 33 has a read address R
The phase of the read enable signal RE having the same phase as 1 is compared with the phase of the data B address B1. If the two phases do not match, that is, the data B address B1 is synchronized with the phase as described in the second embodiment. When a phase jump that occurs upon restoration is indicated, a countdown enable signal S7 for clearing the up / down counter 36 is output. At the time of this clearing, the CBR data D1 accumulated in the deceleration buffer 30 is discarded.

The operation of the third embodiment having such a configuration will be described with reference to FIG. Assume that the initialization of the deceleration buffer 30 is completed between times t0 and t1 shown in FIG. 9 and that the first cell 1C is written into the deceleration buffer 30 at time t1. At this time, the up / down counter 36 counts up under the control of the counter control unit 35 according to the supply of the write enable signal WE.

When the count value of counter 36 becomes equal to the 48 count value of the set count value, read enable signal S6 is output to read address generating section 32, and read address R1 is sent to decellularization buffer 30, and time t2 The reading of the written cell 1C (CBR data D1) is started as shown in FIG.

During the reading, the second cell 2C is written into the decellularization buffer 30 as shown at time t3, and the reading of the first cell 1C is completed at the same time as shown at time t4. Is started, and the third cell 3 </ b> C is written into the decellularization buffer 30 during the reading as shown at time t <b> 5.

Here, assuming that there is a phase jump, the data B address B1
Is read out, the read phase latch unit 33 outputs a countdown enable signal S7 to the up / down counter 36 by detecting a phase mismatch between the data B address B1 and the read enable signal RE, As a result, the counter 36 is cleared as shown at time t6, and the cells 3 stored in the decellularization buffer 30 are cleared.
C is discarded.

Thereafter, at time t7, the fourth cell 1
When C is written, the up / down counter 36 counts up. When the count value of the counter 36 becomes equal to the set count value of 48,
The read permission signal S6 is output to the read address generator 32, the read address R1 is sent to the decellularization buffer 30, and the reading of the written cell 4C is started as shown at time t8. Thereafter, processing is performed in the same manner as described above.

According to the third embodiment described above, CB
When a period abnormality of the frame phase of the R data D1 occurs and the frame is restored again, and a case where the previous phase and the newly synchronized phase are different after the restoration (phase jump) occurs, as in the conventional case, the new phase is used. Data is continuously read from the deceleration buffer, and the counter value for counting and monitoring the amount of data stored in the deceleration buffer differs from the actually readable data amount, and the data remaining amount matches. In other words, even if there is no more data to be read out in the deceleration buffer, deceleration does not continue without generating an underflow alarm.

That is, it is possible to prevent reading even when data does not exist in the decellularization buffer, and to eliminate the transition in the buffer underflow direction. Further, in the configuration of the third embodiment shown in FIG. 8, when a phase jump occurs, the up / down counter 36 supplied with the countdown enable signal S7 output from the read-out phase latch unit 33 sets the previous phase to The count value corresponding to the number of cell bytes of the phase difference is down-counted, and only the remainder of the cell being read at this time is discarded from the decellularization buffer 30.

That is, as shown in FIG. 10 similar to FIG. 9 from time t0 to time t5, when there is a phase jump at time t6, the up / down counter 36 to which the countdown enable signal S7 has been input is supplied with the reference numeral 38. The count value corresponding to the number of cell bytes of the phase difference at the time of restoration from the previous phase is down-counted, and the remainder of the cell 2C being read in the decellularization buffer 30 is discarded. As a result, as shown at time t6, the cell 3C is read.

Therefore, even if a phase jump occurs, the cells stored in the decellularization buffer 30 can be decellularized without being discarded.

[0073]

As described above, according to the ATM cell forming / de-celling apparatus of the present invention, the ATM cell forming / de-celling buffer does not overflow / underflow even when the data frame is out of synchronization. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of an ATM cell forming / de-celling apparatus according to a first embodiment of the present invention.

FIG. 3 is a block diagram of an ATM cell forming / de-celling apparatus according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a multiplex synchronization detecting unit shown in FIG. 3;

FIG. 5 is an explanatory diagram of conversion between ATM cell conversion and decellularization.

FIG. 6 is an explanatory diagram of converting data A and B in CBR data into ATM cells.

FIG. 7 is an explanatory diagram of the operation of the multiplex synchronization detecting unit shown in FIG. 3 when synchronization is restored.

FIG. 8 is a block diagram of an ATM celling / decellulating apparatus according to a third embodiment of the present invention.

FIG. 9 is a diagram illustrating the operation of the ATM cell forming / de-cell forming apparatus shown in FIG. 8;

FIG. 10 is another operation explanatory view of the ATM cell forming / de-celling apparatus shown in FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cellular buffer 2 Abnormality monitoring means 3 Abnormality processing means 4 Writing control means 5 Reading control means

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhiro Uchida 3-22-8 Hakata-ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Inside Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Koichi Maeda Hakata-ku, Fukuoka City, Fukuoka Prefecture Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Takaaki Itose 3-22-8, Hakata Ekimae 3-chome, Hakata-ku, Fukuoka City, Fukuoka Prefecture (72) Inventor Kazuyuki Tajima 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yoshiro Takigawa 3-192-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. S transmitted from a synchronous transfer mode network
A cell buffer for storing TM data; abnormality monitoring means for detecting an abnormality in a frame pulse period of the STM data; and ST in the cell buffer in synchronization with the frame pulse.
Writing control means for writing M data; reading ATM cells from the cell buffer in synchronization with a cell frame pulse of the ATM cells in the asynchronous transfer mode network; ATM cell conversion comprising: read control means for reading an ATM cell; and abnormality processing means for mapping an alarm cell to the ATM cell read from the cell buffer when the abnormality monitoring means detects an abnormality. / Decelerator. 2. The system according to claim 1, wherein when said alarm cell is received by said asynchronous transfer mode network, said read control means is controlled to stop reading said ATM cell from said cellular buffer. Item 4. The ATM cell conversion / decellulation device according to Item 1. 3. S transmitted from a synchronous transfer mode network
A cell buffer for storing TM data; detecting multi-frame synchronization and out-of-synchronization of first data in a multi-frame configuration included in the STM data; Multiplex synchronization detecting means for outputting the first data write address at the phase at the time of restoration when synchronization is restored from the loss of synchronization, the first data write address, and the STM data included in the STM data. By alternately outputting a write address of second data other than the first data to the cell buffer, the STM
Write control means for writing data; outputting the first data read address to the cell buffer in synchronization with the cell frame pulse of the ATM cell in the asynchronous transfer mode network when the first data write address is input;
Read control means for reading an ATM cell in which first and second data are arranged from the cell buffer by outputting a second data read address in synchronization with the cell frame pulse when the first data write address is not input An ATM cell forming / de-celling apparatus comprising: 4. A decellularization buffer for storing ATM cells transmitted from an asynchronous transfer mode network, and writing the ATM cells to the decellularization buffer in synchronization with cell frame pulses of the ATM cells of the asynchronous transfer mode network. A write control means for outputting a first data read address in synchronization with a frame pulse of STM data in a synchronous transfer mode network when a read enable signal is supplied and a first data address is input;
By outputting the second data read address in synchronization with the frame pulse when the data address is not input, the first data of the multi-frame configuration and the second data other than the first data are multiplexed from the deceleration buffer. Read control means for reading as STM data; counting up when only a write enable signal is supplied at the time of writing the ATM cell; down counting when supplying a read enable signal at the time of reading the STM data;
When both the write and read enable signals are input or not input, the count becomes an uncounted state, and when counting up to a count value corresponding to a predetermined capacity of the deceleration buffer,
Capacity monitoring means for outputting the read enable signal; detecting multi-frame synchronization and out-of-synchronization of first data included in the STM data; Multiplex synchronization detecting means for outputting the first data address at the phase at the time of restoration when synchronization is restored from loss of synchronization; and when the phase at the time of restoration of the first data address differs from the phase of the read enable signal Reading phase latch means for outputting a count control signal for clearing the count value of the capacity monitoring means, and discarding the stored ATM cells in the decellularized buffer when the count value is cleared by the count control signal. An ATM cell forming / de-celling apparatus characterized by the above. 5. The first control circuit according to claim 1, wherein
The count value of the capacity monitoring means corresponding to the deceleration buffer capacity of the phase difference between before recovery and at the recovery time indicated by the data address is down-counted. At this time, only the remaining ATM cells being read from the deceleration buffer are read. 5. The ATM cell forming / de-celling apparatus according to claim 4, wherein is discarded.