JPH1070196A - Complementary semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a complementary semiconductor device to be enhanced in circuit speed and lessened in power consumption, by a method wherein a semiconductor substrate's part located under a first source region is kept lower in impurity concentration than the source-side part of an asymmetrical impurity diffused region. SOLUTION: In a semiconductor device 100, a P-type impurity diffusion layer 6 is so formed as not to cover all source diffusion layer 2. Therefore, a part of a semiconductor substrate 1 just under a source diffusion layer 2 is kept lower in impurity concentration than a source-side part of the P-type impurity diffusion layer 6. Generally, the speed of a semiconductor device is proportional to the product of the load capacitance and the reciprocal of the current. Therefore, even if a semiconductor device 100 is applied to a NAND CMOS circuit where a voltage is applied to a region between a source and a substrate, the semiconductor device is not lessened in circuit speed. The power consumption of a semiconductor device is proportional to a product of the load capacitance and the square of the applied voltage. Therefore, a semiconductor device 100 is low in power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary semiconductor device and a method of manufacturing the same, and more particularly to realizing miniaturization of a metal-oxide-semiconductor (MOS) semiconductor device.
The present invention relates to a complementary semiconductor device and a method for manufacturing the same, which can provide a highly reliable and high speed semiconductor integrated circuit operable with low power consumption.

[0002]

2. Description of the Related Art In recent years, in order to realize a VLSI with higher integration, an MO that can be used for such a VLSI has been developed.
The size of S-type semiconductor devices has been increasingly reduced.
As a result, currently available semiconductor devices are formed with a minimum size in the half-micron or sub-half-micron region. At the research level, a semiconductor device having a size on the order of a quarter-micron region or a sub-quarter-micron region has been prototyped.

However, when such a fine-sized device is formed, the electrical characteristics of such a device are likely to deteriorate due to the short channel effect and the hot carrier effect. Thereby, the reliability of the device is severely affected.

On the other hand, in order to develop VLSI technology which can be sufficiently applied to the expanding multimedia society, semiconductor devices must realize not only high-speed operation but also low power consumption.

In order to improve the resistance of the device to deterioration caused by the hot carrier effect and the short channel effect and to improve the driving capability, a MOS type semiconductor device having an asymmetric impurity profile in a channel has been proposed. For example, 1991 Symposiumon VLSI Technology, pp.1
13-114, a laterally doped channel (LDC) structure is proposed by T. Matsui et al.

FIG. 1 is a sectional view of a MOS semiconductor device 50 having an LDC structure.

The semiconductor device 50 includes an n-type high-concentration source diffusion layer 2 and an n-type high-concentration drain diffusion layer 3 formed on a semiconductor substrate 1, a gate oxide film 4 formed on the semiconductor substrate 1, A gate electrode 5 formed on the gate oxide film 4, a channel region between the source diffusion layer 2 and the drain diffusion layer 3, and a p-type high electrode provided inside the semiconductor substrate 1 under the source diffusion layer 2. And a concentration diffusion layer 6 ′. The p-type diffusion layer 6 'is characterized in that the impurity concentration monotonously decreases from the source side to the drain side.

In this structure, the resistance of the device to the short channel effect can be improved by increasing the impurity concentration of the p-type diffusion layer 6 'on the source side.
Further, by lowering the impurity concentration of the p-type diffusion layer 6 'on the drain side, a high electric field generated near the drain can be reduced, thereby suppressing the generation of hot carriers. Therefore, the conventional low-doped drain (LDD) structure is not required for the semiconductor device 50,
Thereby, a high driving capability is achieved.

[0009]

However, this structure,
It is not suitable for MOS type semiconductor devices formed in a region having a size on the order of quarter microns or less. This is an MO having the LDC structure shown in FIG.
This is because the S-type semiconductor device 50 has the following problems.

First, a p-type high concentration diffusion layer is formed below the source diffusion layer, and the impurity concentration of the p-type diffusion layer is 1 × 10 ¹⁸ in order to suppress the short channel effect.
cm ^-3 or more. As a result, p between the source and the substrate
The parasitic capacitance of the n-junction undesirably increases as compared with the conventional structure.

In general, the speed of a MOS semiconductor device (the speed of the entire circuit) is proportional to the product obtained by multiplying the reciprocal of the saturation current value and the load capacitance together. Therefore,
As in the case of the semiconductor device 50 shown in FIG. 1 having an LDC structure, such a semiconductor device having a large parasitic capacitance at the pn junction between the source and the substrate is a NAND type CMOS device.
When applied to a circuit where a voltage is applied to the area between the source and the substrate, such as an S circuit, the speed of the device (the speed of the entire circuit) is undesirably reduced.

On the other hand, the power consumption of a MOS semiconductor device is
It is proportional to the product obtained by multiplying the load capacitance and the square of the applied voltage together. Therefore, the pn between the source and the substrate
The presence of large parasitic capacitance at the junction undesirably increases the power consumption of the circuit.

Second, when devices having sizes on the order of quarter microns or less are formed, the threshold voltage is reduced and the devices are severely affected by short channel effects. The short channel effect depends on the effective channel length and the junction depth between the source diffusion layer and the drain diffusion layer. Since the LDC structure has a deep junction depth between the source diffusion layer and the drain diffusion layer, a decrease in threshold voltage is not suppressed in a region having a size on the order of quarter microns or less.

For the above reasons, the conventional MOS semiconductor device manufacturing technology cannot form a highly reliable and high speed semiconductor device in a region having a size on the order of quarter microns or less.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and its objects are (1) to realize an improvement in circuit speed and a reduction in power consumption, and an excellent resistance to a short channel effect. And (2) to provide a method for manufacturing such a complementary semiconductor device.

[0016]

A complementary semiconductor device according to the present invention includes a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type. And a semiconductor substrate having a main surface, a first MOS transistor provided in the second region, and a second MOS transistor provided in the first region Wherein each of the first and second MOS transistors includes a first source region, a first drain region located at a fixed distance from the first source region, and a first source region. A second source region in contact with the region and the main surface of the semiconductor substrate, the second source region having a junction depth smaller than that of the first source region, and a second source region located at a fixed distance from the second source region; 1 drain region and the main surface of the semiconductor substrate Contact, a second drain region having a shallow junction depth than the first drain region, said second
A channel region located between the source region and the second drain region; a gate insulating film formed on the main surface of the semiconductor substrate so as to cover the channel region; And at least one of the first and second MOS transistors has a non-uniform impurity concentration distribution in a channel length direction in the channel region and a source side. An asymmetric impurity diffusion region formed to have an impurity concentration higher than that of the drain side and having the same conductivity type as that of a corresponding region of the first and second regions. Wherein the impurity concentration in the portion of the semiconductor substrate located below the first source region is lower than the impurity concentration in the portion on the source side of the asymmetric impurity diffusion region.
An OS transistor, which achieves the above object.

In one embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the first MO is
The S transistor is the asymmetric MOS transistor.

In another embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the second conductivity type is n-type.
The S transistor is the asymmetric MOS transistor.

In still another embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the first conductivity type is n-type.
And each of the second MOS transistors is the asymmetric MOS transistor.

The complementary semiconductor circuit of the present invention can be incorporated in a circuit in which a potential difference occurs between the semiconductor substrate and the source of the asymmetric MOS transistor during operation.
For example, the circuit includes a configuration in which a plurality of MOS transistors of the same conductivity type as the asymmetric MOS transistor are connected in series.

In one embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the first MO is
The S transistor is an n-channel asymmetric MOS transistor having the asymmetric impurity diffusion region, and the circuit is a circuit in which a potential difference occurs between the semiconductor substrate and the source of the n-channel asymmetric MOS transistor. .

In another embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the second MO is
The S transistor is a p-channel asymmetric MOS transistor including the asymmetric impurity diffusion region, and the circuit is a circuit in which a potential difference occurs between the semiconductor substrate and a source of the p-channel asymmetric MOS transistor. .

In still another embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the first conductivity type is n-type.
Is an n-channel asymmetric MOS transistor including the asymmetric impurity diffusion region,
The second MOS transistor is a p-channel asymmetric MOS transistor having the asymmetric impurity diffusion region, and the circuit includes a circuit between the semiconductor substrate and a source of the n-channel asymmetric MOS transistor, and This is a circuit in which a potential difference is generated between the source of the p-channel type asymmetric MOS transistor and the source.

In one embodiment, the asymmetric MOS transistor further includes a punch-through stop layer.

On the other hand, according to another aspect of the present invention, the semiconductor device includes a first region doped with a first conductivity type impurity and a second region doped with a second conductivity type impurity, and A semiconductor substrate having a main surface; and a first substrate provided in the second region.
And a second MOS transistor provided in the first region, and a method for manufacturing a complementary semiconductor device. Forming a first insulating film and a conductive film on the main surface of the semiconductor substrate in this order so as to cover the first and second regions; Patterning the conductive film to form gate insulating films and gate electrodes of the first and second MOS transistors; and applying a first resist covering the second region to the main surface of the semiconductor substrate. Forming on the first and the first
Using the resist and the gate electrode of the second MOS transistor as a mask, implanting impurity ions of the second conductivity type into the first region, thereby forming the second MOS transistor.
Forming a source region and a drain region of a second conductivity type of the transistor; removing the first resist; and placing a second resist covering the first region on the main surface of the semiconductor substrate. Forming a first conductive type impurity ion into the second region using the second resist and the gate electrode of the first MOS transistor as a mask, thereby forming the first conductive type impurity ion. Forming a source region and a drain region of the first conductivity type of the MOS transistor; and using the second resist and the gate electrode of the first MOS transistor as a mask to form the second conductivity type in the second region. Impurity ions are obliquely implanted from the source side,
Forming an asymmetric impurity diffusion region having an asymmetric impurity concentration profile between the source region and the drain region of the first conductivity type of the first MOS transistor. This achieves the above object.

In one embodiment, an extension of the source region which is in contact with the source region of the first MOS transistor and the main surface of the semiconductor substrate and has a junction depth smaller than the source region; Forming a drain region of the MOS transistor and an extension of the drain region which is in contact with the main surface of the semiconductor substrate and has a junction depth smaller than the drain region. The first MO
In the S transistor, the asymmetric impurity diffusion region may be formed to reach an end of an extension of the drain region.

In one embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the first MO is
The S transistor is an n-channel MOS transistor having the asymmetric impurity diffusion region.

In another embodiment, the first conductivity type is p-type, the second conductivity type is n-type, and the first MO is
The S transistor is a p-channel MOS transistor having the asymmetric impurity diffusion region.

The method of manufacturing a complementary semiconductor device according to the present invention comprises:
The method may further include configuring a circuit in which a potential difference occurs during operation between the semiconductor substrate and the source of the first MOS transistor having the asymmetric impurity diffusion region. For example, the circuit includes a configuration in which a plurality of MOS transistors of the same conductivity type as the first MOS transistor are connected in series.

In one embodiment, the first resist is removed between the step of forming the source region and the drain region of the second conductivity type of the second MOS transistor and the step of removing the first resist. And using the gate electrode of the second MOS transistor as a mask, impurity ions of the first conductivity type are obliquely implanted into the first region from the source side, whereby the second region of the second MOS transistor is implanted. The method further includes forming an asymmetric impurity diffusion region having an asymmetric impurity concentration profile between the source region and the drain region of the two conductivity type.

In one embodiment, an extension of a source region that is in contact with the source region of the second MOS transistor and the main surface of the semiconductor substrate and has a junction depth smaller than the source region; Forming a drain region of the MOS transistor and an extension of the drain region which is in contact with the main surface of the semiconductor substrate and has a junction depth smaller than the drain region. The second MO
In the S transistor, the asymmetric impurity diffusion region may be formed to reach an end of an extension of the drain region.

In one embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the first MO is
The S transistor is an n-channel MOS transistor having the asymmetric impurity diffusion region.

In another embodiment, the first conductivity type is p-type, the second conductivity type is n-type, and the first MO is
The S transistor is a p-channel MOS transistor having the asymmetric impurity diffusion region.

The method of manufacturing a complementary semiconductor device according to the present invention comprises:
Between the semiconductor substrate and the source of the first MOS transistor having the asymmetric impurity diffusion region; and
The method may further include configuring a circuit in which a potential difference occurs during operation between each of the semiconductor substrate and the source of the second MOS transistor having the asymmetric impurity diffusion region. For example, the circuit comprises the first
A configuration in which a plurality of MOS transistors of the same conductivity type as the MOS transistor of
It includes a configuration in which a plurality of MOS transistors of the same conductivity type as the S transistor are connected in series.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In this specification, a portion of a channel region of a semiconductor device from a position adjacent to a source diffusion layer to the center of the channel region is referred to as a "source portion of the channel region". On the other hand, a portion of the channel region from a position adjacent to the drain diffusion layer to the center of the channel region is referred to as a “drain-side portion of the channel region”.

In the semiconductor device of the present invention, the impurity concentration of the channel region changes along the channel length direction due to the presence of the impurity diffusion layer formed in the channel region. More specifically, the impurity in the channel region is distributed such that its concentration decreases from the source diffusion layer to the drain diffusion layer. Therefore, when a voltage is applied to the region between the source diffusion layer and the drain diffusion layer, the electric field formed in the source-side portion of the channel region has a uniform impurity concentration in the channel region along the channel length direction. It is higher than the case.

By increasing the electric field at the source-side portion of the channel region in this manner, carriers cause speed overshoot at the source-side portion of the channel region.
"Velocity overshoot" means that the carrier gains high energy from the electric field and reaches a non-equilibrium energy state before some loss of carrier velocity occurs due to impurity scattering or lattice scattering, and the saturation velocity (ie, equilibrium (Speed of the state). The saturation current value is determined by a product obtained by multiplying the carrier velocity and the carrier density at the source side portion of the channel region together. Further, the carrier velocity depends on a voltage difference applied to the channel region.

According to the present invention, the saturation current value can be set higher than that obtained by the conventional semiconductor device by causing a speed overshoot in the source side portion of the channel region. In the conventional semiconductor device, since such a speed overshoot occurs only on the drain side portion of the channel region, the speed overshoot does not contribute to an increase in the saturation current.

The effects of the present invention as described above will be further described briefly with reference to FIG.

FIG. 8A is a diagram schematically showing a configuration of a semiconductor device obtained by the present invention. In the semiconductor device of the present invention, the gate (G) is provided on the channel region between the source region (S) and the drain region (D) having the extension. Furthermore, in the channel region,
From the source region (S) to the drain region (D),
An asymmetric diffusion layer (A) having an asymmetric impurity profile is provided.

FIG. 8B is a diagram schematically showing a potential distribution between the source and the drain when a voltage is applied between the source and the drain. In the semiconductor device of the present invention having the asymmetric diffusion layer (A), compared with the potential distribution (dotted line) in the conventional semiconductor device without such an asymmetric diffusion layer,
As shown by the solid line, the potential can be increased particularly on the source side.

FIG. 8C is a diagram schematically showing an electric field distribution between the source and the drain (expressed as a derivative of the potential distribution curve shown in FIG. 8B). Asymmetric diffusion layer (A)
In the semiconductor device of the present invention (solid line) having
The electric field increases on the source side and decreases on the drain side, as compared with the conventional semiconductor device without the asymmetric diffusion layer (dotted line), reflecting the change in the potential distribution described with reference to FIG. Due to such an electric field distribution, as schematically shown in FIG. 8D, the speed (solid line) of the electrons traveling in the channel of the semiconductor device of the present invention is closer to the source than the conventional result (dotted line). And, as a result, the current driving force of the semiconductor device is improved. As shown in FIGS. 8C and 8D, according to the present invention, the electric field intensity near the drain is slightly lower than the result of the conventional technique, and as a result, near the drain, The electron speed decreases slightly. However, as can be seen from the relationship between the electric field intensity and the electron velocity schematically shown in FIG. 8E, generally, when the electric field intensity becomes larger than a certain level, the electron velocity becomes saturated due to phonon scattering and the like. Therefore, a decrease in the electric field intensity near the drain where a large electric field intensity is originally obtained does not actually have a large adverse effect on the electron velocity. Rather,
The favorable effect on the electron velocity of the improvement in the electric field strength near the source, which has been obtained in the prior art with a relatively small electric field strength, is more pronounced.

Hereinafter, preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings. In the following, first, the present invention is applied to a single MOS transistor.
An embodiment in which the present invention is applied to a semiconductor device and a method of manufacturing the same will be described. Subsequently, an embodiment in which the present invention is applied to a complementary semiconductor device and a method of manufacturing the same will be described. Further, an embodiment of a circuit in which the effect of the complementary semiconductor device of the present invention is particularly remarkably obtained will be described later.

(First Embodiment) FIGS. 2A and 2B
Are the semiconductor devices 10 according to the first embodiment of the present invention, respectively.
FIG.

As shown in FIG. 2A or 2B, the semiconductor device 100 includes a p-type semiconductor substrate 1 and a first n-type high-concentration source formed in a main surface region of the semiconductor substrate 1. The semiconductor device includes a diffusion layer, a first n-type high-concentration drain diffusion layer, and a channel region formed inside the semiconductor substrate and located between the source diffusion layer and the drain diffusion layer. A gate insulating film 4 is provided on the channel region, and a gate electrode 5 is provided on the gate insulating film 4.

From the tip of each of the first source / drain diffusion layers 2 and 3 toward the channel direction, a second n
A high-concentration source diffusion layer 7 and a second high-concentration n-type drain diffusion layer 8 are provided. The impurity concentration of the first source / drain diffusion layers 2 and 3 is, for example, about 3 × 10 ²⁰ cm ^−3.
On the other hand, the impurity concentration of the second source / drain diffusion layers 7 and 8 is, for example, about 1 × 10 ²⁰ cm ⁻³ . Therefore, the second source / drain diffusion layers 7 and 8
Do not form a general LDD structure, but rather extend from the first source / drain diffusion layers 2 and 3
n).

A p-type impurity diffusion layer 6 is formed in the channel region. In the p-type impurity diffusion layer 6, the impurity concentration profile is non-uniform along the channel length direction. In the present embodiment, the impurity concentration of a portion adjacent to the source diffusion layer 2 (for example, about 4 × 10 ¹⁷ cm ⁻³ )
Is set higher than the impurity concentration (for example, about 1 × 10 ¹⁶ cm ⁻³ ) of the portion near the drain diffusion layer 3. The p-type impurity diffusion region 6 is formed at least in the channel region from the source diffusion layer 2 to the drain diffusion layer 3 as shown in FIG. Alternatively, as shown in FIG. 2 (b), it is also present at a position located below the second drain diffusion layer 8,
A p-type impurity diffusion region 6 may be provided. In this case,
Second drain diffusion layer 8 in p-type impurity diffusion region 6
The portion located below serves as a punch-through stop layer.

In the structure of the semiconductor device 100 shown in FIG. 2A or 2B, the source diffusion layers 2 and 7 and the drain diffusion layers 3 and 8 are symmetrical with respect to a plane perpendicular to the main surface of the semiconductor substrate 1. However, the impurity profile in the channel region is asymmetric with respect to the plane. This asymmetric profile is formed by the p-type impurity diffusion layer 6. Hereinafter, the p-type impurity diffusion layer 6 is also referred to as “asymmetric diffusion layer 6”.

Although not shown in FIG. 2A or 2B, a gate sidewall (sidewall spacer) may be formed along the sidewall of the gate electrode 5 (for example, FIG. 3C). See).

In the semiconductor device 100 of this embodiment, the p-type impurity diffusion layer (asymmetric diffusion layer) 6 is
It is not formed so as to cover the whole of. Therefore, the impurity concentration of the semiconductor substrate 1 immediately below the source diffusion layer 2 is:
For example, it is about 1 × 10 ¹⁷ cm ⁻³ , and the impurity concentration on the source side of the p-type impurity diffusion layer 6 (for example, about 4 × 10
¹⁷ cm ^-3 ). The impurity concentration of the semiconductor substrate 1 immediately below the source diffusion layer 2 is lower than the impurity concentration of the semiconductor substrate immediately below the source diffusion layer in the conventional LDC structure (1 × 10 ¹⁸ cm ⁻³ or more).
For this reason, the capacitance of the pn junction between the source and the substrate of the semiconductor device 100 shown in FIG.
It is smaller than a conventional semiconductor device having a DC structure.

In general, the speed of a semiconductor device is proportional to the product obtained by multiplying the load capacity and the reciprocal of the current together. Therefore, the semiconductor device 100 of the present embodiment is a NAND type CMOS in which a voltage is applied to the region between the source and the substrate.
Even when applied to an S circuit, the speed of the device (the speed of the entire circuit) is not reduced. The power consumption of the semiconductor device is proportional to the product obtained by multiplying the load capacitance and the square of the applied voltage together. Therefore, the semiconductor device 100 of the present embodiment operates with low power consumption.

Further, in the semiconductor device 100, as described above, the impurity profile of the p-type impurity diffusion layer 6 is non-uniform in the channel length direction, and the impurity concentration on the source side of the channel region is different from that on the drain side. Higher. As a result, the electric field component generated in the channel length direction in the channel region increases on the source side but decreases on the drain side, as compared with the case where the impurities are uniformly distributed in the channel region. Since the saturation current of a MOS semiconductor device is dominated by the electric field on the source side, according to the present invention, a high-speed semiconductor device can be realized by increasing the saturation current. Further, since the generation rate of hot carriers is governed by the electric field on the drain side, according to the present invention, the generation rate of hot carriers can be reduced, and a highly reliable semiconductor device can be realized.

Further, since the impurity concentration of the p-type impurity diffusion layer 6 gradually decreases from the source side to the drain side, the magnitude of the electric field component generated in the channel length direction in the channel region becomes There is no decrease at the center of the channel as compared to near the source. As a result, carriers accelerated by the electric field near the source can travel inside the channel without decreasing their speed.

In addition, the second n-type source / drain diffusion layers 7 and 8 have an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more, and have a thickness (junction depth) of these diffusion layers 7 and 8. Is formed so as to be smaller than the thickness (junction depth D1) of the first n-type source diffusion layer 2 and the first n-type drain diffusion layer 3. Therefore, the spread of the potential curve (spread of the depletion layer) from the source / drain diffusion layers in the channel length direction is effectively suppressed, and the threshold potential of the initial characteristics which becomes a problem in a region having a size on the order of quarter micron or less. Degradation is suppressed.

If the impurity concentration of the second n-type source diffusion layer 7 is formed higher than the impurity concentration of the second n-type drain diffusion layer 8, a high driving capability is realized, and the driving capability by the parasitic resistance is realized. A semiconductor device having high resistance to the short-channel effect can be realized without lowering the semiconductor device.

In the semiconductor device 100 of the present embodiment having the above-described structure, the p-type impurity diffusion layer (asymmetric diffusion layer) 6 extending from the source side to the drain side of the channel ends halfway in the channel. It may be formed as follows. Alternatively, if the asymmetric diffusion layer 6 is formed so as to reach the end on the drain side of the channel (for example, the end of the second n-type drain diffusion layer 8), a decrease in the carrier velocity inside the channel is suppressed. It is more effective in doing.

As described above, according to the present embodiment, a high-speed and high-reliability semiconductor device 100 is realized.

(Second Embodiment) FIGS. 3A to 3C
Is a semiconductor device 200 according to the second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing each process step for manufacturing the semiconductor device.

First, as shown in FIG. 3A, a gate oxide film 4 is formed on one main surface of a semiconductor substrate 1 of a first conductivity type (p type), and a conductive film used as a gate electrode 5 is formed thereon. A conductive film is deposited to form a multilayer film. A predetermined portion of the multilayer film is selectively etched by photolithography and anisotropic etching until the gate oxide film 4 is exposed,
The gate electrode 5 is formed.

Next, an impurity ion of the second conductivity type (n-type), for example, arsenic (As) ion is used as a mask and the implantation angle is set to 7 degrees or more, for example, 7 degrees, and 10 KeV. About 2 while applying the injection energy of
The implantation is performed from the source side at an implantation dose of × 10 ¹⁴ cm ⁻² . Thereby, second source / drain diffusion layers 7 and 8 having the second conductivity type (n-type) are formed. In the specification of the present application, the term “implantation angle” refers to an angle formed between a line perpendicular to the main surface of the semiconductor substrate and the direction of the ion beam to be implanted.

Thereafter, as shown in FIG. 3B, using the gate electrode 5 as a mask and applying an implantation energy of 80 KeV, the implantation dose is about 1.5 × 10 ^13.
cm ⁻² , and the implantation angle is set to 7 degrees or more, for example, 7 degrees, and impurity ions of the first conductivity type (p-type), for example, B
F ₂ ions are implanted from the source side to form a p-type impurity diffusion layer (asymmetric diffusion layer) 6 for controlling the threshold potential. Under the above conditions, the impurity concentration of the formed p-type impurity diffusion layer 6 is about 4 × 10 ¹⁷ cm ⁻³ at the source end and about 1 × 10 ¹⁶ cm ⁻³ at the drain end.

Next, as shown in FIG.
After being deposited to a thickness of 0 nm, the oxide film is partially removed by anisotropic dry etching so that the oxide film remains only on the side of the gate electrode 5 to form a gate sidewall (sidewall spacer) 12. . Then, while applying an implantation energy of 40 KeV, the implantation dose is reduced to about 6 × 10 ¹⁵
cm ^−2, and implanted impurity ions of the second conductivity type (n-type), for example, As ions using the gate side wall 12 and the gate electrode 5 as a mask.
The first source / drain diffusion layers 2 and 3 having the following are formed. Under the above conditions, the impurity concentration of the formed first source / drain diffusion layers 2 and 3 is about 3 × 10 ²⁰ c
m ^-3 .

In the previously formed p-type impurity diffusion layer 6, a portion corresponding to the lower portion of the gate electrode 5 and the gate side wall 12 is a region for forming the first source / drain diffusion layers 2 and 3. It remains even after the injection step. Similarly, of the previously formed second source / drain diffusion layers 7 and 8, a portion corresponding to the lower portion of the gate side wall 12 also remains after this ion implantation step, and Function as an extension of the A portion of the p-type impurity diffusion layer 6 located below the second drain diffusion layer 8 (below the extension of the drain diffusion layer) functions as a punch-through stop layer. However, the formation of the punch-through stop layer may be omitted. Alternatively, the formation of the gate side wall 12 may be omitted, and the predetermined shape of each diffusion layer may be formed by another method.

In the method of manufacturing the semiconductor device 200 of this embodiment, the implantation angle is set to 7 using the gate electrode 5 as a mask.
To control the threshold potential by injecting a first conductivity type (p-type) ion species from the source side at a temperature higher than or equal to
A type impurity diffusion layer (asymmetric diffusion layer) 6 is formed. As a result, an asymmetric diffusion layer 6 having a non-uniform impurity profile in the channel and having a source-side impurity concentration higher than the drain-side impurity concentration can be easily formed without performing an extra masking step. be able to. Further, by forming the impurity concentration in the central portion of the channel lower than the impurity concentration in the vicinity of the source, the parasitic capacitance between the gate and the substrate can be reduced as compared with a conventional semiconductor device having a diffusion layer having a uniform impurity concentration. And the semiconductor device 200 having a high driving capability can be easily formed.

Further, in the above-described ion implantation step, by implanting ion species of the first conductivity type (p-type) at an angle of 7 degrees or more, the thickness (junction depth) of the asymmetric diffusion layer 6 can be reduced.
It can be set smaller than the thickness (junction depth) of the first source diffusion layer 2. Specifically, the asymmetric diffusion layer 6
Is not formed so as to cover the entire source diffusion layer 2. As a result, the impurity concentration in the region of the semiconductor substrate 1 immediately below the first source diffusion layer 2 becomes lower than the impurity concentration on the source side of the asymmetric diffusion layer 6.

According to the manufacturing method of this embodiment, prior to forming the asymmetric diffusion layer 6, the implantation dose is about 2 × while applying the implantation energy of 10 KeV using the gate electrode 5 as a mask. The ion implantation step of implanting n-type impurity ions, for example, As ions from the source side with the implantation angle set at 10 ¹⁴ cm ^-2 and the implantation angle of 7 degrees or more, is performed, thereby forming the second portion corresponding to the extension. N-type source / drain diffusion layers 7 and 8 are formed. The impurity concentration of the second n-type source / drain diffusion layers 7 and 8 is:
It becomes 1 × 10 ¹⁹ cm ⁻³ or more.

In particular, if the impurity concentration of the second n-type source diffusion layer 7 is higher than the impurity concentration of the second n-type drain diffusion layer 8, there is a concern about a diffusion layer having a shallow junction depth. The second n-type source / drain diffusion layers 7 and 8 having a sufficiently low resistance can be formed without reducing the parasitic resistance.

According to the method of manufacturing the semiconductor device 200 of the present embodiment, it is not necessary to perform an additional mask step which is required in the method of manufacturing the conventional LDC structure. If an additional masking step is required in a currently available method of manufacturing a semiconductor device, the manufacturing period of the VLSI is lengthened, and the manufacturing cost is increased. However, according to the manufacturing method of the present invention, a semiconductor device can be easily manufactured at a low cost in a short period of time.

In the present embodiment, p-type impurity ions are implanted after the second n-type source / drain diffusion layers 7 and 8 are formed by implanting n-type impurity ions using the gate electrode 5 as a mask. Thus, a p-type impurity diffusion layer 6 is formed. However, the present invention is not limited to this. Alternatively, after the p-type impurity diffusion layer 6 is formed by implanting p-type impurity ions using the gate electrode 5 as a mask, the second n-type source / drain diffusion layers 7 are implanted by implanting n-type impurity ions. And 8 may be formed.

The semiconductor device 2 of the present embodiment described above
In the manufacturing method of No. 00, the p-type impurity diffusion layer (asymmetric diffusion layer) 6 extending from the source side to the drain side of the channel may be formed so as to end partway through the channel. Alternatively, if the asymmetric diffusion layer 6 is formed so as to reach the end on the drain side of the channel (for example, the end of the second n-type drain diffusion layer 8), a decrease in the carrier velocity inside the channel is suppressed. It is more effective in doing.

(Third Embodiment) FIG. 4 shows a third embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a complementary semiconductor device 300 according to the embodiment.

As shown in FIG. 4, the semiconductor device 300 includes an n-channel MOS transistor 310 formed in a predetermined region of a p-type semiconductor substrate 1 and an n-type well 21 in the p-type semiconductor substrate 1. P-type MO formed on
And an S transistor 320, which are separated by the separation region 20.

N-channel MOS transistor 310
Is the first n formed in the main surface region of the p-type semiconductor substrate 1.
A high-concentration source diffusion layer 2 and a first high-concentration drain diffusion layer 3 and a channel region formed inside the semiconductor substrate 1 and located between the source diffusion layer 2 and the drain diffusion layer 3. Have. A gate insulating film 4 is provided on the channel region, and an n-type gate electrode 15 is provided on the gate insulating film 4.

From the tip of each of the first source / drain diffusion layers 2 and 3 toward the channel direction, a second n
A high-concentration source diffusion layer 7 and a second high-concentration n-type drain diffusion layer 8 are provided. The impurity concentration of the first source / drain diffusion layers 2 and 3 is, for example, about 3 × 10 ²⁰ cm ^−3.
On the other hand, the impurity concentration of the second source / drain diffusion layers 7 and 8 is, for example, about 1 × 10 ²⁰ cm ⁻³ . Therefore, the second source / drain diffusion layers 7 and 8
Do not form a general LDD structure, but rather extend from the first source / drain diffusion layers 2 and 3
n).

In the channel region, a p-type impurity diffusion layer (asymmetric diffusion layer) 6 is formed. In the p-type impurity diffusion layer 6, the impurity concentration profile is non-uniform along the channel length direction. In the present embodiment, the impurity concentration of the portion adjacent to the source diffusion layer 2 (for example, about 4
The impurity concentration of the channel region is set so that (× 10 ¹⁷ cm ⁻³ ) is higher than the impurity concentration (for example, about 1 × 10 ¹⁶ cm ⁻³ ) near the drain diffusion layer 3. p
The type impurity diffusion region 6 is formed at least in the channel region from the source diffusion layer 2 to the drain diffusion layer 3. Alternatively, as shown in FIG. 4, the p-type impurity diffusion region 6 may be provided so as to exist also at a position below the second drain diffusion layer 8. In this case, a portion of the p-type impurity diffusion region 6 located below the second drain diffusion layer 8 functions as a punch-through stop layer.

The above n-channel MOS shown in FIG.
In the structure of the transistor 310, the source diffusion layers 2 and 7
And the drain diffusion layers 3 and 8 are located symmetrically with respect to a plane perpendicular to the main surface of the semiconductor substrate 1,
The impurity profile in the channel region is asymmetric with respect to its plane. This asymmetric profile is formed by the p-type impurity diffusion layer (asymmetric diffusion layer) 6.

On the other hand, p-channel type MOS transistor 3
Reference numeral 20 denotes a first p-type high-concentration source diffusion layer 22 and a first p-type high-concentration drain diffusion layer 23 formed in the main surface region of the n-type well 21 and the inside of the n-type well 21.
A channel region located between the source diffusion layer 22 and the drain diffusion layer 23. A gate insulating film 4 is provided on the channel region, and a p-type gate electrode 25 is provided on the gate insulating film 4.

First source / drain diffusion layers 22 and 2
3 toward the channel direction from each tip of
The p-type high-concentration source diffusion layer 27 and the second p-type high-concentration drain diffusion layer 28 are provided. The impurity concentration of the first source / drain diffusion layers 22 and 23 is, for example, about 3 ×
Against 10 ²⁰ of cm ^-3, the impurity concentration of the second source / drain diffusion layers 27 and 28, for example, about 5 × 1
0 ¹⁹ cm ^-3 . Therefore, the second source / drain diffusion layers 27 and 28 do not form a general LDD structure, but the first source / drain diffusion layers 22 and 23.
This is equivalent to the extension of the above.

The above p-channel type MOS shown in FIG.
In the structure of the transistor 320, the source diffusion layers 22 and 27 and the drain diffusion layers 23 and 28
It is located symmetrically with respect to a plane perpendicular to the main surface of (n-type well 21), and the impurity profile in the channel region is symmetrical with respect to that plane.

Further, although not shown in FIG. 4, in each of the n-channel and p-channel MOS transistors 310 and 320, a gate sidewall (sidewall spacer) is formed along the sidewall of the gate electrodes 15 and 25. (See, for example, FIG. 6D).

As described above, in the complementary semiconductor device 300 of this embodiment, the p-channel MOS transistor 32
While the impurity profile in the zero channel region is uniform, the impurity profile in the channel region of the n-channel MOS transistor 310 is non-uniform.

In n-channel MOS transistor 310, p-type impurity diffusion layer (asymmetric diffusion layer) 6 is not formed so as to cover the entire source diffusion layer 2. Therefore, the impurity concentration of the semiconductor substrate 1 immediately below the source diffusion layer 2 is, for example, about 1 × 10 ¹⁷ cm ⁻³ , and the impurity concentration on the source side of the p-type impurity diffusion layer 6 (for example, about 4 × 10 ¹⁷ cm ^−3). × 10 ¹⁷ cm ^-3 ). The impurity concentration of the semiconductor substrate 1 immediately below the source diffusion layer 2 is the impurity concentration of the semiconductor substrate immediately below the source diffusion layer in the conventional LDC structure (1 × 10 ¹⁸ cm ⁻³ or more).
Lower than. Therefore, the n-channel type M shown in FIG.
The capacitance of the pn junction between the source of the OS transistor 310 and the substrate is smaller than that of a conventional semiconductor device having an LDC structure.

In general, the speed of a semiconductor device is proportional to the product obtained by multiplying the load capacity and the reciprocal of the current together. Therefore, even when the complementary semiconductor device 300 of this embodiment is applied to a NAND CMOS circuit in which a voltage is applied to a region between a source and a substrate, the speed of the device (the speed of the entire circuit) is not reduced. The power consumption of the semiconductor device is proportional to the product obtained by multiplying the load capacitance and the square of the applied voltage together. Therefore, the complementary semiconductor device 300 of the present embodiment operates with low power consumption.

Further, in the n-channel MOS transistor 310, as described above, the impurity profile of the p-type impurity diffusion layer 6 is non-uniform in the channel length direction.
The impurity concentration on the source side of the channel region is formed higher than the impurity concentration on the drain side. As a result, compared to the case where the impurities are uniformly distributed in the channel region,
The electric field component generated in the channel length direction in the channel region increases on the source side but decreases on the drain side.
Since the saturation current of a MOS semiconductor device is governed by the electric field on the source side, according to the present invention, the saturation current is increased,
A high-speed semiconductor device can be realized. Further, since the generation rate of hot carriers is governed by the electric field on the drain side, according to the present invention, the generation rate of hot carriers can be reduced, and a highly reliable semiconductor device can be realized.

Further, since the impurity concentration of p-type impurity diffusion layer 6 gradually decreases from the source side to the drain side, the magnitude of the electric field component generated in the channel length direction in the channel region becomes There is no decrease at the center of the channel as compared to near the source. As a result, carriers accelerated by the electric field near the source can travel inside the channel without decreasing their speed.

Further, in the n-channel MOS transistor 310, the second n-type source / drain diffusion layer 7
And 8, the impurity concentration is not less than 1 × 10 ¹⁹ cm ^-3, and the thickness of these diffusion layers 7 and 8 (junction depth D
2) is formed to be smaller than the thickness (junction depth D1) of the first n-type source diffusion layer 2 and the first n-type drain diffusion layer 3. For this reason, the expansion of the potential curve (expansion of the depletion layer) from the n-type source / drain diffusion layer in the channel length direction is effectively suppressed, and the initial characteristic which becomes a problem in a region having a size on the order of quarter micron or less is reduced. Deterioration of the threshold potential is suppressed.

Similarly, in p-channel MOS transistor 320, second p-type source / drain diffusion layer 2
7 and 28, the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more, and the thickness (junction depth D2) of these diffusion layers 27 and 28 is equal to that of the first p-type source diffusion layer 22 and the first p-type source diffusion layer 22. 1 is formed so as to be smaller than the thickness (junction depth D1) of the p-type drain diffusion layer 23. For this reason, the expansion of the potential curve (expansion of the depletion layer) from the p-type source / drain diffusion layer in the channel length direction is effectively suppressed, and the initial characteristic which is problematic in a region having a size on the order of quarter micron or less is reduced. Deterioration of the threshold potential is suppressed.

In the complementary semiconductor device 300 according to the present embodiment having the above-described structure, the p-type impurity diffusion layer (asymmetric diffusion layer) 6 extending from the source side to the drain side of the channel extends halfway through the channel. It may be formed to end with. Alternatively, if the asymmetric diffusion layer 6 is formed to reach the end on the drain side of the channel (for example, the end of the second n-type drain diffusion layer 8), the decrease in the electric field inside the channel is suppressed. Above is more effective.

As described above, according to this embodiment, a high-speed and high-reliability complementary semiconductor device 300 is realized.

In the above-described complementary semiconductor device 300 of this embodiment, only the n-channel MOS transistor 310 is formed asymmetrically, and the p-channel MOS transistor 320 is formed symmetrically. Alternatively, only the p-channel MOS transistor is formed asymmetrically and n
The channel type MOS transistor may be formed symmetrically.

(Fourth Embodiment) FIG. 5 shows a fourth embodiment of the present invention.
FIG. 14 is a sectional view showing a complementary semiconductor device 400 according to the embodiment.

As shown in FIG. 5, the semiconductor device 400 includes an n-channel MOS transistor 410 formed in a predetermined region of a p-type semiconductor substrate 1 and an n-type well 21 in the p-type semiconductor substrate 1. P-type MO formed on
And an S transistor 430, which are separated by the separation region 20.

N-channel MOS transistor 410
Is the first n formed in the main surface region of the p-type semiconductor substrate 1.
A high-concentration source diffusion layer 2 and a first high-concentration drain diffusion layer 3 and a channel region formed inside the semiconductor substrate 1 and located between the source diffusion layer 2 and the drain diffusion layer 3. Have. A gate insulating film 4 is provided on the channel region, and an n-type gate electrode 15 is provided on the gate insulating film 4.

From the tip of each of the first source / drain diffusion layers 2 and 3 toward the channel direction, a second n
A high-concentration source diffusion layer 7 and a second high-concentration n-type drain diffusion layer 8 are provided. The impurity concentration of the first source / drain diffusion layers 2 and 3 is, for example, about 3 × 10 ²⁰ cm ^−3.
On the other hand, the impurity concentration of the second source / drain diffusion layers 7 and 8 is, for example, about 1 × 10 ²⁰ cm ⁻³ . Therefore, the second source / drain diffusion layers 7 and 8
Do not form a general LDD structure, but rather extend from the first source / drain diffusion layers 2 and 3
n).

In the channel region, a p-type impurity diffusion layer (asymmetric diffusion layer) 6 is formed. In the p-type impurity diffusion layer 6, the impurity concentration profile is non-uniform along the channel length direction. In the present embodiment, the impurity concentration of the portion adjacent to the source diffusion layer 2 (for example, about 4
The impurity concentration of the channel region is set so that (× 10 ¹⁷ cm ⁻³ ) is higher than the impurity concentration (for example, about 1 × 10 ¹⁶ cm ⁻³ ) near the drain diffusion layer 3. p
The type impurity diffusion region 6 is formed at least in the channel region from the source diffusion layer 2 to the drain diffusion layer 3. Alternatively, as shown in FIG. 5, the p-type impurity diffusion region 6 may be provided so as to exist also at a position located below the second drain diffusion layer 8. In this case, a portion of the p-type impurity diffusion region 6 located below the second drain diffusion layer 8 functions as a punch-through stop layer.

The above n-channel MOS shown in FIG.
In the structure of the transistor 410, the source diffusion layers 2 and 7
And the drain diffusion layers 3 and 8 are located symmetrically with respect to a plane perpendicular to the main surface of the semiconductor substrate 1,
The impurity profile in the channel region is asymmetric with respect to its plane. This asymmetric profile is formed by the p-type impurity diffusion layer 6 (asymmetric diffusion layer).

On the other hand, p-channel MOS transistor 4
Reference numeral 30 denotes a first p-type high-concentration source diffusion layer 22 and a first p-type high-concentration drain diffusion layer 23 formed in the main surface region of the n-type well 21 and the inside of the n-type well 21.
A channel region located between the source diffusion layer 22 and the drain diffusion layer 23. A gate insulating film 4 is provided on the channel region, and a p-type gate electrode 25 is provided on the gate insulating film 4.

First source / drain diffusion layers 22 and 2
3 toward the channel direction from each tip of
The p-type high-concentration source diffusion layer 27 and the second p-type high-concentration drain diffusion layer 28 are provided. The impurity concentration of the first source / drain diffusion layers 22 and 23 is, for example, about 3 ×
Against 10 ²⁰ of cm ^-3, the impurity concentration of the second source / drain diffusion layers 27 and 28, for example, about 5 × 1
0 ¹⁹ cm ^-3 . Therefore, the second source / drain diffusion layers 27 and 28 do not form a general LDD structure, but the first source / drain diffusion layers 22 and 23.
This is equivalent to the extension of the above.

In the channel region, an n-type impurity diffusion layer (asymmetric diffusion layer) 26 is formed. In the n-type impurity diffusion layer 26, the impurity concentration profile is
Non-uniform along the channel length direction. In the present embodiment, the impurity concentration (for example, about 7 × 10 ¹⁷ cm ⁻³ ) of the part adjacent to the source diffusion layer 22 is higher than the impurity concentration (for example, about 2 × 10 ¹⁶ cm ⁻³ ) of the part close to the drain diffusion layer 23. , The impurity concentration of the channel region is set. The n-type impurity diffusion region 26 is formed at least in the channel region from the source diffusion layer 22 to the drain diffusion layer 23. Alternatively, as shown in FIG. 5, the n-type impurity diffusion region 26 may be provided so as to exist also at a position located below the second drain diffusion layer 28. In this case, a portion of the n-type impurity diffusion region 26 located below the second drain diffusion layer 28 functions as a punch-through stop layer.

The above p-channel type MOS shown in FIG.
In the structure of the transistor 430, the source diffusion layers 22 and 27 and the drain diffusion layers 23 and 28
Although located symmetrically with respect to a plane perpendicular to the main surface of (n-type well 21), the impurity profile in the channel region is asymmetrical with respect to that plane.
This asymmetric profile is formed by an n-type impurity diffusion layer (asymmetric diffusion layer) 26.

Further, although not shown in FIG. 5, in each of the n-channel type and p-channel type MOS transistors 410 and 430, a gate side wall (side wall spacer) is formed along the side wall of the gate electrodes 15 and 25. (See, for example, FIG. 7D).

As described above, in the complementary semiconductor device 400 of the present embodiment, the n-channel MOS transistor 41
In each of the 0-channel and p-channel MOS transistors 430, the impurity profile in the channel region is non-uniform. Among them, with respect to the p-channel MOS transistor, conventionally, the drive capability has been improved by increasing the gate width. However, by applying the present invention to a p-channel MOS transistor and providing a non-uniform in-channel impurity profile as shown in FIG. It is possible to reduce the size.

In n-channel MOS transistor 410, p-type impurity diffusion layer (asymmetric diffusion layer) 6 is not formed so as to cover the entire source diffusion layer 2. Therefore, the impurity concentration of the semiconductor substrate 1 immediately below the source diffusion layer 2 is, for example, about 1 × 10 ¹⁷ cm ⁻³ , and the impurity concentration on the source side of the p-type impurity diffusion layer 6 (for example, about 4 × 10 ¹⁷ cm ^−3). × 10 ¹⁷ cm ^-3 ). Further, the impurity concentration of the semiconductor substrate 1 immediately below the source diffusion layer 2 is the impurity concentration of the semiconductor substrate immediately below the source diffusion layer in the conventional LDC structure (1 × 10 ¹⁸ cm ⁻³ or more).
Lower than. Therefore, the n-channel type M shown in FIG.
The capacitance of the pn junction between the source of the OS transistor 410 and the substrate is smaller than that of a conventional semiconductor device having an LDC structure.

In general, the speed of a semiconductor device is proportional to the product obtained by multiplying the load capacity and the reciprocal of the current together. Therefore, even when the complementary semiconductor device 400 of this embodiment is applied to a NAND CMOS circuit in which a voltage is applied to a region between a source and a substrate, the speed of the device (the speed of the entire circuit) is not reduced. . The power consumption of the semiconductor device is proportional to the product obtained by multiplying the load capacitance and the square of the applied voltage together. Therefore, the complementary semiconductor device 400 of the present embodiment operates with low power consumption.

Further, in the n-channel MOS transistor 410, as described above, the impurity profile of the p-type impurity diffusion layer 6 is non-uniform in the channel length direction.
The impurity concentration on the source side of the channel region is formed higher than the impurity concentration on the drain side. As a result, compared to the case where the impurities are uniformly distributed in the channel region,
The electric field component generated in the channel length direction in the channel region increases on the source side but decreases on the drain side.
Since the saturation current of a MOS semiconductor device is governed by the electric field on the source side, according to the present invention, the saturation current is increased,
A high-speed semiconductor device can be realized. Further, since the generation rate of hot carriers is governed by the electric field on the drain side, according to the present invention, the generation rate of hot carriers can be reduced, and a highly reliable semiconductor device can be realized.

Since the impurity concentration of p-type impurity diffusion layer 6 gradually decreases from the source side to the drain side, the magnitude of the electric field component generated in the channel length direction in the channel region is There is no decrease at the center of the channel as compared to near the source. As a result, carriers accelerated by the electric field near the source can travel inside the channel without decreasing their speed.

In the n-channel MOS transistor 410, the second n-type source / drain diffusion layers 7 and 8
Has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more, and the thickness (junction depth D2) of these diffusion layers 7 and 8 is
The thickness of the first n-type source diffusion layer 2 and the first n-type drain diffusion layer 3 is smaller than the thickness (junction depth D1).
Is formed. For this reason, the expansion of the potential curve (expansion of the depletion layer) from the n-type source / drain diffusion layer in the channel length direction is effectively suppressed, and the initial characteristic which becomes a problem in a region having a size on the order of quarter micron or less is reduced. Deterioration of the threshold potential is suppressed.

On the other hand, p-channel MOS transistor 4
At 30, an n-type impurity diffusion layer (asymmetric diffusion layer) 2
6 is not formed so as to cover the entire source diffusion layer 22. Therefore, the impurity concentration of the n-type well 21 immediately below the source diffusion layer 22 is, for example, about 1 × 10 ¹⁷ cm ^−3.
And is kept lower than the impurity concentration on the source side of the n-type impurity diffusion layer 26 (for example, about 7 × 10 ¹⁷ cm ⁻³ ). Further, the impurity concentration of the n-type well 21 immediately below the source diffusion layer 22 is the impurity concentration of the semiconductor substrate immediately below the source diffusion layer (1
× 10 ¹⁸ cm ^-3 or more). For this reason, the capacitance of the pn junction between the source and the well of the p-channel MOS transistor 430 shown in FIG. 5 is smaller than that of the conventional semiconductor device having the LDC structure.

In general, the speed of a semiconductor device is proportional to the product obtained by multiplying the load capacity and the reciprocal of the current together. Therefore, even when the complementary semiconductor device 400 of this embodiment is applied to a NAND CMOS circuit in which a voltage is applied to a region between a source and a well (substrate), the speed of the device is not reduced. The power consumption of the semiconductor device is proportional to the product obtained by multiplying the load capacitance and the square of the applied voltage together. Therefore, the complementary semiconductor device 400 of the present embodiment operates with low power consumption.

Further, in p-channel MOS transistor 430, as described above, the impurity profile of n-type impurity diffusion layer 26 is non-uniform in the channel length direction, and the impurity concentration on the source side of the channel region is lower than that on the drain side. Is formed higher than the impurity concentration. as a result,
The electric field component generated in the channel length direction in the channel region increases on the source side but decreases on the drain side, as compared with the case where the impurities are uniformly distributed in the channel region. Since the saturation current of a MOS semiconductor device is dominated by the electric field on the source side, according to the present invention, a high-speed semiconductor device can be realized by increasing the saturation current. Also,
Since the generation rate of hot carriers is governed by the electric field on the drain side, according to the present invention, the generation rate of hot carriers can be reduced and a highly reliable semiconductor device can be realized.

Since the impurity concentration of the n-type impurity diffusion layer 26 gradually decreases from the source side to the drain side, the magnitude of the electric field component generated in the channel length direction in the channel region becomes There is no decrease at the center of the channel as compared to near the source. As a result, carriers accelerated by the electric field near the source can travel inside the channel without decreasing their speed.

The second p-type source / drain diffusion layers 27 and 28 of the p-channel type MOS transistor 430 have an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more, and the thickness of these diffusion layers 27 and 28 is The thickness (junction depth D2) is smaller than the thickness (junction depth D1) of the first p-type source diffusion layer 22 and the first p-type drain diffusion layer 23. For this reason, the expansion of the potential curve (expansion of the depletion layer) from the p-type source / drain diffusion layer in the channel length direction is effectively suppressed, and the initial characteristic which is problematic in a region having a size on the order of quarter micron or less is reduced. Deterioration of the threshold potential is suppressed.

In the complementary semiconductor device 400 of the present embodiment having the structure described above, a p-type or n-type impurity diffusion layer (asymmetric diffusion layer) 6 or 26 extending from the source side to the drain side of the channel. May be formed so as to end partway through the channel. Alternatively, if the asymmetric diffusion layer 6 or 26 is formed so as to reach the drain-side end of the channel (for example, the end of the second n-type or p-type drain diffusion layer 8 or 28), the inside of the channel can be formed. This is more effective in suppressing the decrease in the electric field of the above.

As described above, according to the present embodiment, a high-speed and high-reliability complementary semiconductor device 400 is realized.

(Fifth Embodiment) FIGS. 6A to 6D
FIGS. 14A to 14C are cross-sectional views showing process steps for manufacturing a complementary semiconductor device according to the fifth embodiment of the present invention. FIGS.

First, a first insulating film to be the gate insulating film 4 of the transistor is formed on one main surface of the semiconductor substrate so as to cover the p-type well 11 and the n-type well 21 provided on the semiconductor substrate. In addition, an n-channel type MO
A conductive film used as the n-type gate electrode 15 of the S transistor and the p-type gate electrode 25 of the p-channel MOS transistor is deposited. Next, predetermined portions of the conductive film are selectively etched by photolithography and anisotropic etching until the gate oxide film 4 is exposed, so that gate electrodes 15 and 25 are formed.

Subsequently, as shown in FIG. 6A, a first resist 31 covering a p-type well (p-type region) 11, which is a region for forming an n-channel MOS transistor, is formed on the main surface of the semiconductor substrate. Deposited on And p-type impurity ions,
For example, BF ₂ ions are implanted into the n-type well 21 at an implantation dose of about 2 × 10 ¹⁴ cm ⁻² while applying implantation energy of 10 KeV using the first resist 31 and the p-type gate electrode 25 as a mask. I do. Thereby, the second
The p-type source diffusion layer 27 and the second p-type drain diffusion layer 28 are formed. Under the above conditions, the impurity concentration of the formed second source / drain diffusion layers 27 and 28 is
It becomes about 5 × 10 ¹⁹ cm ⁻³ .

Next, after removing the first resist 31, as shown in FIG. 6B, an n-type well (n-type region) 21 for forming a p-channel MOS transistor is formed.
Is deposited on the main surface of the semiconductor substrate. Then, using the second resist 32 and the n-type gate electrode 15 as a mask, n-type impurity ions, for example, As ions are implanted at an implantation dose of about 2 × 10 ¹⁴ cm ⁻² while applying an implantation energy of 10 KeV. , Into the p-type well 11. Thus, a second n-type source diffusion layer 7 and a second n-type drain diffusion layer 8 are formed (this As ion implantation step is not shown in FIG. 6B). Under the above conditions, the impurity concentration of the formed second source / drain diffusion layers 7 and 8 is about 1 × 10 ²⁰ c
m ^-3 .

Further, using the second resist 32 and the n-type gate electrode 15 as a mask, while applying an implantation energy of 80 KeV, the implantation dose is set to about 1.5 × 10 5
¹³ cm ^-2 , the implantation angle is set to 7 degrees or more, for example, 7 degrees, and p-type impurity ions, for example, BF ₂ ions are implanted into the p-type well 11 from the source side, and FIG. A p-type impurity diffusion layer (asymmetric diffusion layer) 6 for controlling a threshold potential as shown in FIG. Under the above conditions,
The impurity concentration of the formed p-type impurity diffusion layer 6 is about 4 × 10 ¹⁷ cm ⁻³ at the source end, and about 1 × 1 ¹⁷ at the drain end.
It becomes 0 ¹⁶ cm ^-3 .

Next, after removing the second resist 32, an oxide film is deposited to a thickness of about 80 nm on the main surface of the semiconductor substrate. Then, the oxide film is partially removed by anisotropic dry etching so that the oxide film remains only on the side portions of the gate electrodes 15 and 25, and a gate sidewall (sidewall spacer) 12 is formed.

Next, as shown in FIG. 6C, a third resist 33 covering the n-type well (n-type region) 21 which is a formation region of the p-channel MOS transistor is formed on the main surface of the semiconductor substrate. Deposited on And n-type impurity ions,
For example, using As ion as the mask with the third resist 33, the n-type gate electrode 15 and the gate side wall 12 as masks,
About 6 × 10 ¹⁵ c while applying KeV implantation energy
An implantation dose of m ⁻² is implanted into the p-type well 11. Thereby, a first n-type source diffusion layer 2 and a first n-type drain diffusion layer 3 are formed. Under the above conditions, the impurity concentration of the first n-type source / drain diffusion layers 2 and 3 to be formed is about 3 × 10 ²⁰ cm ⁻³ .

In the previously formed p-type impurity diffusion layer 6, a portion corresponding to the lower portion of the n-type gate electrode 15 and the gate side wall 12 is the first n-type source / drain diffusion layer 2
And 3 also remain after the ion implantation step for forming them. Similarly, of the second n-type source / drain diffusion layers 7 and 8 formed earlier, a portion corresponding to the lower portion of the gate side wall 12 also remains after this ion implantation step, and the n-type source / drain diffusion layers 7 and 8 remain. / Drain diffusion layer. A portion of the p-type impurity diffusion layer 6 located below the second drain diffusion layer 8 (below the extension of the drain diffusion layer) functions as a punch-through stop layer. However, the formation of the punch-through stop layer may be omitted. Also, the formation of the gate side wall 12 is omitted,
The predetermined shape of each diffusion layer may be formed by another method.

Next, after removing the third resist 33, as shown in FIG. 6D, a p-type well (p-type region) 11 for forming an n-channel MOS transistor is formed.
Is deposited on the main surface of the semiconductor substrate. Then, p-type impurity ions, for example, BF ₂ ions are applied at a dose of about 2 × 10 ¹⁵ cm ⁻² while applying an implantation energy of 30 KeV using the fourth resist 34, the p-type gate electrode 25 and the gate side wall 12 as a mask. The n-type well 21 is implanted at an implantation dose. Thereby, the first
The p-type source diffusion layer 22 and the first p-type drain diffusion layer 23 are formed. Under the above conditions, the impurity concentration of the formed first p-type source / drain diffusion layers 22 and 23 is about 3 × 10 ²⁰ cm ⁻³ .

In the previously formed second p-type source / drain diffusion layers 27 and 28, a portion corresponding to the lower portion of the gate side wall 12 is formed of the first p-type source / drain diffusion layers 22 and 23. It remains after the ion implantation step for formation and functions as an extension of the p-type source / drain diffusion layer. However, the formation of the gate side wall 12 may be omitted, and the predetermined shape of each diffusion layer may be formed by another method.

In the method of manufacturing a semiconductor device according to the present embodiment,
In the step shown in FIG. 6B, the n-type gate electrode 1
By implanting p-type ion species from the source side by setting the implantation angle to 7 degrees or more using 5 as a mask,
A p-type impurity diffusion layer (asymmetric diffusion layer) 6 for controlling a threshold potential is formed. As a result, the asymmetric diffusion layer 6 has a non-uniform impurity profile in the channel, and the impurity concentration on the source side is higher than the impurity concentration on the drain side.
Can be easily formed without performing an extra masking step. Further, by forming the impurity concentration in the central portion of the channel lower than the impurity concentration in the vicinity of the source, the parasitic capacitance between the gate and the substrate can be reduced as compared with a conventional semiconductor device having a diffusion layer having a uniform impurity concentration. And a semiconductor device having a high driving capability can be easily formed.

Further, in the above ion implantation step, the thickness (junction depth) of the asymmetric diffusion layer 6 is reduced by implanting p-type ion species at an angle of 7 degrees or more. It can be set smaller than the thickness of the layer 2 (junction depth). Specifically, the asymmetric diffusion layer 6 is not formed so as to cover the entire source diffusion layer 2. as a result,
The impurity concentration in the region of the p-type well 11 immediately below the first n-type source diffusion layer 2 is lower than the impurity concentration on the source side of the asymmetric diffusion layer 6.

Further, according to the manufacturing method of this embodiment, prior to forming the asymmetric diffusion layer 6, the first resist 31 is formed.
And 10 Ke using the p-type gate electrode 25 as a mask.
By applying an implantation energy of V and setting an implantation dose to about 2 × 10 ¹⁴ cm ⁻² and performing an ion implantation step of implanting p-type impurity ions, for example, BF ₂ ions, into the n-type well 21. , Second p-type source / drain diffusion layers 27 and 28 corresponding to the extensions are formed. Further, using the second resist 32 and the n-type gate electrode 15 as a mask, while applying an implantation energy of 10 KeV, the implantation dose is set to about 2 × 10 ¹⁴ cm ⁻² ,
n-type impurity ions, for example, As ions, are added to the p-type well 1
By performing an ion implantation step of implanting the first and second n-type diffusion layers, second n-type source / drain diffusion layers 7 and 8 corresponding to extensions are formed.

The thus formed second n-type source / drain diffusion layers 7 and 8 have an impurity concentration of 1 ×.
10 ¹⁹ cm ^-3 or more, and these diffusion layers 7 and 8
Of the first n-type source diffusion layer 2 (junction depth D2)
And the thickness of the first n-type drain diffusion layer 3 (the junction depth D
It becomes smaller than 1). Similarly, the second p-type source / drain diffusion layers 27 and 28 have an impurity concentration of 1 × 1
0 ¹⁹ cm ⁻³ or more, and these diffusion layers 27 and 2
8 (junction depth D2) is smaller than the thickness (junction depth D1) of the first p-type source diffusion layer 22 and the first p-type drain diffusion layer 23. For this reason, the spread of the potential curve (spread of the depletion layer) from the n-type or p-type source / drain diffusion layers in the channel length direction is effectively suppressed, which causes a problem in a region having a size on the order of quarter microns or less. The deterioration of the threshold potential of the initial characteristics is suppressed.

Further, since the impurity concentrations of the second n-type source / drain diffusion layers 7 and 8 and the second p-type source / drain diffusion layers 27 and 28 are formed at 1 × 10 ¹⁹ cm ⁻³ or more. In addition, a source / drain diffusion layer having a sufficiently low resistance can be formed without causing a decrease in parasitic resistance which is a concern in a diffusion layer having a shallow junction depth.

According to the method for manufacturing a semiconductor device of the present embodiment, it is not necessary to perform an additional masking step which is required in a conventional method for manufacturing an LDC structure. If an additional masking step is required in a currently available method of manufacturing a semiconductor device, the manufacturing period of the VLSI is lengthened, and the manufacturing cost is increased. However, according to the manufacturing method of the present invention, a semiconductor device can be easily manufactured at a low cost in a short period of time.

In the above description, the step shown in FIG. 6B may be performed prior to the step shown in FIG. Similarly, the steps shown in FIG.
May be performed prior to the step shown in FIG.

Further, in this embodiment, after the second n-type source / drain diffusion layers 7 and 8 are formed by implanting n-type impurity ions using the n-type gate electrode 15 as a mask, the p-type impurity The p-type impurity diffusion layer 6 is formed by implanting ions. However,
The present invention is not limited to this. Alternatively, after the p-type impurity diffusion layer 6 is formed by implanting p-type impurity ions using the n-type gate electrode 15 as a mask, the second n-type source / drain diffusion is performed by implanting n-type impurity ions. Layers 7 and 8 may be formed.

In the method of manufacturing the complementary semiconductor device according to the present embodiment described above, the p-type impurity diffusion layer (asymmetric diffusion layer) 6 extending from the source side to the drain side of the channel is provided in the middle of the channel. It may be formed so as to end. Alternatively, if the asymmetric diffusion layer 6 is formed to reach the end on the drain side of the channel (for example, the end of the second n-type drain diffusion layer 8), the decrease in the electric field inside the channel is suppressed. Above is more effective.

In the method of manufacturing a complementary semiconductor device according to the present embodiment described above, only the n-channel MOS transistor is formed asymmetrically, and the p-channel MOS transistor is formed symmetrically. Alternatively, only the p-channel MOS transistor may be formed asymmetrically, and the n-channel MOS transistor may be formed symmetrically.

(Sixth Embodiment) FIGS. 7A to 7D
FIGS. 14A to 14C are cross-sectional views showing process steps for manufacturing a complementary semiconductor device according to the sixth embodiment of the present invention. FIGS.

First, a first insulating film to be the gate insulating film 4 of the transistor is formed on one main surface of the semiconductor substrate so as to cover the p-type well 11 and the n-type well 21 provided on the semiconductor substrate. In addition, an n-channel type MO
A conductive film used as the n-type gate electrode 15 of the S transistor and the p-type gate electrode 25 of the p-channel MOS transistor is deposited. Next, predetermined portions of the conductive film are selectively etched by photolithography and anisotropic etching until the gate oxide film 4 is exposed, so that gate electrodes 15 and 25 are formed.

Subsequently, as shown in FIG. 7A, a first resist 31 covering a p-type well (p-type region) 11, which is a region for forming an n-channel MOS transistor, is formed on the main surface of the semiconductor substrate. Deposited on And p-type impurity ions,
For example, BF ₂ ions are implanted into the n-type well 21 at an implantation dose of about 2 × 10 ¹⁴ cm ⁻² while applying implantation energy of 10 KeV using the first resist 31 and the p-type gate electrode 25 as a mask. I do. Thereby, the second
Forming a p-type source diffusion layer 27 and the second p-type drain diffusion layer 28 (implantation step of the BF ₂ ions, 7
(Not shown in (a)). Under the above conditions, the formed second p-type source / drain diffusion layers 27 and 28
Has an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ .

Further, using the first resist 31 and the p-type gate electrode 25 as a mask, while applying an implantation energy of 140 KeV, the implantation dose is about 5.0 ×.
Set to 10 ¹³ cm ^-2 and set the injection angle to 7 degrees or more, for example, 7
At this time, n-type impurity ions, for example, As ions are implanted into the n-type well 21 from the source side, and an n-type impurity diffusion layer (asymmetrical) for controlling a threshold potential as shown in FIG. (A diffusion layer) 26 is formed. Under the above conditions, the impurity concentration of the formed n-type impurity diffusion layer 26 is
At the source end it is about 7 × 10 ¹⁷ cm ^-3 and at the drain end it is about 2 × 10 ¹⁶ cm ^-3 .

Next, after removing the first resist 31, as shown in FIG. 7B, an n-type well (n-type region) 21 for forming a p-channel MOS transistor is formed.
Is deposited on the main surface of the semiconductor substrate. Then, using the second resist 32 and the n-type gate electrode 15 as a mask, n-type impurity ions, for example, As ions are implanted at an implantation dose of about 2 × 10 ¹⁴ cm ⁻² while applying an implantation energy of 10 KeV. , Into the p-type well 11. Thereby, a second n-type source diffusion layer 7 and a second n-type drain diffusion layer 8 are formed (this As ion implantation step is not shown in FIG. 7B). Under the above conditions, the impurity concentration of the formed second n-type source / drain diffusion layers 7 and 8 is about 1 × 10
²⁰ cm ^-3 .

Further, using the second resist 32 and the n-type gate electrode 15 as a mask, while applying an implantation energy of 80 KeV, an implantation dose amount of about 1.5 × 10
¹³ cm ^-2 , the implantation angle is set to 7 degrees or more, for example, 7 degrees, and p-type impurity ions, for example, BF ₂ ions are implanted into the p-type well 11 from the source side. A p-type impurity diffusion layer (asymmetric diffusion layer) 6 for controlling a threshold potential as shown in FIG. Under the above conditions,
The impurity concentration of the formed p-type impurity diffusion layer 6 is about 4 × 10 ¹⁷ cm ⁻³ at the source end, and about 1 × 1 ¹⁷ at the drain end.
It becomes 0 ¹⁶ cm ^-3 .

Next, after removing the second resist 32, an oxide film is deposited to a thickness of about 80 nm on the main surface of the semiconductor substrate. Then, the oxide film is partially removed by anisotropic dry etching so that the oxide film remains only on the side portions of the gate electrodes 15 and 25, and a gate sidewall (sidewall spacer) 12 is formed.

Next, as shown in FIG. 7C, a third resist 33 covering the n-type well (n-type region) 21 which is the formation region of the p-channel MOS transistor is formed on the main surface of the semiconductor substrate. Deposited on And n-type impurity ions,
For example, using As ion as the mask with the third resist 33, the n-type gate electrode 15 and the gate side wall 12 as masks,
About 6 × 10 ¹⁵ c while applying KeV implantation energy
An implantation dose of m ⁻² is implanted into the p-type well 11. Thereby, a first n-type source diffusion layer 2 and a first n-type drain diffusion layer 3 are formed. Under the above conditions, the impurity concentration of the first n-type source / drain diffusion layers 2 and 3 to be formed is about 3 × 10 ²⁰ cm ⁻³ .

In the previously formed p-type impurity diffusion layer 6, a portion corresponding to the lower portion of the n-type gate electrode 15 and the gate side wall 12 is the first n-type source / drain diffusion layer 2
And 3 also remain after the ion implantation step for forming them. Similarly, of the second n-type source / drain diffusion layers 7 and 8 formed earlier, a portion corresponding to the lower portion of the gate side wall 12 also remains after this ion implantation step, and the n-type source / drain diffusion layers 7 and 8 remain. / Drain diffusion layer. A portion of the p-type impurity diffusion layer 6 located below the second drain diffusion layer 8 (below the extension of the drain diffusion layer) functions as a punch-through stop layer. However, the formation of the punch-through stop layer may be omitted. Also, the formation of the gate side wall 12 is omitted,
The predetermined shape of each diffusion layer may be formed by another method.

Next, after removing the third resist 33, as shown in FIG. 7D, a p-type well (p-type region) 11 for forming an n-channel MOS transistor is formed.
Is deposited on the main surface of the semiconductor substrate. Then, p-type impurity ions, for example, BF ₂ ions are applied at a dose of about 2 × 10 ¹⁵ cm ⁻² while applying an implantation energy of 30 KeV using the fourth resist 34, the p-type gate electrode 25 and the gate side wall 12 as a mask. The n-type well 21 is implanted at an implantation dose. It is. Then, a first p-type source diffusion layer 22 and a first p-type drain diffusion layer 23 are formed. Under the above conditions, the first formed
The impurity concentration of the p-type source / drain diffusion layers 22 and 23 becomes about 3 × 10 ²⁰ cm ⁻³ .

N-type impurity diffusion layer 26 formed earlier
Among them, the portion corresponding to the lower portion of the p-type gate electrode 25 and the gate side wall 12 remains even after the ion implantation step for forming the first p-type source / drain diffusion layers 22 and 23. Similarly, of the second p-type source / drain diffusion layers 27 and 28 formed earlier, a portion corresponding to the lower portion of the gate side wall 12 also remains after this ion implantation step, and / Drain diffusion layer. A portion of the n-type impurity diffusion layer 26 located below the second drain diffusion layer 28 (below the extension of the drain diffusion layer) functions as a punch-through stop layer. However, the formation of the punch-through stop layer may be omitted. Alternatively, the formation of the gate side wall 12 may be omitted, and the predetermined shape of each diffusion layer may be formed by another method.

In the method of manufacturing a semiconductor device according to the present embodiment,
In the step shown in FIG. 7A, the p-type gate electrode 2
By using 5 as a mask and setting the implantation angle to 7 degrees or more and implanting n-type ion species from the source side,
An n-type impurity diffusion layer (asymmetric diffusion layer) 26 for controlling the threshold potential is formed. As a result, an asymmetric diffusion layer 26 having a non-uniform impurity profile in the channel and having a source-side impurity concentration higher than the drain-side impurity concentration can be easily formed without performing an extra masking step. be able to. Further, by forming the impurity concentration in the central portion of the channel lower than the impurity concentration in the vicinity of the source, the parasitic capacitance between the gate and the substrate can be reduced as compared with a conventional semiconductor device having a diffusion layer having a uniform impurity concentration. And a semiconductor device having a high driving capability can be easily formed.

Further, in the above ion implantation step, the thickness (junction depth) of the asymmetric diffusion layer 26 is reduced by implanting n-type ion species at an angle of 7 degrees or more to the first p-type source diffusion. It can be set smaller than the thickness of the layer 22 (junction depth). Specifically, the asymmetric diffusion layer 26 is not formed so as to cover the entire source diffusion layer 22. As a result, the impurity concentration in the region of the n-type well 21 immediately below the first p-type source diffusion layer 22 is
6 becomes lower than the impurity concentration on the source side.

The effect similar to that described above with respect to the asymmetric diffusion layer 26 can be obtained also with respect to the asymmetric p-type impurity diffusion layer 6 formed in the step shown in FIG.

Further, according to the manufacturing method of the present embodiment, prior to forming the asymmetric n-type diffusion layer 26, the first resist 31 and the p-type gate electrode 25 are used as masks, and
By applying an implantation energy of 0 KeV and setting an implantation dose to about 2 × 10 ¹⁴ cm ⁻² and performing an ion implantation step of implanting p-type impurity ions, for example, BF ₂ ions, into the n-type well 21. , Second p-type source / drain diffusion layers 27 and 28 corresponding to the extensions are formed. Further, prior to forming the asymmetric p-type diffusion layer 6, using the second resist 32 and the n-type gate electrode 15 as a mask, while applying an implantation energy of 10 KeV, the implantation dose is about 2 × 10 ¹⁴ cm. Set to ^-2 and n
Type impurity ions, for example, As ions
Of the second n-type source / drain diffusion layers 7 and 8 corresponding to the extensions
Is formed.

The second n-type source / drain diffusion layers 7 and 8 thus formed have an impurity concentration of 1 ×.
10 ¹⁹ cm ^-3 or more, and these diffusion layers 7 and 8
Of the first n-type source diffusion layer 2 (junction depth D2)
And the thickness of the first n-type drain diffusion layer 3 (the junction depth D
It becomes smaller than 1). Similarly, the second p-type source / drain diffusion layers 27 and 28 have an impurity concentration of 1 × 1
0 ¹⁹ cm ⁻³ or more, and these diffusion layers 27 and 2
8 (junction depth D2) is smaller than the thickness (junction depth D1) of the first p-type source diffusion layer 22 and the first p-type drain diffusion layer 23. Therefore, the expansion of the potential curve (expansion of the depletion layer) from the n-type or p-type source / drain diffusion layer in the channel length direction is effectively suppressed, which causes a problem in a region having a size on the order of quarter micron or less. The deterioration of the threshold potential of the initial characteristics is suppressed.

Further, since the impurity concentrations of the second n-type source / drain diffusion layers 7 and 8 and the second p-type source / drain diffusion layers 27 and 28 are formed at 1 × 10 ¹⁹ cm ⁻³ or more. In addition, a source / drain diffusion layer having a sufficiently low resistance can be formed without causing a decrease in parasitic resistance which is a concern in a diffusion layer having a shallow junction depth.

According to the method of manufacturing a semiconductor device of the present embodiment, it is not necessary to perform an additional masking step which is required in a method of manufacturing a conventional LDC structure. If an additional masking step is required in a currently available method of manufacturing a semiconductor device, the manufacturing period of the VLSI is lengthened, and the manufacturing cost is increased. However, according to the manufacturing method of the present invention, a semiconductor device can be easily manufactured at a low cost in a short period of time.

In the above description, the step shown in FIG. 7B may be performed prior to the step shown in FIG. 7A. Similarly, the steps shown in FIG.
May be performed prior to the step shown in FIG.

Further, in this embodiment, after the second n-type source / drain diffusion layers 7 and 8 are formed by implanting n-type impurity ions using the n-type gate electrode 15 as a mask, the p-type impurity The p-type impurity diffusion layer 6 is formed by implanting ions. However,
The present invention is not limited to this. Alternatively, after the p-type impurity diffusion layer 6 is formed by implanting p-type impurity ions using the n-type gate electrode 15 as a mask, the second n-type source / drain diffusion is performed by implanting n-type impurity ions. Layers 7 and 8 may be formed. This is because the second p-type source / drain diffusion layer 27
28, and the step of forming the n-type impurity diffusion layer 26.

In the method of manufacturing a complementary semiconductor device according to the present embodiment described above, the p-type or n-type impurity diffusion layer (asymmetric diffusion layer) 6 or 26 extending from the source side to the drain side of the channel is formed. , May be formed so as to end partway through the channel. Alternatively, if the asymmetric diffusion layer 6 or 26 is formed so as to reach the drain-side end of the channel (for example, the end of the second n-type or p-type drain diffusion layer 8 or 28), the inside of the channel can be formed. This is more effective in suppressing the decrease in the electric field of the above.

(Seventh Embodiment) In the complementary semiconductor device of the present invention described in the above embodiments, when the n-channel MOS transistor is configured to have an asymmetric impurity profile in the channel, Used in a circuit having a configuration in which a potential difference can occur between the source of an n-channel MOS transistor and a substrate during circuit operation (for example, a circuit in which two or more n-channel transistors are connected in series) When done, it has a particularly remarkable effect.

FIG. 9 is a diagram schematically showing a configuration of a two-input NAND circuit as a specific example of the above circuit.
This two-input NAND circuit generates one output C for two inputs A and B.

In a two-input NAND circuit, two n
Channel type MOS transistors 710 and 720 are connected in series. When the p-channel transistor 730 or 740 included in the circuit is turned on, the power supply voltage Vd
d is applied to two n-channel MOS transistors 710 and 720 connected in series. Therefore, the voltage actually applied to one n-channel MOS transistor 710 or 720 is V half of the power supply voltage.
dd / 2. In order to compensate for such a decrease in the driving force of the n-channel MOS transistor due to the decrease in the applied voltage, it is necessary to use an n-channel MOS transistor having a high driving ability. Therefore, a configuration having an asymmetric impurity profile in the channel is effective.

In the configuration of the two-input NAND circuit shown in FIG. 9, the source of the n-channel MOS transistor 710 is not directly connected to the GND level. For this reason,
ON / OFF operation at fast clock frequency (power supply voltage Vd
When the switching between the d level and the GND level) is repeated, the potential of the source of the n-channel MOS transistor 710 gradually becomes non-zero and enters a floating state. When a potential difference occurs between the source of the n-channel MOS transistor and the substrate in this way, the junction capacitance Cj at the pn junction between the source and the substrate affects the circuit operation through a transient phenomenon. In particular, the junction capacitance C
If j is large, a delay may occur in the circuit operation, resulting in a decrease in circuit speed.

The junction capacitance Cj at the pn junction between the source and the substrate is mainly controlled by the capacitance generated at the bottom of the source region having a large area. In the asymmetric n-channel MOS transistor obtained by the conventional technique, an asymmetric diffusion layer (high-concentration impurity diffusion layer 6 'in FIG. 1) is provided so as to surround the entire source region.
The junction capacitance Cj at the n-junction portion is relatively large, and therefore, the adverse effect of the junction capacitance on the circuit operation as described above may significantly occur. On the other hand, in the configuration of the present invention, the asymmetric diffusion layer (for example, the diffusion layer 6 in FIGS. 4 and 5) is provided only at the end of the source region so as not to cover the entire source region. As a result, since the formed junction capacitance Cj is small, it is possible to sufficiently overcome the problem that the driving capability is reduced due to the reduction in the applied voltage without lowering the circuit speed.

(Eighth Embodiment) In the complementary semiconductor device of the present invention, if the p-channel MOS transistor is configured to have an asymmetric in-channel impurity profile, the p-channel MOS Type MO
A particularly remarkable effect is obtained when used in a circuit having a configuration in which a potential difference can occur between the source of the S transistor and the substrate (for example, a circuit in which two or more p-channel transistors are connected in series). Demonstrate.

FIG. 10 is a diagram schematically showing a configuration of a two-input NOR circuit as a specific example of the above circuit.
This two-input NOR circuit generates one output C for two inputs A and B.

In the two-input NOR circuit, two p-channel MOS transistors 830 and 840 are connected in series. When the n-channel transistor 810 or 820 included in the circuit is turned on, the power supply voltage Vdd
Is applied to two p-channel MOS transistors 830 and 840 connected in series. Therefore, one p
The voltage actually applied to the channel type MOS transistor 830 or 840 is Vd which is half the power supply voltage.
d / 2. In order to compensate for the decrease in the driving force of the p-channel MOS transistor due to the decrease in the applied voltage, it is necessary to use a p-channel MOS transistor having a high driving ability. Therefore, a configuration having an asymmetric impurity profile in the channel is effective.

By the way, in the configuration of the two-input NOR circuit shown in FIG. 10, when the ON / OFF operation (switching between the power supply voltage Vdd level and the GND level) is repeated at a high clock frequency, the source of the p-channel MOS transistor 840 is changed. Gradually becomes non-zero and becomes a floating state. When a potential difference occurs between the source of the p-channel MOS transistor and the substrate in this way, the junction capacitance Cj at the pn junction between the source and the substrate affects the circuit operation through a transient phenomenon. In particular, when the junction capacitance Cj is large, a delay may occur in the circuit operation, and the circuit speed is reduced.

The junction capacitance Cj at the source / substrate pn junction is mainly controlled by the capacitance generated at the bottom of the source region having a large area. In the asymmetric p-channel MOS transistor obtained by the conventional technique, the junction capacitance Cj at the pn junction between the source and the substrate is relatively large, and therefore, the adverse effect of the junction capacitance on the circuit operation as described above occurs remarkably. obtain. On the other hand, in the configuration of the present invention, the asymmetric diffusion layer (for example, the diffusion layer 26 in FIG. 5) is provided only at the end of the source region so as not to cover the entire source region. As a result, since the formed junction capacitance Cj is small, it is possible to sufficiently overcome the problem that the driving capability is reduced due to the reduction in the applied voltage without lowering the circuit speed.

In the seventh and eighth embodiments, a circuit configuration in which a potential difference occurs between the source of one of the n-channel and p-channel MOS transistors and the semiconductor substrate will be described as an example. But
The scope of the present invention is not limited to this. For a circuit in which a potential difference occurs between the source and the semiconductor substrate in both the n-channel and p-channel MOS transistors, the n-channel and p-channel MOS transistors
By providing both S transistors with an asymmetric configuration configured according to the present invention, the effects described above can be obtained.

[0167]

As described above, according to the present invention, an asymmetric diffusion layer having an asymmetric impurity profile along the channel length direction is formed in a channel region of a semiconductor device. The impurity concentration profile of the asymmetric diffusion layer is set such that the impurity concentration on the source side is higher than the impurity concentration on the drain side. Further, the impurity concentration of the semiconductor substrate (or well) immediately below the source diffusion layer is maintained lower than the impurity concentration on the source side of the asymmetric diffusion layer. Therefore, in the semiconductor device of the present invention, the capacitance of the pn junction between the source and the substrate is L
It is smaller than a conventional semiconductor device having a DC structure.

In general, the speed of a semiconductor device is proportional to the product obtained by multiplying the load capacity and the reciprocal of the current together. Therefore, even when the semiconductor device of the present invention is applied to a NAND CMOS circuit in which a voltage is applied to a region between a source and a substrate, the speed of the device (the speed of the entire circuit) is not reduced. The power consumption of the semiconductor device is proportional to the product obtained by multiplying the load capacitance and the square of the applied voltage together. Therefore, according to the present invention, a semiconductor device which operates with low power consumption can be obtained.

Furthermore, according to the present invention, the impurity profile of the asymmetric diffusion layer is non-uniform in the channel length direction, and the impurity concentration on the source side of the channel region is formed higher than the impurity concentration on the drain side. I have. As a result, the electric field component generated in the channel length direction in the channel region increases on the source side but decreases on the drain side, as compared with the case where the impurities are uniformly distributed in the channel region. Since the saturation current of a MOS semiconductor device is dominated by the electric field on the source side, according to the present invention, a high-speed semiconductor device can be realized by increasing the saturation current. Further, since the generation rate of hot carriers is governed by the electric field on the drain side, according to the present invention, the generation rate of hot carriers can be reduced, and a highly reliable semiconductor device can be realized.

Further, since the impurity concentration of the asymmetric diffusion layer gradually decreases from the source side to the drain side, the magnitude of the electric field component generated in the channel length direction in the channel region is reduced in the vicinity of the source. Does not decrease at the center of the channel. As a result, carriers accelerated by the electric field near the source can travel inside the channel without decreasing their speed.

In addition, according to the present invention, the extension of the source / drain diffusion layer has an impurity concentration of 1 × 10 ¹⁹ cm.
^-3 or more, and the thickness of these extensions (joining depth)
Are formed so as to be smaller than the thickness (junction depth) of the body portion of the source / drain diffusion layer. Therefore, the spread of the potential curve (spread of the depletion layer) from the source / drain diffusion layers in the channel length direction is effectively suppressed, and the threshold potential of the initial characteristics which becomes a problem in a region having a size on the order of quarter micron or less. Degradation is suppressed.

If the impurity concentration of the extension of the source diffusion layer is formed higher than the impurity concentration of the extension of the drain diffusion layer, a high driving capability can be realized, and the short channel can be formed without lowering the driving capability due to the parasitic resistance. A semiconductor device having high resistance to the effect can be realized.

Further, in the complementary semiconductor device of the present invention,
The junction capacitance formed at the pn junction between the source and the substrate of the asymmetric MOS transistor is small. Therefore, even in a circuit in which a potential difference occurs between the source and the substrate of the asymmetric MOS transistor, the problem of a reduction in drive capability due to a reduction in applied voltage can be sufficiently overcome without lowering the circuit speed.

As described above, according to the present invention, a high-speed and high-reliability semiconductor device is realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of the structure of a MOS type semiconductor device having an LDC structure.

FIGS. 2A and 2B are cross-sectional views showing the structure of the semiconductor device according to the first embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views showing respective process steps for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a complementary semiconductor device according to a third embodiment of the present invention;

FIG. 5 is a sectional view showing the structure of a complementary semiconductor device according to a fourth embodiment of the present invention.

FIGS. 6A to 6D are cross-sectional views illustrating respective process steps for manufacturing a complementary semiconductor device according to a fifth embodiment of the present invention.

FIGS. 7A to 7D are cross-sectional views showing process steps for manufacturing a complementary semiconductor device according to a sixth embodiment of the present invention.

FIG. 8 is a diagram for explaining an effect of the present invention,
(A) is a diagram schematically showing a configuration of a semiconductor device obtained by the present invention, and (b) is a diagram schematically showing a potential distribution between the source / drain when a voltage is applied between the source / drain. (C) is a diagram schematically showing an electric field distribution between a source and a drain, (d) is a diagram schematically showing the speed of electrons traveling in a channel,
(E) is a diagram schematically showing the relationship between the electric field intensity and the electron velocity.

FIG. 9 is a diagram schematically showing a configuration of a two-input NAND circuit.

FIG. 10 is a diagram schematically showing a configuration of a two-input NOR circuit.

[Explanation of symbols]

 Reference Signs List 1 p-type semiconductor substrate 2 first n-type source diffusion layer 3 first n-type drain diffusion layer 4 gate oxide film 5 gate electrode 6 p-type impurity diffusion layer (asymmetric diffusion layer) 7 second n-type source diffusion Layer 8 second n-type drain diffusion layer 11 p-type well (p-type region) 12 gate side wall (sidewall spacer) 15 n-type gate electrode 20 isolation region 21 n-type well (n-type region) 22 first p-type Source diffusion layer 23 First p-type drain diffusion layer 25 N-type gate electrode 26 P-type impurity diffusion layer (asymmetric diffusion layer) 27 Second p-type source diffusion layer 28 Second p-type drain diffusion layer

Claims (25)

[Claims] A first conductive type doped first impurity;
A semiconductor substrate including a region and a second region doped with a second conductivity type impurity and having a main surface; a first MOS transistor provided in the second region; And a second MOS transistor provided in a region of the first and second MOS transistors, wherein each of the first and second MOS transistors has a first source region and a first source region. A first drain region located at a fixed distance from the first source region and the main surface of the semiconductor substrate;
A second source region having a junction depth shallower than the first source region; a second drain region located at a fixed distance from the second source region; and a first surface of the first drain region and the semiconductor substrate. In contact with
A second transistor having a junction depth shallower than the first drain region;
A drain region, a channel region located between the second source region and the second drain region, and a gate insulating film formed on the main surface of the semiconductor substrate so as to cover the channel region. And a gate electrode formed on the gate insulating film, wherein at least one of the first and second MOS transistors has a non-uniform impurity in a channel length direction in the channel region. It has the same conductivity type as the conductivity type of the corresponding region of the first and second regions formed so as to have a concentration distribution and the source-side impurity concentration is higher than the drain-side impurity concentration. Further comprising an asymmetric impurity diffusion region, wherein an impurity concentration of a portion of the semiconductor substrate located below the first source region is lower than an impurity concentration of a source-side portion of the asymmetric impurity diffusion region; A complementary semiconductor device which is an asymmetric MOS transistor. 2. The method according to claim 1, wherein the first conductivity type is n-type, and the second conductivity type is n-type.
2. The complementary semiconductor device according to claim 1, wherein the conductivity type is p-type, and said first MOS transistor is said asymmetric MOS transistor. 3. The method according to claim 2, wherein the first conductivity type is n-type, and the second conductivity type is n-type.
2. The complementary semiconductor device according to claim 1, wherein the conductivity type is p-type, and said second MOS transistor is said asymmetric MOS transistor. 4. The method according to claim 1, wherein the first conductivity type is n-type, and the second conductivity type is n-type.
The complementary semiconductor device according to claim 1, wherein the conductivity type is p-type, and each of said first and second MOS transistors is said asymmetric MOS transistor. 5. The complementary semiconductor device according to claim 1, wherein said asymmetric MOS transistor further comprises a punch-through stop layer. 6. The complementary semiconductor device according to claim 1, wherein the semiconductor device is incorporated in a circuit in which a potential difference occurs during operation between the semiconductor substrate and the source of the asymmetric MOS transistor. 7. The complementary semiconductor device according to claim 6, wherein said circuit includes a configuration in which a plurality of MOS transistors of the same conductivity type as said asymmetric MOS transistor are connected in series. 8. The method according to claim 1, wherein the first conductivity type is n-type, and the second conductivity type is n-type.
The conductivity type is p-type, the first MOS transistor is an n-channel asymmetric MOS transistor having the asymmetric impurity diffusion region, and the circuit includes the semiconductor substrate and the n-channel asymmetric M transistor.
7. The complementary semiconductor device according to claim 6, wherein the circuit has a potential difference between the source of the OS transistor and the source. 9. The method according to claim 1, wherein the first conductivity type is n-type, and the second conductivity type is n-type.
The conductivity type is p-type, the second MOS transistor is a p-channel asymmetric MOS transistor provided with the asymmetric impurity diffusion region, and the circuit includes the semiconductor substrate and the p-channel asymmetric M transistor.
7. The complementary semiconductor device according to claim 6, wherein the circuit has a potential difference between the source of the OS transistor and the source. 10. The first conductivity type is n-type, the second conductivity type is p-type, and the first MOS transistor is an n-channel asymmetric MOS transistor provided with the asymmetric impurity diffusion region. Wherein the second MOS transistor is a p-channel asymmetric MOS transistor having the asymmetric impurity diffusion region; and the circuit comprises the semiconductor substrate and the n-channel asymmetric M transistor.
7. The complementary semiconductor device according to claim 6, wherein the circuit is such that a potential difference is generated between the source of the OS transistor and between the semiconductor substrate and the source of the p-channel asymmetric MOS transistor. 11. The asymmetric MOS transistor comprises:
7. The device according to claim 6, further comprising a punch-through stop layer.
5. The complementary semiconductor device according to claim 1. 12. A semiconductor substrate including a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type and having a main surface; 2
A method of manufacturing a complementary semiconductor device comprising: a first MOS transistor provided in a first region; and a second MOS transistor provided in the first region. Forming a first insulating film and a conductive film in this order on the main surface of the semiconductor substrate so as to cover the second region; and patterning the first insulating film and the conductive film. Forming a gate insulating film and a gate electrode of the first and second MOS transistors; and forming a first resist covering the second region on the main surface of the semiconductor substrate. Using the first resist and the gate electrode of the second MOS transistor as a mask, impurity ions of the second conductivity type are implanted into the first region, whereby the second region of the second MOS transistor is implanted. Conductive source region and drain Forming a second resist, a step of removing the first resist, a step of forming a second resist covering the first region on the main surface of the semiconductor substrate, and a step of forming the second resist And using the gate electrode of the first MOS transistor as a mask, implanting impurity ions of the first conductivity type into the second region, thereby forming a source region of the first conductivity type of the first MOS transistor. And forming a drain region, and using the second resist and the gate electrode of the first MOS transistor as a mask, implanting impurity ions of the second conductivity type into the second region obliquely from the source side. Thereby, an asymmetric impurity diffusion region having an asymmetric impurity concentration profile is formed between the source region and the drain region of the first conductivity type of the first MOS transistor. And a method for manufacturing a complementary semiconductor device. 13. An extension of a source region which is in contact with a source region of the first MOS transistor and the main surface of the semiconductor substrate and has a junction depth smaller than the source region; 13. The complementary semiconductor device according to claim 12, further comprising a step of forming a drain region and an extension of the drain region which is in contact with the main surface of the semiconductor substrate and has a junction depth smaller than the drain region. Manufacturing method. 14. The method according to claim 13, wherein in the first MOS transistor, the asymmetric impurity diffusion region is formed so as to reach an end of an extension of the drain region. . 15. The semiconductor device according to claim 15, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the first MOS transistor has the asymmetric impurity diffusion region.
The method for manufacturing a complementary semiconductor device according to claim 12, wherein the method is an OS transistor. 16. The semiconductor device according to claim 16, wherein the first conductivity type is p-type, the second conductivity type is n-type, and the first MOS transistor is a p-channel type M having the asymmetric impurity diffusion region.
The method for manufacturing a complementary semiconductor device according to claim 12, wherein the method is an OS transistor. 17. The method according to claim 12, further comprising the step of configuring a circuit in which a potential difference occurs during operation between the semiconductor substrate and the source of the first MOS transistor having the asymmetric impurity diffusion region. 5. The method for manufacturing a complementary semiconductor device according to item 1. 18. The method of manufacturing a complementary semiconductor device according to claim 17, wherein said circuit includes a configuration in which a plurality of MOS transistors of the same conductivity type as said first MOS transistor are connected in series. 19. The second MOS transistor, comprising:
Between the step of forming the source and drain regions of the conductivity type and the step of removing the first resist, using the first resist and the gate electrode of the second MOS transistor as a mask, Impurity ions of the first conductivity type are obliquely implanted into the first region from the source side, whereby the second MOS transistor has the second conductivity type.
13. The method of manufacturing a complementary semiconductor device according to claim 12, further comprising the step of forming an asymmetric impurity diffusion region having an asymmetric impurity concentration profile between the conductive source and drain regions. 20. An extension of a source region that is in contact with the source region of the second MOS transistor and the main surface of the semiconductor substrate and has a junction depth smaller than the source region, 20. The complementary semiconductor device according to claim 19, further comprising a step of forming a drain region and an extension of the drain region which is in contact with the main surface of the semiconductor substrate and has a junction depth smaller than the drain region. Manufacturing method. 21. The method of manufacturing a complementary semiconductor device according to claim 20, wherein in the second MOS transistor, the asymmetric impurity diffusion region is formed so as to reach an end of an extension of the drain region. . 22. An n-channel type transistor in which the first conductivity type is n-type, the second conductivity type is p-type, and the first MOS transistor has the asymmetric impurity diffusion region.
The method for manufacturing a complementary semiconductor device according to claim 19, wherein the method is an OS transistor. 23. A semiconductor device according to claim 23, wherein said first conductivity type is p-type, said second conductivity type is n-type, and said first MOS transistor is a p-channel type M having said asymmetric impurity diffusion region.
The method for manufacturing a complementary semiconductor device according to claim 19, wherein the method is an OS transistor. 24. The semiconductor device according to claim 1, wherein the semiconductor substrate and the source of the first MOS transistor having the asymmetric impurity diffusion region, and the semiconductor substrate and the second MOS transistor having the asymmetric impurity diffusion region. 20. The method of manufacturing a complementary semiconductor device according to claim 19, further comprising a step of configuring a circuit in which a potential difference is generated during operation between each of the source and the source. 25. The circuit according to claim 25, wherein a plurality of MOS transistors of the same conductivity type as the first MOS transistor are connected in series, and a plurality of MOS transistors of the same conductivity type as the second MOS transistor are connected in series. 25. The method for manufacturing a complementary semiconductor device according to claim 24, further comprising a configuration connected to the semiconductor device.