JPH1066348A - Short-circuit protector of 3-level power converter - Google Patents

Short-circuit protector of 3-level power converter

Info

Publication number
JPH1066348A
JPH1066348A JP8215655A JP21565596A JPH1066348A JP H1066348 A JPH1066348 A JP H1066348A JP 8215655 A JP8215655 A JP 8215655A JP 21565596 A JP21565596 A JP 21565596A JP H1066348 A JPH1066348 A JP H1066348A
Authority
JP
Japan
Prior art keywords
short
circuit
gate
igbt
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8215655A
Other languages
Japanese (ja)
Other versions
JP3391025B2 (en
Inventor
Hideyoshi Dobashi
栄喜 土橋
Naoto Yoshinori
直人 義則
Mamoru Sakamoto
守 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP21565596A priority Critical patent/JP3391025B2/en
Publication of JPH1066348A publication Critical patent/JPH1066348A/en
Application granted granted Critical
Publication of JP3391025B2 publication Critical patent/JP3391025B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Protection Of Static Devices (AREA)
  • Inverter Devices (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To protect IGBT's(insulated gate bipolar transistors) of which a power converter outputting voltage of 3 levels, i.e., positive, negative and zero, from an overcurrent caused by a short-circuit, etc. SOLUTION: IGBT's 1a-1d are turned on and off by a gate controller 6 through gate drivers 2a-2d. When a short-circuit failure is detected by a short- circuit detector in the gate driver (2a, 2b, 2c or 2d), if the fact is transmitted to the gate controller 6 through a signal line (5a, 5b, 5c or 5d), the gate controller 6 controls an order in which the gate drivers are put into protective operations through a logic circuit 6A so as to avoid a prohibiting mode. With this constitution, the IGBT's are protected from excessive voltage burdens.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、絶縁ゲート形バ
イポーラトランジスタ(以下、IGBTとも略記する)
からなり、正,零,負の3レベルの電圧を出力すること
が可能な3レベル電力変換器の短絡保護装置に関する。
The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as IGBT).
And a short-circuit protection device for a three-level power converter capable of outputting three levels of positive, zero, and negative voltages.

【0002】[0002]

【従来の技術】この種の従来例を図4に示す。同図にお
いて、1a〜1dは電力変換器1相分を構成するスイッ
チング素子としてのIGBTで、例えば素子1aと1b
とをオンすること(スイッチングパターン1)で正の直
流電圧を、また、素子1bと1cとをオンすること(ス
イッチングパターン2)で零電圧を、さらに、素子1c
と1dとをオンすること(スイッチングパターン3)で
負電圧を、それぞれ出力する。
2. Description of the Related Art FIG. 4 shows a conventional example of this kind. In the figure, reference numerals 1a to 1d denote IGBTs as switching elements constituting one phase of the power converter, for example, elements 1a and 1b
To turn on (switching pattern 1) a positive DC voltage, to turn on elements 1b and 1c (switching pattern 2) to zero voltage, and to turn on element 1c
When 1 and 1d are turned on (switching pattern 3), a negative voltage is output.

【0003】2a〜2dは短絡検知装置および短絡保護
装置からなりスイッチング素子を駆動するゲート駆動装
置、6はこれらを制御するゲート制御装置である。ま
た、3a〜3dはゲート制御装置6からゲート駆動装置
2a〜2dに通常のIGBTのオン,オフ信号を伝える
信号線、5a〜5dはゲート駆動装置2a〜2dで検知
した情報をゲート制御装置6に伝える信号線を示す。
[0003] Reference numerals 2a to 2d denote a gate drive device which includes a short-circuit detection device and a short-circuit protection device and drives a switching element, and 6 denotes a gate control device which controls these devices. Reference numerals 3a to 3d denote signal lines for transmitting on / off signals of a normal IGBT from the gate control device 6 to the gate drive devices 2a to 2d. Reference numerals 5a to 5d denote information detected by the gate drive devices 2a to 2d. Are shown.

【0004】3レベル電力変換器の場合、通常に装置を
停止させるときは、直流側のIGBT1aまたは1dを
先にゲートオフし、続いて交流側のIGBT1bまたは
1cをオフするように制御している。つまり、この種の
短絡保護装置では、短絡時には即座に素子をオフするの
みで、特に素子の短絡を検知した場合に素子の短絡状態
を判別し、ゲート駆動装置の素子保護機能を一定のロジ
ックに従って動作させるなどの措置は取られていない。
In the case of a three-level power converter, when the apparatus is normally stopped, control is performed so that the IGBT 1a or 1d on the DC side is gated off first, and then the IGBT 1b or 1c on the AC side is turned off. In other words, in this type of short-circuit protection device, when a short-circuit occurs, the device is simply turned off immediately. In particular, when a short-circuit of the device is detected, the short-circuit state of the device is determined, and the device protection function of the gate drive device is determined according to a certain logic. No action has been taken to operate it.

【0005】[0005]

【発明が解決しようとする課題】ところで、3レベル電
力変換器にはスイッチング状態に或る条件を必要とし、
例えば下アームの2つのIGBT1c,1dがオンして
いる場合に、交流側のIGBT1cを先にオフすると、
負荷の電流は上アームの素子に還流し、このIGBT1
cのコレクタ側の電位は電源のPの電位まで上昇する。
また、このとき直流側のIGBT1dがオンしているの
で、エミッタ側の電位は電源のNの電位になる。したが
って、上記のようにすると短絡保護停止した素子(ここ
では1c)に電源の電圧が印加されるという問題が生じ
る。この問題は、上アームの2つの素子1a,1bがオ
ンしている場合に1bを先にオフすると、上記と同様の
問題が生じる。したがって、このような問題が生じない
ようにスイッチングを禁止するモードを以下禁止モード
と呼ぶが、この発明の課題は、この禁止モードとならな
いようにして素子の保護を図ることにある。
By the way, a three-level power converter requires a certain condition in a switching state,
For example, if the two IGBTs 1c and 1d of the lower arm are turned on and the IGBT 1c on the AC side is turned off first,
The current of the load flows back to the element of the upper arm, and this IGBT1
The potential on the collector side of c rises to the potential of P of the power supply.
Further, at this time, since the DC-side IGBT 1d is on, the emitter-side potential becomes the N potential of the power supply. Therefore, the above-described method causes a problem that the voltage of the power supply is applied to the element (1c in this case) whose short-circuit protection has been stopped. This problem is the same as described above if the two elements 1a and 1b of the upper arm are turned on and the element 1b is turned off first. Therefore, a mode in which switching is inhibited so that such a problem does not occur is hereinafter referred to as an inhibition mode. An object of the present invention is to protect the elements by preventing the inhibition mode.

【0006】[0006]

【課題を解決するための手段】このような課題を解決す
べく、請求項1の発明では、IGBTからなる3レベル
電力変換器に対し、その各IGBTのスイッチングを制
御するゲート制御部と、短絡検知回路および短絡保護回
路を有し、前記ゲート制御装置からの信号を受けて各I
GBTを駆動するゲート駆動部とを備え、IGBTを過
電流から保護するための3レベル電力変換器の短絡保護
装置において、前記ゲート制御部に短絡検知回路からの
出力に応動するロジック回路を設けるとともに、その出
力信号を前記ゲート駆動部に与える専用線を設け、短絡
検知時には前記ロジック回路により、ゲート駆動部によ
る短絡保護動作の開始順序を制御するようにしている。
In order to solve the above-mentioned problems, according to the first aspect of the present invention, a three-level power converter comprising an IGBT is provided with a gate control unit for controlling the switching of each IGBT, and a short circuit. A detection circuit and a short-circuit protection circuit.
A short-circuit protection device for a three-level power converter for protecting the IGBT from overcurrent, comprising a logic circuit responsive to an output from the short-circuit detection circuit. A dedicated line for providing the output signal to the gate drive section is provided, and when a short circuit is detected, the logic circuit controls the start order of the short-circuit protection operation by the gate drive section.

【0007】上記請求項1の発明では、前記ロジック回
路からはロック信号のみを出力し、短絡検知時には、こ
のロック信号を入力されない前記ゲート駆動部では、直
ちに短絡保護動作を開始することができ(請求項2の発
明)、または、前記短絡保護回路は常時はロックしてお
く一方、前記ロジック回路からはロック解除信号のみを
出力し、短絡検知時にそのロック解除信号を受けたとき
のみ、ゲート駆動部では直ちに短絡保護動作を開始する
ことができ(請求項3の発明)、もしくは、前記ゲート
駆動部では、短絡検知時に前記ロジック回路からの入力
信号が反転したときは直ちに、または一定期間経過後に
短絡保護動作を開始し、入力信号が反転しない場合は短
絡検知時の状態を維持することができる(請求項4の発
明)。
According to the first aspect of the present invention, only the lock signal is output from the logic circuit, and upon detection of a short circuit, the gate drive unit to which the lock signal is not input can immediately start the short-circuit protection operation ( The invention according to claim 2) or, while the short-circuit protection circuit is always locked, only the unlock signal is output from the logic circuit, and the gate drive is performed only when the unlock signal is received when the short circuit is detected. The unit can immediately start the short-circuit protection operation (the invention of claim 3), or the gate drive unit immediately upon inversion of the input signal from the logic circuit upon detection of a short circuit, or after a certain period of time has elapsed. When the short-circuit protection operation is started and the input signal is not inverted, the state at the time of short-circuit detection can be maintained (the invention of claim 4).

【0008】[0008]

【発明の実施の形態】図1はこの発明の実施の形態を示
す構成図である。同図からも明らかなように、これは図
4に示す従来例に対し、ゲート制御装置6内にロジック
回路6Aを設けた点、また、ゲート制御装置6からゲー
ト駆動装置2a〜2dの短絡保護装置に信号を伝えるた
めの信号線4a〜4dを付加した点で異なる以外は、図
4と同じである。
FIG. 1 is a block diagram showing an embodiment of the present invention. As is apparent from FIG. 4, this is different from the conventional example shown in FIG. 4 in that a logic circuit 6A is provided in the gate control device 6, and the gate control device 6 protects the gate driving devices 2a to 2d from short-circuit. This is the same as FIG. 4 except that signal lines 4a to 4d for transmitting signals to the device are added.

【0009】このような構成において、いま、IGBT
1aとIGBT1bを通るルートで通流時に、IGBT
1cが誤オンしてアーム短絡が生じた場合を想定する。
この場合、ゲート駆動装置2a〜2cによって短絡が検
知され、これが信号線5a〜5cを通してゲート制御装
置6に伝えられる。ゲート制御装置6ではこれによって
IGBT1a〜IGBT1cに短絡が発生したことを知
るとともに、ゲート駆動装置2a,2bにはオン信号,
ゲート駆動装置2c,2dにはオフ信号を出力している
ことから、IGBT1cが何らかの原因で誤点弧したこ
とを判別することができる。したがって、ゲート制御装
置6はまずゲート駆動装置2aに保護動作を開始させる
とともに、他のIGBTのゲート駆動が正規のオン,オ
フ信号によって動作しないようにロックする。次に、一
定時間後IGBT1bのゲート駆動装置2bに保護動作
を開始させる。これらの保護動作およびロックの信号
は、通常のオン,オフ信号と区別するために、専用に設
けた信号線4a〜4dにより行なう。
In such a configuration, an IGBT is
1a and IGBT1b, when passing through the route, the IGBT
Assume that 1c is turned on incorrectly and an arm short circuit occurs.
In this case, a short circuit is detected by the gate drive devices 2a to 2c, and this is transmitted to the gate control device 6 through the signal lines 5a to 5c. The gate control device 6 knows that a short circuit has occurred in the IGBTs 1a to 1c by this, and outputs an ON signal to the gate drive devices 2a and 2b.
Since the off signal is output to the gate driving devices 2c and 2d, it can be determined that the IGBT 1c has erroneously fired for some reason. Therefore, the gate control device 6 first causes the gate drive device 2a to start the protection operation, and locks the gate drive of the other IGBTs so as not to operate by the regular on / off signals. Next, after a certain time, the gate driving device 2b of the IGBT 1b starts the protection operation. These protection operation and lock signals are performed by dedicated signal lines 4a to 4d in order to distinguish them from normal on / off signals.

【0010】図2はこの発明の第2の実施の形態を示す
構成図である。この例が図1と異なる点は、ゲート駆動
装置2a〜2dの短絡検知装置はその短絡保護装置に対
し直接短絡検知信号を与えるようにするとともに、この
短絡検知信号を入力されるゲート制御装置6では、どの
ゲート駆動装置をロックするか否かのみを判定し、専用
の信号線4a〜4dを介してゲート駆動装置にロック信
号を伝送するようにした点にある。したがって、ロック
信号を受け取ったゲート駆動装置では短絡時の状態を維
持し、ロック信号を受け取らなかったゲート駆動装置で
は即座に短絡保護動作に入り、装置を保護する。
FIG. 2 is a configuration diagram showing a second embodiment of the present invention. This example is different from FIG. 1 in that the short-circuit detection devices of the gate driving devices 2a to 2d directly supply a short-circuit detection signal to the short-circuit protection device, and the gate control device 6 to which the short-circuit detection signal is input. Thus, only the gate drive device to be locked or not is determined, and a lock signal is transmitted to the gate drive device via the dedicated signal lines 4a to 4d. Therefore, the gate drive device that has received the lock signal maintains the state at the time of the short circuit, and the gate drive device that has not received the lock signal immediately enters the short-circuit protection operation to protect the device.

【0011】図2でも、IGBT1aとIGBT1bを
通るルートで通流時に、IGBT1cが誤オンしてアー
ム短絡が生じた場合を想定すると、これがゲート駆動装
置2a〜2cによって短絡が検知され、その情報が信号
線5a〜5cを通してゲート制御装置6に伝えられる。
ゲート制御装置6ではこれによってIGBT1a〜IG
BT1cに短絡が発生したことを知るとともに、ゲート
駆動装置2a,2bにはオン信号,ゲート駆動装置2
c,2dにはオフ信号を出力していることから、IGB
T1cが何らかの原因で誤点弧したことが判別できる。
したがって、ゲート制御装置6はまずゲート駆動装置2
aに保護動作を開始させるべく、ゲートロック信号は入
力せず、他のIGBTのゲート駆動が正規のオン,オフ
信号により動作しないようにロックする。次に、一定時
間後IGBT1bのゲート駆動装置2bのゲートロック
を解除し、保護動作を開始させる。これらの保護動作お
よびロック信号は通常のオン,オフ信号と区別するため
に、専用線4a〜4dにより行なうのは、図1の場合と
同様である。
In FIG. 2 as well, assuming that an IGBT 1c is erroneously turned on and an arm short circuit occurs when current flows through a route passing through the IGBT 1a and the IGBT 1b, this is detected by the gate drive devices 2a to 2c, and the information is detected. The signal is transmitted to the gate control device 6 through the signal lines 5a to 5c.
In the gate control device 6, the IGBTs 1a to IG
When it is known that a short circuit has occurred in the BT 1c, the gate drive devices 2a and 2b receive an ON signal and the gate drive device 2
Since an off signal is output to c and 2d, IGB
It can be determined that T1c is erroneously fired for some reason.
Therefore, the gate control device 6 first operates the gate drive device 2
In order to start the protection operation, the gate lock signal is not input, and the gate drive of the other IGBTs is locked so as not to be operated by regular ON / OFF signals. Next, after a certain time, the gate lock of the gate drive device 2b of the IGBT 1b is released, and the protection operation is started. The protection operation and the lock signal are performed by the dedicated lines 4a to 4d in order to be distinguished from the normal ON / OFF signal, as in the case of FIG.

【0012】上記では、ゲート制御装置6はゲートロッ
ク信号を与えるようにしたが、ゲート駆動装置が短絡保
護機能をロックした状態で維持しているものとすると、
以下のようにすることができる。すなわち、短絡検知し
た信号をゲート制御装置6が受けた時、どのゲート駆動
装置をロック解除するかのみを判断し、信号線4a〜4
cを介してゲート駆動装置にロック解除信号を伝送す
る。ロック解除信号を受け取ったゲート駆動装置は短絡
保護を開始し、ロック解除信号を受け取らなかったゲー
ト駆動装置はロック状態を保持する。
In the above description, the gate control device 6 supplies the gate lock signal. However, if the gate drive device maintains the short-circuit protection function in a locked state,
It can be as follows. That is, when the gate control device 6 receives the signal indicating the detection of the short circuit, only the gate drive device to be unlocked is determined and the signal lines 4 a to 4
The lock release signal is transmitted to the gate driving device via c. The gate drive that has received the unlock signal starts short-circuit protection, and the gate drive that has not received the unlock signal holds the locked state.

【0013】この場合も、IGBT1aとIGBT1b
を通るルートで通流時に、IGBT1cが誤オンしてア
ーム短絡が生じた場合を想定すると、これがゲート駆動
装置2a〜2cによって短絡が検知され、その情報が信
号線5a〜5cを通してゲート制御装置6に伝えられ
る。ゲート制御装置6ではこれによってIGBT1a〜
IGBT1cに短絡が発生したことを知るとともに、ゲ
ート駆動装置2a,2bにはオン信号,ゲート駆動装置
2c,2dにはオフ信号を出力していることから、IG
BT1cが何らかの原因で誤点弧したことが判別でき
る。したがって、ゲート制御装置6はまずゲート駆動装
置2aに保護動作を開始させるべく、ゲートロックを解
除する信号を入力するとともに、他のIGBTのゲート
駆動が正規のオン,オフ信号および短絡保護機能により
動作しないようにロックする。次に、一定時間後IGB
T1bのゲート駆動装置2bのゲートロックを解除し、
保護動作を開始させる。これらの保護動作およびロック
信号は通常のオン,オフ信号と区別するために、専用線
4a〜4dにより行なうのは、これ迄と同様である。
Also in this case, IGBT 1a and IGBT 1b
Assuming that the IGBT 1c is erroneously turned on and an arm short circuit occurs at the time of passage through the route, the short circuit is detected by the gate drive devices 2a to 2c, and the information is transmitted to the gate control device 6 through the signal lines 5a to 5c. Conveyed to. In the gate control device 6, the IGBTs 1a to
Since it is known that a short circuit has occurred in the IGBT 1c, an ON signal is output to the gate drive devices 2a and 2b, and an OFF signal is output to the gate drive devices 2c and 2d.
It can be determined that the BT1c has been erroneously fired for some reason. Therefore, the gate control device 6 first inputs a signal to release the gate lock in order to start the protection operation to the gate drive device 2a, and the gate drive of the other IGBTs is operated by the normal on / off signal and short-circuit protection function. Lock not to. Next, after a certain time, IGB
Release the gate lock of the gate drive device 2b of T1b,
Start the protection operation. The protection operation and the lock signal are performed by the dedicated lines 4a to 4d in order to distinguish them from the normal ON and OFF signals, as in the conventional case.

【0014】図3はこの発明の第3の実施の形態を示す
構成図である。図2と比較すれば明らかなように、この
例は図2から専用線4a〜4dを削除した点、また、ゲ
ートロック信号は信号線3a〜3dを介して伝送するよ
うにした点が特徴である。ここでは、短絡を検知したこ
とがゲート制御装置6に伝えられると、どのゲート駆動
装置を保護動作させるかのみを判断し、短絡検知時に出
力していた信号の極性を反転させる。ゲート駆動装置で
は短絡検知したことと、入力信号の極性が反転したこと
を条件に短絡保護動作を開始する。このため、短絡保護
の専用線4a〜4dを必要としない。このとき、入力信
号の極性を反転させるタイミングを互いにずらすことに
より、短絡保護動作の開始時期を遅らせることができ
る。なお、入力信号の極性が反転しないゲート駆動装置
では、短絡検知時の状態を保持する。また、オフ状態で
短絡を検知しなかったゲート駆動装置では、そのままオ
フの状態を維持するように、ゲート制御装置6からは特
に信号を出力しないようにする。この例では、短絡検知
したときにIGBT1aのゲート駆動装置2aに、信号
線3aを介して反転信号を入力し、一定時間後にはIG
BT1b,IGBT1cの順でゲート駆動装置に反転信
号を入力すれば、図1と同様の短絡保護動作を行なうこ
とができる。
FIG. 3 is a block diagram showing a third embodiment of the present invention. As apparent from comparison with FIG. 2, this example is characterized in that the dedicated lines 4a to 4d are deleted from FIG. 2, and that the gate lock signal is transmitted via the signal lines 3a to 3d. is there. Here, when the detection of the short circuit is transmitted to the gate control device 6, only the gate drive device to be protected is determined, and the polarity of the signal output when the short circuit is detected is inverted. The gate drive device starts the short-circuit protection operation on condition that the short-circuit is detected and the polarity of the input signal is inverted. Therefore, the dedicated lines 4a to 4d for short-circuit protection are not required. At this time, the start timing of the short-circuit protection operation can be delayed by shifting the timing of inverting the polarity of the input signal from each other. In the gate driving device in which the polarity of the input signal is not inverted, the state at the time of detecting the short circuit is maintained. In the gate drive device in which no short circuit is detected in the off state, the gate control device 6 does not particularly output a signal so as to maintain the off state. In this example, when a short circuit is detected, an inversion signal is input to the gate drive device 2a of the IGBT 1a via the signal line 3a, and after a predetermined time, the IGBT 1a
If an inversion signal is input to the gate drive device in the order of BT1b and IGBT1c, the same short-circuit protection operation as in FIG. 1 can be performed.

【0015】[0015]

【発明の効果】この発明によれば、短絡検知時に短絡検
知した素子の位置情報をもとに、3レベル電力変換器の
禁止モードにならないよう、ゲート駆動装置をして素子
の保護動作を行なうようにしたので、短絡保護停止時に
IGBT素子に多大な電圧責務を加えることなく装置を
停止させることが可能となる利点が得られる。
According to the present invention, when the short circuit is detected, the gate drive device performs the protection operation of the element so as not to enter the inhibition mode of the three-level power converter based on the position information of the element that has detected the short circuit. With this configuration, there is an advantage that the device can be stopped without applying a large voltage duty to the IGBT element when the short-circuit protection is stopped.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1の実施の形態を示す構成図であ
る。
FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

【図2】この発明の第2の実施の形態を示す構成図であ
る。
FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

【図3】この発明の第3の実施の形態を示す構成図であ
る。
FIG. 3 is a configuration diagram showing a third embodiment of the present invention.

【図4】従来例を示す構成図である。FIG. 4 is a configuration diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

1a〜1d…IGBT、2a〜2d…ゲート駆動装置、
3a〜3d,4a〜4d,5a〜5d…信号線、6…ゲ
ート制御装置、6A…ロジック回路。
1a to 1d IGBT, 2a to 2d gate drive device,
3a to 3d, 4a to 4d, 5a to 5d: signal line, 6: gate control device, 6A: logic circuit.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 IGBTからなる3レベル電力変換器に
対し、その各IGBTのスイッチングを制御するゲート
制御部と、短絡検知回路および短絡保護回路を有し、前
記ゲート制御装置からの信号を受けて各IGBTを駆動
するゲート駆動部とを設け、IGBTを過電流から保護
するための3レベル電力変換器の短絡保護装置におい
て、 前記ゲート制御部に短絡検知回路からの出力に応動し、
前記ゲート駆動部による短絡保護動作の開始順序を制御
するロジック回路を設けたことを特徴とする3レベル電
力変換器の短絡保護装置。
1. A three-level power converter composed of an IGBT includes a gate control unit for controlling switching of each IGBT, a short-circuit detection circuit and a short-circuit protection circuit, and receives a signal from the gate control device. A gate drive unit for driving each IGBT; and a short-circuit protection device for a three-level power converter for protecting the IGBT from overcurrent, wherein the gate control unit responds to an output from a short-circuit detection circuit,
A short-circuit protection device for a three-level power converter, further comprising a logic circuit for controlling a start order of a short-circuit protection operation by the gate driver.
【請求項2】 前記ロジック回路からはロック信号のみ
を出力し、短絡検知時には、このロック信号を入力され
ない前記ゲート駆動部では、直ちに短絡保護動作を開始
することを特徴とする請求項1に記載の3レベル電力変
換器の短絡保護装置。
2. The gate driver according to claim 1, wherein only a lock signal is output from the logic circuit, and when a short circuit is detected, the gate driver to which the lock signal is not input immediately starts a short circuit protection operation. Short-circuit protection device for a three-level power converter.
【請求項3】 前記短絡保護回路は常時はロックしてお
く一方、前記ロジック回路からはロック解除信号のみを
出力し、短絡検知時にそのロック解除信号を受けたとき
のみ、ゲート駆動部では直ちに短絡保護動作を開始する
ことを特徴とする請求項1に記載の3レベル電力変換器
の短絡保護装置。
3. The short-circuit protection circuit is always locked, while the logic circuit outputs only an unlock signal, and the gate driver immediately short-circuits only when the unlock signal is received upon detection of a short circuit. The short-circuit protection device for a three-level power converter according to claim 1, wherein a protection operation is started.
【請求項4】 前記ゲート駆動部では、短絡検知時に前
記ロジック回路からの入力信号が反転したときは直ち
に、または一定期間経過後に短絡保護動作を開始し、入
力信号が反転しない場合は短絡検知時の状態を維持する
ことを特徴とする請求項1に記載の3レベル電力変換器
の短絡保護装置。
4. The gate driving section starts a short-circuit protection operation immediately when an input signal from the logic circuit is inverted at the time of detecting a short-circuit or after a lapse of a predetermined period. The short-circuit protection device for a three-level power converter according to claim 1, wherein the state is maintained.
JP21565596A 1996-08-15 1996-08-15 Short-circuit protection device for 3-level power converter Expired - Lifetime JP3391025B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21565596A JP3391025B2 (en) 1996-08-15 1996-08-15 Short-circuit protection device for 3-level power converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21565596A JP3391025B2 (en) 1996-08-15 1996-08-15 Short-circuit protection device for 3-level power converter

Publications (2)

Publication Number Publication Date
JPH1066348A true JPH1066348A (en) 1998-03-06
JP3391025B2 JP3391025B2 (en) 2003-03-31

Family

ID=16675996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21565596A Expired - Lifetime JP3391025B2 (en) 1996-08-15 1996-08-15 Short-circuit protection device for 3-level power converter

Country Status (1)

Country Link
JP (1) JP3391025B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007185064A (en) * 2006-01-10 2007-07-19 Toshiba Mitsubishi-Electric Industrial System Corp Multi-level power conversion device
JP2012110125A (en) * 2010-11-17 2012-06-07 Fuji Electric Co Ltd Protection device for 3-level power converter
JP2012210150A (en) * 2012-08-02 2012-10-25 Toshiba Mitsubishi-Electric Industrial System Corp Multilevel power conversion device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007185064A (en) * 2006-01-10 2007-07-19 Toshiba Mitsubishi-Electric Industrial System Corp Multi-level power conversion device
JP2012110125A (en) * 2010-11-17 2012-06-07 Fuji Electric Co Ltd Protection device for 3-level power converter
JP2012210150A (en) * 2012-08-02 2012-10-25 Toshiba Mitsubishi-Electric Industrial System Corp Multilevel power conversion device

Also Published As

Publication number Publication date
JP3391025B2 (en) 2003-03-31

Similar Documents

Publication Publication Date Title
US6369543B1 (en) Method for symmetrizing asymmetric faults
EP0215897B1 (en) Inverter shoot-through protection circuit
JP6944546B2 (en) Power converter
JP2585511B2 (en) Inverter drive
JPH0753037B2 (en) Inverter protector
JP5605183B2 (en) 3-level power converter protection device
JPH1066348A (en) Short-circuit protector of 3-level power converter
JPH08298786A (en) Gate drive device for igbt
JP6129676B2 (en) VEHICLE ELECTRIC MOTOR CONTROL DEVICE AND ELECTRIC POWER STEERING CONTROL DEVICE
JPH05219752A (en) Short circuit protecting device for power converter
JP3226084B2 (en) Power transistor overcurrent limiting circuit
JP2005185003A (en) Protective device of power conversion apparatus
JP2000116144A (en) Inverter apparatus
JP4449190B2 (en) Voltage-driven semiconductor device gate drive device
JPH09182463A (en) Arm short circuit detector of voltage type inverter
JPH04322173A (en) Bridge type converter protection apparatus
JPH05236763A (en) Pulse drive circuit
JP2002199741A (en) Gate drive apparatus for igbt
WO2018188746A1 (en) Inverter switching arrangement and method
JP2001037244A (en) Power converter
JP4099703B2 (en) Gate drive circuit for voltage driven semiconductor device
JP3764259B2 (en) Inverter device
JP2002058234A (en) Failure detecting method for voltage driving semiconductor device
JP4742313B2 (en) Power converter protection system
JPH1093408A (en) Excessive current protecting circuit for igbt

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080124

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090124

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100124

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110124

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110124

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120124

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120124

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130124

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130124

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140124

Year of fee payment: 11

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term