JPH1065531A - Charge pump circuit and phase locked loop circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken a lock time of the phase locked loop(PLL) circuit and to suppress jitter. SOLUTION: For example, in the case that a feedback clock CK2 outputted from a voltage controlled oscillator (VCO) is delayed more than a clock signal CK1, a phase comparator 10 provides an output of a signal Su being a pulse having a width equivalent to the phase difference. A POMS 21 is conductive by the pulse signal Su so as to form a charging current path with respect to an LPF 40. Pulse width conversion circuits 27a, 27b convert a pulse signal whose pulse width differs from that of the pulse signal Su, and the pulse width conversion circuits 27a, 27b and switches 30a, 30b act like short-circuiting selectively constant current sources 24a-24c. Thus, the charging current of the LPF 40 is changed. A capacitor 42 in the LPF 40 is charged by the charging current. The VCO 50 is oscillated based on a voltage at an output node 43 and provides an output of the clock signal CK2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump and a signal phase locked loop (Phase Locked) circuit that generates a clock synchronized with a reference clock using the charge pump.
Loop; hereinafter, referred to as PLL).

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one shown in the following document. Reference: Japanese Utility Model Application Laid-Open No. 4-137616 The above reference discloses an entire PLL high-speed lock-up circuit using an IC.
A technology to be incorporated in the inside is disclosed, in which a charge pump is used to charge and discharge a capacitor in a filter in a PLL. The charge pump includes a constant current circuit connected to a power supply. The constant current circuit sets the charge / discharge current to a constant value, and the charge / discharge of the capacitor is performed with the charge / discharge current.

[0003]

However, the PLL using the conventional charge pump has the following problems. FIG. 2 is a circuit diagram of a PLL for explaining a conventional problem. This PLL includes a phase comparator (PC) 1 to which a reference clock CK1 is input, and a charge pump 2 connected to the phase comparator 1. Charge pump 2
Is connected to a low-pass filter (hereinafter, referred to as LPF) 3, and a voltage-controlled oscillator (hereinafter, referred to as VCO) 4 is connected to the LPF 3. The voltage-controlled oscillator 4 oscillates according to a given control voltage to generate a clock CK2, and the output clock CK2 is supplied to the phase comparator 1
The feedback input is made. The phase comparator 1
The phases of the input reference clock CK1 and the output clock CK2 of the VCO 4 are compared, and the signal S is determined according to the phase difference.
A pulse is formed on u or the signal Sd and output.

The charge pump 1 includes a PMOS 2a for inputting a signal Su to a gate and an NMOS 2c for inputting a signal Sd to a gate via an inverter 2b. The source of the PMOS 2a is connected to the power supply potential Vdd via the constant current source 2d, and the source of the NMOS 2c is connected to the ground via the constant current source 2e. PMO
The drain of S2a and the drain of NMOS 2c are connected, and the connection point between the drains is output terminal 2f of charge pump 2. The LPF 3 includes a resistor 3a having one end connected to the output terminal 2f of the charge pump 2, and a capacitor 3b having one end connected to the other end of the resistor 3a.
And The other electrode of the capacitor 3b is connected to the ground. The connection point between the resistor 3a and the capacitor 3b is the output node 3c of the LPF 3, and the node outputs the control voltage Vc of the VCO 4.

[0005] The PLL having such a configuration performs the following operation. First, when the phase of the output clock CK2 of the VCO 4 is later than the reference clock CK1, the phase comparator 1
Forms an "L" level pulse having a phase difference width in the signal Su and outputs the same to the gate of the PMOS 3a. At this time, the level of the signal Sd is, "H" remains level, is converted into a signal Sd ₁ of "L" level by the inverter 2b is applied to the gate of NMOS2c by. The PMOS 2a to which the “L” level pulse is applied turns on, and the output terminal 2
f is connected to the constant current source 2d and the power supply potential Vdd.
As a result, a constant current set by the internal resistance of the constant current source 2d flows to the capacitor 3b via the resistor 3a, and the capacitor 3b is charged. Therefore, voltage Vc of output node 3c increases. When the control voltage Vc increases, VCO4
And the phase of the output clock CK2 becomes faster.

Conversely, if the phase of the output clock CK2 of the VCO 4 is earlier than the reference clock CK1, the phase comparator 1
Forms an "L" level pulse of the width of the phase difference in the signal Sd. At this time, the level of the signal Su remains at the “H” level. Signal Sd is supplied is converted by the inverter 2b to the signal Sd ₁ and the gate of NMOS2c. NMOS2c is turned on by "H" level of the pulse signal Sd _1, an output terminal 2f and the constant current source 2e and the ground are connected. The constant current set by the constant current source 2c flows out of the capacitor 3b via the resistor 3a and flows to the ground. That is, discharging to the capacitor 3b is performed, and the voltage Vc of the output node 3c decreases due to the discharging. When the voltage Vc decreases, the oscillation frequency of the VCO 4 decreases, and the phase of the output clock CK2 delays. The above operation is repeated, and the output clock CK2 of the VCO 4 is output.
And the reference clock CK1 are reduced in phase difference. When the phases match, both the signal Su and the signal Sd become “H”.
Level, and the voltage of the output node 3c of the LPF 3 is fixed. In this state, the VCO 4 oscillates at a constant frequency, and the PLL is locked.

In the conventional PLL shown in FIG. 2, the capacitor 3b connected to the node 3d is charged by the constant current source 2
The discharge is performed with the current set by d, and the discharge to the capacitor 3b is performed with the constant current set by the constant current source 2e. If the constant current sources 2d and 2e are of a small current type and the amount of the constant current is small, it takes a long time to charge and discharge the capacitor 3b, which leads to an increase in the lock time.
Conversely, when the constant current sources 2d and 2e are of a large current type and have a large amount of constant current, the charging and discharging time of the capacitor 3b is reduced, but the voltage of the node 3c becomes unstable. This is V
The oscillation frequency of CO4 is fluctuated, causing an increase in jitter. That is, when the phase difference is large as in the initial stage of the operation process of the phase synchronization, the constant current sources 2d and 2d
e is preferably a large current type, and it is better that the constant current sources 2d and 2e are of a small current type when the phase difference becomes small after a certain period of time. However, P using a conventional charge pump
In the LL, the charge / discharge current is kept constant irrespective of the phase difference, so that the lock time becomes longer or the jitter increases.

[0008]

According to a first aspect of the present invention, there is provided a charge pump having the following switching element, a plurality of current control means, and a pulse width converter. A circuit and a switch are provided. The switching element is provided between the power supply and the output terminal, and connects the power supply and the output terminal during a period when an input pulse is given. The plurality of current control means are connected in series or in parallel between the power supply and the output terminal to form a current path. The pulse width conversion circuit has a function of generating and outputting a pulse having a width different from that of the input pulse during a period when the input pulse is given. The switch has a function of turning on or off according to a pulse output from the pulse width conversion circuit, and changing a current path between a power supply and an output terminal. A phase comparator, a charge pump, a voltage setter having a capacitor that is charged and discharged by a charge / discharge current input / output by the charge pump and sets a voltage of an output node, and an oscillator that performs frequency according to an output voltage of the voltage setter And a PLL having
The operation of the charge pump of the first invention is as follows.

In the PLL, a phase comparator compares a reference signal and a feedback signal, and outputs a pulse signal corresponding to a phase difference between the reference signal and the feedback signal. In the charge pump, the switching means conducts between the power supply and the output terminal in response to the pulse signal, and inputs and outputs a charge / discharge current. The capacitor of the voltage setting device sets the voltage of the output node by being charged / discharged by the charge / discharge current input / output of the charge pump. When the oscillator oscillates at a frequency corresponding to the output voltage of the voltage setting device, the feedback signal is generated. Here, the pulse width conversion circuit provided in the charge pump of the first invention outputs a pulse having a width different from the pulse width during a period when the pulse signal output from the phase comparator is being input. The switch is turned on and off according to the pulse output from the pulse width conversion circuit, and changes the current path between the power supply and the output terminal. That is, the value of the charging / discharging current input / output to / from the voltage setting device via the output terminal changes. Thereby, for example, when the phase difference between the reference signal and the feedback signal is large, the value of the charging / discharging current is set to a large current value, the voltage change of the output node is fast, and when the phase difference is small, the value is small. The current value is set, and the voltage change at the output node becomes slow. Therefore, the above problem can be solved.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a PLL showing a first embodiment of the present invention. This PLL includes a reference clock C which is a reference signal.
A phase comparator (CP) 10 for generating a clock CK2 phase-synchronized with K1 and receiving the reference clock CK1 and the generated clock CK2. A charge pump 20 is connected to the phase comparator 10, and an LPF 40, which is a voltage setting device for setting the control voltage Vc, is connected to the charge pump 20. LPF40
The oscillation of the control voltage Vc causes the clock C
The VCO 50 that generates K2 is connected. The clock CK2 is connected to the phase comparator 10 as a feedback signal. The phase comparator 10 corresponds to the phase comparator 1 shown in FIG.
Similarly to the above, the phase of the reference clock CK1 is compared with the phase of the feedback clock CK2 from the VCO 50, and the comparison result is output using two pulse signals Su and Sd. The signal Su is an up signal that speeds up the phase of the clock CK2. The signal Sd is do which delays the phase of the clock CK2.
wn signal. When the phase of the feedback clock CK2 is delayed as a result of the comparison, the phase comparator 10 forms a pulse having a width corresponding to the phase difference in the signal Su, and when the phase of the output clock CK2 is advanced, A pulse having a width corresponding to the phase difference is formed in the signal Sd.

The charge pump 20 includes a PMOS 21 as a switching element for inputting a signal Su to a gate, and an NMOS 23 as a switching element for inputting a signal Sd to a gate via an inverter 22. The source of the PMOS 21 as the first node and the power supply potential Vd
The constant current sources 24a, 24b, and 24c constituting three current control means are connected in series between the current sources d and d. Similarly, between the source of the NMOS 23 and the ground G, there are constant current sources 25a, 25b, 25c as three current control means.
Are connected in series. PMOS 21 drain and N
The drain of the MOS 23 is connected to the output terminal 26 of the charge pump 20.
It has become. The constant current sources 24a to 24c form a plurality of resistors, and the constant current sources 25a to 25c form a plurality of resistors. That is, each of the constant current sources 24a to 24
The internal resistances c, 25a to 25c form a current path for the charging / discharging current and act to set the value of the charging current or the discharging current constant. This charge pump 20
Further, two pulse width conversion circuits 27a and 27b for inputting a pulse formed in the signal Su and outputting pulses having different widths, and inputting a pulse formed in the signal Sd to output different widths , And two inverters 29a and 29b connected to the output sides of the pulse width conversion circuits 28a and 28b, respectively, and two switches 30a and 30b. Switch circuit 30 and two switches 31a, 3
1b is provided.

FIG. 3 shows a pulse width conversion circuit 27 shown in FIG.
It is a circuit diagram which shows the structure of a, 27b, 28a, 28b. Each pulse width conversion circuit 27a, 27b, 28a, 28
b denotes an inverter 33 for inputting the signal Su or the signal Sd, a resistor 34 having one end connected to the output side of the inverter 33, and one electrode connected to the other end of the resistor 34,
A capacitor 35 having the other electrode connected to the ground,
It comprises an inverter 37 connected to a connection point 36 between a resistor 34 and a capacitor 35. That is, although the insides of the pulse width conversion circuits 27a, 27b, 28a, and 28b are connected in the same manner, the capacitor value of the capacitor 35 and the resistance value of the resistor 36 are equal to each other.
Unique time constants are set for 7a, 27b, 28a, and 28b, respectively. The time constants of the pulse width conversion circuits 27b and 28b are set to be larger than the time constants of the pulse width conversion circuits 27a and 28a.

While the pulse is being output from the pulse width conversion circuit 27a, the switch 30 of the switch circuit 30 in FIG.
The switch 30b is turned on during a period in which a is turned on and a pulse is output from the pulse width conversion circuit 27b.
The switch 31a of the switch circuit 31 shown in FIG. 1 is turned on during a period when a pulse is output from the pulse width conversion circuit 28a, and the switch 31b is turned on during a period when a pulse is output from the pulse width conversion circuit 28b. The switch 30a is configured to short-circuit both ends of the constant current source 24a, and the switch 30b is connected to the constant current source 24 connected in series.
a, 24b are short-circuited at both ends. Switch 31
a is a configuration in which both ends of the constant current source 25a are short-circuited, and the switch 31b includes constant current sources 25a, 25 connected in series.
b is configured to short-circuit both ends. The LPF 40 includes a resistor 4 having one end connected to the output terminal 26 of the charge pump 20.
1 and a capacitor 42 having one end connected to the other end of the resistor 41. The other electrode of the capacitor 42 is connected to the ground. A connection point between the resistor 41 and the capacitor 42 is an output node 43 of the LPF 40, and the node 43 outputs the control voltage Vc of the VCO 50.

Next, the operation of the PLL will be described with reference to FIGS. FIG. 4 is a time chart (No. 1) showing the operation of FIG. 1, and shows a signal waveform when the phase of the clock CK2 is delayed. The phase of the clock CK2 generated by the oscillation of the VCO 50 is
If it is later than K1, the phase comparator 10 outputs the signal Su.
The first pulse p1 at the “L” level having a width corresponding to the phase difference φ
Is formed and output. The pulse p1 formed in the signal Su
Is given to the gate of the PMOS 21 and the PMOS 21 is turned on. The pulse p1 is also given to the pulse width conversion circuits 27a and 27b. At this time, the signal Sd is
The “H” level is maintained, and the signal Sd ₁ inverted by the inverter 22 is maintained at the “L” level.

FIG. 5 is a waveform chart for explaining the operation (1) of FIG. In each of the pulse width conversion circuits 27a and 27b, the inverter 33 inverts the logic level of the signal Su. That is, when the pulse p1 is given, the voltage level output from the inverter 33 increases, and the capacitor 35 is charged via the resistor 34. This charging causes the voltage at the connection point 36 to rise. The inverter 37 determines the voltage at the connection point 36 based on the threshold value _Vth , and outputs “H” as the determination result.
Here, the voltage rise at the connection point 36 depends on the time constant set by the resistor 34 and the capacitor 35. The voltage at the connection point 36 in the pulse width conversion circuit 27a having a small time constant rises quickly. When the period of the pulse p1 has passed, the inverter 33
And the voltage at the node 36 also decreases, and the inverter 37 outputs "L". That is, each of the pulse width conversion circuits 27a and 27b changes the pulse width of the pulse p1, and forms and outputs pulses having different widths.

For example, when the phase difference φ between the reference clock CK1 and the returned clock CK2 is large, as in the period (1) shown in FIG. 4, the pulse width conversion circuit 27a has a pulse width wider than the pulse p1. A small pulse p2 is output, and the pulse width conversion circuit 27b outputs a pulse p3 having a smaller pulse width. The switches 30a and 30b are turned on by these pulses p2 and p3, the constant current sources 24a and 24b are short-circuited, and the constant current sources 24
c is connected to the power supply Vdd. In this state, the PMOS
This is equivalent to connecting only the internal resistance of the constant current source 24c between the source of the power supply 21 and the power supply Vdd, and the capacitor 4 has a current set by the internal resistance of the constant current source 24c.
2 is charged.

When the phase difference φ between the reference clock CK1 and the feedback clock CK2 is small as in the period (2) shown in FIG. 4, the pulse width conversion circuit 27a outputs a pulse p2 having a width smaller than the pulse p1. I do. However, in the pulse width conversion circuit 27b, the voltage at the connection point 36 is set to the threshold voltage V
pulse p3
Is not output. In this case, the switch 30a is turned on by the pulse p2, only the constant current source 24a is short-circuited, and the constant current sources 24b and 24c are connected to the power supply Vdd. That is, between the source of the PMOS 21 and the power supply Vdd, it is equivalent to the internal resistances of the constant current source 24c and the constant current source 24b connected in series. , The capacitor 42 is charged. When the phase difference φ between the reference clock CK1 and the fed back clock CK2 is smaller than that in (2), as in the period (3) shown in FIG. 4, the pulse width conversion circuit 27a also takes no charge time and the pulse p2 Will not be output. In this case, the switches 30a and 30b are both off, and the serial constant current source 24
a, 24b and 24c are connected to the power supply Vdd. That is, the internal resistances of the constant current sources 24a, 24b and 24c are connected in series between the source of the PMOS 21 and the power supply Vdd, and the capacitor 42 is charged with a current set by the serial internal resistances.

FIG. 6 is a time chart (No. 2) showing the operation of FIG. 1, and shows a signal waveform when the phase of the clock CK2 is advanced. When the clock CK2 generated by the oscillation of the VCO 50 is ahead of the reference clock CK1, the phase comparator 10 adds the phase difference φ to the signal Sd.
A second pulse p4 of "L" level having a width of one minute is formed and output. The pulse p4 formed in the signal Sd is inverted to the “H” level by the inverter 22 and given to the gate of the NMOS 23, and the NMOS 23 is turned on. Also,
The pulse p4 is also given to the pulse width conversion circuits 28a and 28b. On the other hand, signal Su is maintained at the “H” level. FIG. 7 is a waveform diagram illustrating the operation (part 2) of FIG. In each of the pulse width conversion circuits 28a and 28b, the inverter 33 inverts the logic level of the signal Sd. That is,
When the pulse p4 is given, the voltage level output from the inverter 33 rises to “H” level, and the capacitor 35 is charged via the resistor 34. By this charging, connection point 3
The voltage of 6 rises. The inverter 37 determines the voltage at the connection point 36 based on the threshold value _Vth , and outputs an “H” level as a result of the determination. Here, the voltage rise at the connection point 36 is caused by the resistance 34
And the time constant set by the capacitor 35.
The voltage rise at the connection point 36 in the pulse width conversion circuit 28a having a small time constant is fast. After the period of the pulse p4, the output voltage of the inverter 33 drops and the voltage of the connection point 36 also drops, and the inverter 37 outputs "L". That is, the operation similar to that of FIG.
a and 28b change the pulse width of the pulse p4, and
Pulses having different widths are formed and output. The pulses output from the pulse width conversion circuits 28a and 28b are inverted to "H" level by the inverters 29a and 29b, and supplied to the switches 31a and 31b.

For example, when the phase difference φ between the reference clock CK1 and the returned clock CK2 is large, as in the period (4) shown in FIG. 6, the pulse width conversion circuit 28a has a pulse width that is larger than the pulse p4. A small pulse p5 is output, and the pulse width conversion circuit 28b outputs a pulse p6 having a smaller pulse width. Inverter 29
The switches 31a and 31b are turned on by the pulses p5 and p6 inverted via the signals a and 29b, and the constant current source 25
a and 25b are short-circuited, and the constant current source 25c is connected to the ground. In this state, it is equivalent to that only the internal resistance of the constant current source 25c is connected between the source of the NMOS 23 and the ground, and the capacitor 42 is set by the current set by the internal resistance of the constant current source 25c. Discharged. When the phase difference φ between the reference clock CK1 and the fed back clock CK2 is small as in the period (5) shown in FIG. 6, the pulse width conversion circuit 28a outputs a pulse p5 having a width smaller than the pulse p4. However, the pulse width conversion circuit 28
In b, the pulse p6 is not output because there is no charging time for raising the voltage of the connection point 36 to the threshold voltage Vth or more.
In this case, the switch 31a is turned on by the pulse p5, and only the constant current source 25a is short-circuited.
25c is connected to the ground. That is, NMOS2
3 is equivalent to connecting the internal resistances of the constant current source 25c and the constant current source 25b in series between the source and the ground.
The capacitor 42 is discharged.

When the phase difference φ between the reference clock CK1 and the feedback clock CK2 is smaller than that in (5) as in the period (6) shown in FIG. 6, the pulse width conversion circuit 28
In the case of a, the charging time is not sufficient, and the pulse p5 is not output. In this case, the switches 31a and 31b are both off, and the constant current sources 25a, 25b and 25c in series are connected to the ground. That is, the internal resistances of the constant current sources 25a, 25b, and 25c are connected in series between the source of the NMOS 23 and the ground, and the capacitor 42 is discharged with a current set by these serial internal resistances. The capacitor 42 charges or discharges, and the voltage of the node 43 of the LPF 40 is set. This voltage becomes the control voltage Vc of the VCO 50. VCO 50 oscillates at a frequency based on control voltage Vc and outputs clock CK2. When the control voltage Vc is high, the phase of the clock CK2 is advanced, and when the control voltage Vc is low, the clock CK2 is delayed so that the VCO 50
Oscillates. The PLL repeats the above operation to obtain V
The phase difference between the output clock CK2 (feedback clock) of the CO 50 and the reference clock CK1 is reduced. When the phases match, both the signal Su and the signal Sd become “H” level, and the voltage of the output node 43 of the LPF 40 is fixed. When this occurs, the VCO 50 oscillates at a constant frequency, and the PLL is locked.

As described above, in the first embodiment,
Pulse width conversion circuits 27a, 27b, 28a, which change the widths of the pulses p1 and p4 to form pulses having different widths.
28b and switch circuits 30 and 31, and a constant current source 2 disposed in a charge / discharge route in the charge pump 20.
4a to 24c and 25a to 25c are configured to be selectively short-circuited according to the widths of the pulses p1 and p4. For example,
If the width of the pulse p1 is wide, the constant current sources 27a and 27b are short-circuited, and the charging current for the capacitor 42 becomes a large current value determined by the internal resistance of the constant current source 27c and the resistor 41. Conversely, if the width of the pulse p1 is narrow, the constant current source 27
a and 27b are not short-circuited, and the charging current to the capacitor 42 has a small current value determined by the combined resistance of the internal resistances of the constant current sources 27a, 27b and 27c and the resistance 41. The same applies to the discharge current. That is, each of the constant current sources 24a to 24c,
Assuming that the resistance values of the resistors 25a to 25c are r and the resistance value of the resistor 41 is R, the resistance values of the charging route and the discharging route when the widths of the pulses p1 and p4 are large are (r + R), respectively.
When the widths of the pulses p1 and p4 are small, (3r + R)
become. Therefore, the lock time when the phase difference φ is large as in the initial stage of the control can be shortened, and even when the control is advanced and the phase difference φ is small, the P time which does not cause an increase in jitter can be obtained.
LL can be configured.

Second Embodiment FIG. 8 is a circuit diagram of a PLL showing a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals. This PLL includes the same phase comparator 10, LPF 40, and VCO 50 as in the first embodiment, and a charge pump 60 provided between the phase comparator 10 and LPF 40 and different from FIG. The charge pump 60 includes a PMOS 61 that is a switching element that inputs a signal Su from the phase comparator 10 to a gate, and an NMOS 63 that is a switching element that inputs a signal Sd to a gate via an inverter 62. PM
The source of the OS 61 is connected to the power supply potential Vdd.
The drains of the OS 61 are connected to the constant current sources 64a, 64b, and 6 as three current limiting means via the first node N2a.
4c are sequentially connected in series. The source of the NMOS 63 is connected to the ground, and the drain of the NMOS 63 is connected to three constant current sources 65a, 65a through a first node N2b.
65b and 65c are connected in series in order. The other end of the series constant current sources 64a, 64b, 64c and the constant current source 65
The other ends of the terminals a, 65b, and 65c are connected to the output terminal 66 of the charge pump 60.

The charge pump 60 further receives a signal Su
Width conversion circuit 2 similar to the first embodiment, which receives the pulses formed in the first embodiment and outputs pulses having different widths from each other
7a, 27b, pulse width conversion circuits 28a, 28b for inputting pulses formed in the signal Sd and outputting pulses of different widths, switches 29a, 29b, and switches having two switches 30a, 30b. Circuit 30
And a switch circuit 31 having switches 31a and 31b
Are provided. That is, the PM of the switching element
A plurality of constant current sources 64a to 64c are connected between the OS 61 and the output terminal 66 of the charge pump, and a plurality of constant current sources 65 are connected between the NMOS 63 of the switching element and the output terminal 66.
The feature of the second embodiment is that a to 65c are connected, and the other points are the same as those of the first embodiment. The switch 30a is configured to short-circuit both ends of the constant current source 64a, and the switch 30b is connected to the constant current source 6 connected in series.
In this configuration, both ends of 4a and 64b are short-circuited. Switch 3
1a is a configuration in which both ends of the constant current source 65a are short-circuited,
The switch 31b includes constant current sources 65a, 6 connected in series.
5b is configured to short-circuit both ends.

In the PLL of FIG. 8, the PMOS 61 and the LPF
Constant current sources 64 a to 64 c are arranged between the capacitors 42 in the capacitor 40, and constant current sources 65 a to 64 c are arranged between the NMOS 63 and the capacitor 42.
65c are arranged. These constant current sources 64a to 64
When the internal resistances of the capacitors c and 65a to 65c are constituted by diffusion resistances, a parasitic capacitance (not shown) is arranged between the PMOS 61 and the NMOS 63 and the capacitance 42, and the charge / discharge time of the capacitance 42 slightly increases. The charge / discharge time of the capacitor 42 can be changed by the same operation as in the first embodiment. That is, the constant current sources 24a to 24c and 25a to 25c in FIG.
, The constant current sources 64a to 64c and 65a to 65c respectively function. The capacitor 42 charges or discharges, LP
The voltage of the node 43 of F40 is set. This voltage is V
It becomes the control voltage Vc of CO50. VCO 50 oscillates at a frequency based on control voltage Vc and outputs clock CK2. When the control voltage Vc is high, the phase of the clock Ck2 advances, and when the control voltage Vc is low, the VCO 50 oscillates so that the clock CK2 is delayed. The PLL reduces the phase difference between the output clock CK2 of the VCO 50 and the reference clock CK1 by repeating the above operation.
When the phases match, both the signal Su and the signal Sd become “H” level, and the voltage of the output node 43 of the LPF 40 is fixed. When this occurs, the VCO 50 oscillates at a constant frequency, and the PLL is locked.

As described above, in the second embodiment,
Pulse width conversion circuits 27a, 27b, 28a, 28b for forming pulses having different widths as in the first embodiment;
Switch circuits 30 and 31 are provided;
Constant current sources 64a to 64 arranged in the charge / discharge route in
c, 65a to 65c are selectively short-circuited. Therefore, similarly to the first embodiment, the lock time when the phase difference φ is large as in the initial stage of control can be shortened,
Further, even when the control is advanced and the phase difference φ is small, it is possible to configure a PLL that does not cause an increase in jitter. On the other hand, in FIG. 8, constant current sources 64a to 64c are arranged between the PMOS 61 and the capacitor 42 in the LPF 40, and the NMOS 63 and the capacitor 42 are connected.
The constant current sources 65a to 65c are arranged therebetween. For example, by devising the switch circuits 30 and 31, the constant current sources 64a to 64c can be shared for charging and discharging, and the constant current sources 65a to 65c can be omitted.

Third Embodiment FIG. 9 is a circuit diagram of a PLL showing a third embodiment of the present invention. Elements common to those in FIGS. 1 and 8 are denoted by the same reference numerals. I'm This PLL comprises the same phase comparator 10, LPF 40, and V as in the first and second embodiments.
A CO 50 and a charge pump 70 provided between the phase comparator 10 and the LPF 40 and different from those in FIGS. 1 and 8 are provided. The charge pump 70 includes the phase comparator 1
A PMOS 71 as a switching element for inputting a signal Su from 0 to a gate and an NMOS as a switching element for inputting a signal Sd to a gate via an inverter 72
73 are provided. Between the source of the PMOS 71 and the power supply potential Vdd, three constant current sources 74a, 74b and 74c as current control means are connected in parallel. NMO
Constant current sources 75a, 75b, and 75c, which are three current control means, are connected in parallel between the source of S73 and the ground. The drain of the PMOS 71 and the drain of the NMOS 73 are connected to the output terminal 76 of the charge pump 70.

The charge pump 70 further receives a signal Su
Width conversion circuit 2 similar to the first embodiment, which receives the pulses formed in the first embodiment and outputs pulses having different widths from each other
7a and 27b, pulse width conversion circuits 28a and 28b that input pulses formed in the signal Sd and output pulses of different widths, and inverters 29a and 29b that invert the output signals of the pulse width conversion circuits 28a and 28b. And a switch circuit 80 and a switch circuit 81. The switch circuit 80 includes a constant current source 74a and a PMOS 7
A switch 80a for opening between the two sources, and a constant current source 7
Switch 80 for opening between 4b and the source of PMOS 71
b. The switch circuit 81 includes a switch 8 that opens between the constant current source 75a and the source of the NMOS 73.
1a and a switch 81b that opens between the constant current source 75b and the source of the NMOS 73. The switch 80a is switched by the pulse output from the pulse width conversion circuit 27a.
Is turned on, and the switch 80b is turned on by a pulse output from the pulse width conversion circuit 27b. The switch 81a is turned on by a pulse output from the pulse width conversion circuit 28a, and the switch 81b is turned on by a pulse output from the pulse width conversion circuit 28b.

Next, the operation of the PLL shown in FIG. 9 will be described. The operations of the phase comparator 10, the LPF 40, the VCO 50, and the pulse width conversion circuits 27a to 28b are the same as those in the first embodiment.
Since the embodiment is the same as that of the first embodiment, FIGS. The phase comparator 10 outputs the clock CK2
Is later than the reference clock CK1,
As shown in FIG. 4, the signal Su forms and outputs an "L" level first pulse p1 having a width corresponding to the phase difference φ. The pulse p1 formed in the signal Sd is given to the gate of the PMOS 71, and the PMOS 71 is turned on. Also, the pulse p
1 is also supplied to the pulse width conversion circuits 27a and 27b.
At this time, the level of signal Sd is maintained at “H” level, and signal Sd ₁ output from inverter 72 is maintained at “L” level.

When the phase difference φ between the reference clock CK1 and the fed back clock CK2 is large as in the period (1) shown in FIG. 4, the pulse width conversion circuit 27a outputs a pulse having a width smaller than the width of the pulse p1. p2, and the pulse width conversion circuit 27b outputs a pulse p3 having a smaller pulse width. By these pulses p2 and p3,
The switches 80a, 80b are turned on, and the respective constant current sources 74a,
74b and the PMOS 71 are connected. That is, a parallel current path including the three constant current sources 74a, 74b, and 74c is configured between the LPF 40 and the power supply potential Vdd. Therefore, the capacitor 42 is connected to these parallel constant current sources 74a, 74a.
b, 74c to charge from the power supply potential Vdd. When the phase difference φ between the reference clock CK1 and the fed back clock CK2 is small as in the period (2) shown in FIG. 4, the pulse width conversion circuit 27a outputs a pulse p2 having a smaller width than the pulse p1. However, the pulse width conversion circuit 27
In b, the pulse p3 is not output because there is no charging time for raising the voltage of the connection point 36 to the threshold voltage Vth or more.
In this case, the switch 80a is turned on by the pulse p2, and the constant current source 74a is connected to the PMOS 71. That is, a parallel current path including the constant current source 74a and the constant current source 24c is formed between the source of the PMOS 71 and the power supply Vdd, and the capacitor 42 is charged via the constant current sources 74a and 74.

When the phase difference φ between the reference clock CK1 and the fed back clock Ck2 is smaller than that in (2), as in the period (3) shown in FIG.
In the case of a, the pulse p2 is not output because the charging time of the capacitor 35 is not sufficient. In this case, the switches 60a and 80b are both opened, and only the constant current source 74c is connected between the PMOS 71 and the power supply potential Vdd. Therefore, the capacity 42
Is charged via the constant current source 74c. The clock CK2 generated by the oscillation of the VCO 50 is used as the reference clock CK1.
When the phase is more advanced, the phase comparator 10 forms and outputs the second pulse p4 of “L” level having a width corresponding to the phase difference φ to the signal Sd. Inverter 72 outputs signal Sd ₁ obtained by inverting the level of signal Sd. That is, the pulse p4 is inverted by the inverter 72 and given to the gate of the NMOS 73, and the NMOS 73 is turned on. The pulse p4 is also given to the pulse width conversion circuits 28a and 28b. On the other hand, the signal Su is maintained at the “H” level.

For example, when the phase difference φ between the reference clock CK1 and the fed back clock CK2 is large as in the period (4) shown in FIG. 6, the pulse width conversion circuit 28a has a pulse width larger than the pulse p4. A small pulse p5 is output, and the pulse width conversion circuit 28b outputs a pulse p6 having a smaller pulse width. The switches 81a and 81b are turned on by these pulses p5 and p6, and the constant current sources 75a and 75b are connected to the source of the NMOS 73. Therefore, between the ground and the NMOS 73,
A parallel current path including the constant current sources 75a, 75b, and 75c is formed. The discharge current from the capacitor 42 flows to the ground via the parallel constant current sources 75a, 75b, 75c. When the phase difference φ between the reference clock CK1 and the fed back clock CK2 is small as in the period (5) shown in FIG. 6, the pulse width conversion circuit 28a outputs a pulse p5 having a width smaller than the pulse p4. However, the pulse width conversion circuit 28
In b, the pulse p6 is not output because there is no charging time for raising the voltage of the connection point 36 to the threshold voltage Vth or more. In this case, only the switch 81a is turned on by the pulse p5, the constant current source 75a is connected to the NMOS 73, and a parallel current path including the constant current sources 75a and 75c is formed.
The discharge current from the capacitor 42 is supplied to the parallel constant current sources 75a, 75
Flow to ground via 5c.

When the phase difference φ between the reference clock CK1 and the feedback clock Ck2 is smaller than that in (5), as in the period (6) shown in FIG. 6, the pulse width conversion circuit 28
In the case of a, the charging time is not sufficient, and the pulse p5 is not output. In this case, the switches 31a and 31b are both open and the constant current source 25c is connected between the ground and the NMOS 73.
Only the connected state. Therefore, the discharge current from the capacitor 42 flows to the ground via the constant current source 75c. The capacitor 42 charges or discharges, and the voltage of the node 43 of the LPF 40 changes. This voltage becomes the control voltage Vc of the VCO 50. VCO 50 oscillates at a frequency based on control voltage Vc and outputs clock CK2. Control voltage V
When c is high, the phase of the clock CK2 is advanced, and when the control voltage Vc is low, VCK is delayed so that the clock CK2 is delayed.
The CO 50 oscillates. The PLL reduces the phase difference between the output clock CK2 of the VCO 50 and the reference clock CK1 by repeating the above operation. When the phases match, both the signal Su and the signal Sd become “H” level, and the voltage of the output node 43 of the LPF 40 is fixed.
When this occurs, the VCO 50 oscillates at a constant frequency, and the PLL is locked.

As described above, in the third embodiment,
Pulse width conversion circuits 27a, 27b, 28a, 28b;
Switch circuits 80 and 81 are provided;
Constant current sources 74a to 74c, 75a to 7
5c is selectively connected to the charging / discharging route according to the widths of the pulses p1 and p4 to open the other. For example, if the width of the pulse p1 is wide, the constant current sources 74a and 74a
b is connected in parallel to the charging route. As a result, the charging current for the capacitor 42 becomes a large current value determined by the internal resistance of the constant current sources 74a to 74c and the resistance 41. That is, assuming that the resistance value of the internal resistance of each of the constant current sources 74a to 74c is r and the resistance value of the resistor 41 in the LPF 40 is R, the resistance value of the capacitor 42 and the power supply potential Vdd becomes (r / 3 + R). The capacitor 42 can be charged by the current. Conversely, if the width of the pulse p1 is narrow, the constant current sources 74a and 74b are not connected to the charging route, the resistance of the capacitor 42 and the power supply potential Vdd becomes (r + R), and the capacitor 42 is charged with a small current. It is. The same applies to the case where the capacity 42 is discharged. That is, it is possible to configure a PLL that can shorten the lock time when the phase difference φ is large as in the initial stage of control, and does not cause an increase in jitter even when the control is advanced and the phase difference φ is small.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (A) In the above embodiment, the circuit for converting the width of the pulse p1 by inputting the signal Su is the pulse width conversion circuit 27a, 2
7b, and two circuits for converting the width of the pulse p4 by inputting the signal Sd are respectively composed of two pulse width conversion circuits 28a and 28b, but these are not limited to two and may be further increased. it can. (B) In the second embodiment, the constant current sources 64a to 64c and 65a to 65c are connected in series separately for the charging route and the discharging route.
By devising the above, a configuration in which these are shared may be adopted. (C) In the third embodiment, constant current sources 74a to 74c are arranged between the PMOS 71 and the power supply potential Vdd.
Constant current sources 75a to 75 are provided between the MOS 73 and the ground.
c, which are connected to each PMOS 71, N
A configuration may be employed in which the connection is made between the MOS 73 and the output terminal 76, respectively. (D) Each constant current source 24 for setting the amount of charge / discharge current
a to 24c, 25a to 25c, 64a to 64c, 65a
65b, 74a to 74c, and 75a to 75c can obtain the same effects as those of the above embodiment even if they are replaced by resistors. (E) The connection points of the switches in the switch circuits 30, 31, 80, and 81 are not limited to those shown in FIGS. 1, 8, and 9 as long as the amount of charge / discharge current can be changed.

[0035]

As described above in detail, according to the first aspect, the switching element for connecting the power supply and the output terminal during the period in which the input pulse is given, and the current path of the charge / discharge current are formed. A plurality of current control means for setting the current value, a pulse width conversion circuit for generating and outputting a pulse having a width different from the input pulse during a given period, and an output from the pulse width conversion circuit A switch for turning on or off in response to a pulse and selecting a plurality of current control means to change a current path between a power supply and an output terminal is provided in the charge pump, so that a charge / discharge current for a target circuit is input. It can be changed according to the pulse width. Therefore, for example, when the phase difference between the reference signal and the feedback signal in the PLL is large, the phase control is performed by increasing the charge / discharge current, and when the phase difference is small, the phase control is performed by reducing the charge / discharge current. Can be. Therefore, a PLL with a short lock time and with suppressed jitter can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a PLL showing a first embodiment of the present invention. .

FIG. 2 is a circuit diagram of a PLL explaining a conventional problem.

FIG. 3 is a pulse width conversion circuit 27a, 27b, 2 shown in FIG.
It is a circuit diagram which shows the structure of 8a, 28b.

FIG. 4 is a time chart (part 1) illustrating the operation of FIG. 1;

FIG. 5 is a waveform chart for explaining the operation (1) of FIG.

FIG. 6 is a time chart (part 2) illustrating the operation of FIG. 1;

FIG. 7 is a waveform diagram illustrating the operation (part 2) of FIG.

FIG. 8 is a circuit diagram of a PLL showing a second embodiment of the present invention.

FIG. 9 is a circuit diagram of a PLL showing a third embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 phase comparator 20, 60, 70 charge pump 21, 23, 61, 63, 71, 73 switching element 24a to 24c, 25a to 25c, 64a to 64c, 6
5a to 65c, 74a to 74c, 75a to 75c
Constant current sources 27a, 27b, 28a, 28b Pulse width conversion circuits 30, 31, 80, 81 Switch circuits 30a, 30b, 31a, 31b, 80a, 80b, 8
1a, 81b switch 40 LPF 50 VCO CK1 reference clock CK2 feedback clock p1 to p6 pulse

Claims (16)

[Claims] A switching element provided between a power supply and an output terminal, the switching element connecting the power supply and the output terminal during a period in which an input pulse is supplied; and a switching element connected in series between the power supply and the output terminal. Alternatively, a plurality of current control means connected in parallel to form a current path, and a pulse width conversion circuit that generates and outputs a pulse having a width different from the input pulse during a period in which the input pulse is given; A charge pump, comprising: a switch that is turned on or off in response to a pulse output from the pulse width conversion circuit and changes a current path between the power supply and an output terminal. 2. The method according to claim 1, wherein the switch is configured to change a current path between the power supply and an output terminal by selectively short-circuiting or opening the plurality of current control means when the switch is on or off. The charge pump according to claim 1, wherein A switching element connected between the output terminal and the first node, the switching element being in a conductive state during a period in which an input pulse is given; a switching element connected between the first node and a power supply; A plurality of current limiting means forming a current path; a pulse width conversion circuit for generating and outputting a pulse having a width different from the input pulse during a period in which the input pulse is supplied; and an output of the pulse width conversion circuit. And a switch for turning on or off in response to a pulse to change a current path between the first node and a power supply. 4. The charge pump according to claim 3, wherein said plurality of current control means are connected in series between said first node and said power supply. 5. The charge pump according to claim 3, wherein said plurality of current control means are connected in parallel between said first node and said power supply. 6. A plurality of current limiting means connected between an output terminal and a first node to form a current path, and connected between the first node and a power supply to receive an input pulse. A switching element that is in a conductive state during a period of time, a pulse width conversion circuit that generates and outputs a pulse having a width different from that of the input pulse during a period in which the input pulse is supplied, and an output of the pulse width conversion circuit. And a switch for turning on or off in response to a pulse to change a current path between the first node and an output terminal. 7. The charge pump according to claim 6, wherein said plurality of current control means are connected in series between said first node and said output terminal. 8. The charge pump according to claim 6, wherein said plurality of current control means are connected in parallel between said first node and said output terminal. 9. A phase comparator that compares a phase of a reference signal with a phase of a feedback signal and outputs a pulse signal according to the phase difference, and a charging / discharging current according to the pulse signal output from the phase comparator. A charge pump that inputs and outputs a voltage, a capacitor that is charged / discharged by the charge / discharge current and sets a voltage of an output node, and outputs a voltage corresponding to the phase difference from the output node; An oscillator that oscillates at a frequency corresponding to the output voltage of the setter and outputs the feedback signal, wherein the charge pump is provided when the phase difference exceeds a first value set in advance. Inputs and outputs the charge / discharge current at a first current value, and when the phase difference exceeds a second value larger than the first value, a second current larger than the first current value The charge / discharge current is input / output at the current value of Phase locked loop circuit is characterized in that the configuration of. 10. A phase comparator that compares a phase of a reference signal with a phase of a feedback signal and outputs a pulse signal according to the phase difference, and a charge / discharge current according to the pulse signal output from the phase comparator. A charge pump that inputs and outputs a voltage, a capacitor that is charged / discharged by the charge / discharge current and sets a voltage of an output node, and outputs a voltage corresponding to the phase difference from the output node; An oscillator that oscillates at a frequency according to the output voltage of the setting device and outputs the feedback signal, wherein the charge pump is provided between a power supply and an output terminal connected to the voltage setting device. A switching element for connecting the power supply and the output terminal during a period in which a pulse signal output by the phase comparator is provided; and a switching element connected in series between the power supply and the output terminal. A plurality of current control means connected in parallel to form a current path; and a pulse for generating and outputting a pulse having a width different from the pulse signal during a period in which the pulse signal output from the phase comparator is given. A phase synchronization circuit, comprising: a width conversion circuit; and a switch that is turned on or off in response to a pulse output from the pulse width conversion circuit and changes a current path between the power supply and an output terminal. 11. A phase comparator that compares a phase of a reference signal with a phase of a feedback signal and outputs a pulse signal according to the phase difference, and a charging / discharging current according to the pulse signal output from the phase comparator. A charge pump that inputs and outputs a voltage, a capacitor that is charged / discharged by the charge / discharge current and sets a voltage of an output node, and outputs a voltage corresponding to the phase difference from the output node; An oscillator that oscillates at a frequency according to an output voltage of the setting device and outputs the feedback signal, wherein the charge pump comprises: an output terminal connected to the voltage setting device; a first node; A switching element that is connected between the first node and a power supply, and that is turned on during a period in which the pulse signal output from the phase comparator is supplied. A plurality of current limiting means to be formed; a pulse width conversion circuit for generating and outputting a pulse having a width different from the pulse signal during a period in which the pulse signal output from the phase comparator is provided; And a switch for turning on or off in response to a pulse output from the circuit to change a current path between the first node and a power supply. 12. The first current control unit according to claim 1, wherein
12. The phase-locked loop according to claim 11, wherein the node is connected in series between the power supply node and the power supply. 13. The method according to claim 13, wherein the plurality of current control means includes:
12. The phase-locked loop according to claim 11, wherein the node is connected in parallel between the power supply node and the power supply. 14. A phase comparator for comparing a phase of a reference signal with a phase of a feedback signal and outputting a pulse signal corresponding to the phase difference, and a charge / discharge current corresponding to the pulse signal output from the phase comparator. A charge pump that inputs and outputs a voltage, a capacitor that is charged / discharged by the charge / discharge current and sets a voltage of an output node, and outputs a voltage corresponding to the phase difference from the output node; An oscillator that oscillates at a frequency according to an output voltage of the setting device and outputs the feedback signal, wherein the charge pump comprises: an output terminal connected to the voltage setting device; a first node; And a plurality of current limiting means connected between the first node and a power supply, and turned on during a period in which a pulse signal output from the phase comparator is supplied. A switching element to be in a state, a pulse width conversion circuit that generates and outputs a pulse having a width different from the pulse signal during a period in which the pulse signal output by the phase comparator is provided, A phase synchronization circuit comprising: a switch that is turned on or off in response to an output pulse and changes a current path between the first node and an output terminal. 15. The method according to claim 15, wherein the plurality of current control units include the first current control unit.
15. The phase-locked loop according to claim 14, wherein the phase-locked loop is connected in series between the first node and the output terminal. 16. The method according to claim 16, wherein the plurality of current control units include the first current control unit.
15. The phase-locked loop according to claim 14, wherein the node is connected in parallel with the output terminal.