JPH1065081A - Lead frame and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor package by preventing the disconnection failure of a lead due to environmental stress. SOLUTION: A semiconductor package includes a semiconductor chip 15 where a plurality of electrode pads 16 are formed at the peripheral edge of a chip surface, a wiring film 7 that is arranged and fixed at the surface side of the semiconductor chip 15 and at the same time where an insulation film 6 is laminated on a lead pattern 5, a plurality of leads 9 that are extended from the wiring film 7, at the same time where the extended edge is connected to the electrode pad 16 of the semiconductor chip 15 by a specific bending forming and its bending position L is arranged inside the lamination region of the insulation film 6, and a sealing resin 17 where the peripheral region of the semiconductor chip 15 including the boundary part between each lead 9 and the insulation film 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor package provided with a wiring film formed by laminating an insulating film on a lead pattern.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional semiconductor package which can be mounted on a printed wiring board or the like via an organic substrate having external connection terminals such as solder balls. In FIG. 4, a semiconductor chip 51 is mounted on the surface of a multi-layer organic wiring substrate 50 of about 2 to 6 layers using an organic material. The electrode pads of the semiconductor chip 51 and the wiring film 52 formed on the surface of the multilayer organic wiring substrate 50 are connected by wire bonding using gold wires 53 or the like.

A solder ball (external connection terminal) 55 that is electrically connected to the wiring film 52 on the front surface through a through hole 54 is provided on the back surface of the multilayer organic wiring board 50. It faces outside from the opening of the solder resist film 56. The semiconductor chip 51 is sealed together with the gold wire 53 by a sealing resin 57.

[0004] In the semiconductor package 58 having the above structure, the solder balls 55 formed on the back surface are connected to the printed wiring board 59. Further, the multilayer organic wiring board 50 is often called a ball grid array (BGA) because a large number of solder balls 55 are arranged in a grid pattern. It is called a BGA package.

[0005]

However, in the above-mentioned conventional semiconductor package 58, since the electrode pads of the semiconductor chip 51 and the wiring film 52 of the multilayer organic wiring substrate 50 are connected by wire bonding, the wiring pitch is reduced. There was a limit to reducing the size of Also, in other semiconductor packages called, for example, TCP (tape carrier package), since leads are formed by etching a copper foil attached on an insulating film base, lead thinning by side etching or the like is performed. Therefore, there is a limit in increasing the number of pins.

Therefore, the present applicant has already proposed a semiconductor package having a super multi-pin structure by joining a novel lead frame and a semiconductor chip, and the manufacturing procedure thereof will be briefly described below. First, in manufacturing a lead frame, as shown in FIG. 5A, a metal base 1 having a three-layer structure is prepared. The metal base 1 is obtained by forming an auminium film 3 on a surface of a substrate (hereinafter, referred to as a copper substrate) 2 made of copper or a copper alloy, and forming a nickel film 4 thereon. Next, as shown in FIG.
Lead pattern 5 by electrolytic copper plating on the surface of
To form Next, as shown in FIG. 5C, a slit S for defining the outer shape of each chip of the lead frame is formed. Next, as shown in FIG. 5D, an insulating film 6 is laminated on the lead pattern 5, thereby forming a wiring film 7 composed of the lead pattern 5 and the insulating film 6, and a large number of wiring films are formed on the film. The holes 8 are formed in a lattice. At this time, from the wiring film 7,
A plurality of leads 9 corresponding to each lead pattern 5 are in an extended form.

Next, as shown in FIG. 5E, an external connection terminal 10 made of a solder ball is formed at the end of the lead pattern 5 covered with the insulating film 6 (immediately above the hole 8). Next, as shown in FIGS. 5F to 5G, the copper substrate 2, the aluminum film 3, and the nickel film 4 of the metal base 1 are sequentially removed by selective etching so as to leave the outer ring 11. Thus, each lead pattern 5 (including the lead 9) is separated and made independent.
Next, as shown in FIG. 5H, bumps 12 are formed on the tips of the leads 9 extending from the wiring film 7.
As described above, the lead frame 1 before the semiconductor chip is mounted
3 is completed.

[0008] Thereafter, when assembling the semiconductor chip to the lead frame 13, as shown in FIG. 6 (a), the semiconductor chip 15 is positioned and fixed to the back surface of the wiring film 7 via an adhesive layer 14. Next, as shown in FIG. 6B, the tips of the leads 9 are connected to the electrode pads 16 of the semiconductor chip 15 via the bumps 12. Next, as shown in FIG. 6C, a sealing resin 17 is injected into a peripheral region of the semiconductor chip 15, and the sealing resin 17 is cured to integrate the components. Finally, as shown in FIG. 6D, unnecessary portions are cut off at the outer edge of the outer ring 11 to complete the semiconductor package 18 having a super multi-pin structure. In the semiconductor package 18, since the lead pattern 5 is formed on the metal base 1 by electrolytic copper plating at the stage of manufacturing the lead frame 13, a multi-pin structure exceeding the limit up to that point is realized.

However, in realizing such an ultra-high pin count, the strength of the lead 9 itself is inevitably weakened. Therefore, when a temperature cycle test or the like is performed, as shown in FIG. In some cases, stress is applied to the bent position L of the lead 9 and the lead 9 is disconnected there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to prevent lead disconnection failure due to environmental stress and improve the reliability of a semiconductor package.

[0011]

In a lead frame according to the present invention, a plurality of leads extending from a wiring film are connected to an electrode pad of a semiconductor chip by a bending area of an insulating film relative to a lead bending position. The structure is extended to the lead extension end side from the lead bending position.

In the lead frame having the above structure, when connecting the plurality of leads extending from the wiring film to the electrode pads of the semiconductor chip, a part of the insulating film is bent together with each of the leads. Bend positions are reinforced with an insulating film.

In the semiconductor package according to the present invention, a semiconductor chip having a plurality of electrode pads formed on a peripheral portion of the chip surface, an insulating film fixed on the surface side of the semiconductor chip, and an insulating film formed on a lead pattern. A wiring film formed by laminating, extending from the wiring film, the extending end is connected to the electrode pad of the semiconductor chip by predetermined bending, and the bending position is arranged inside the lamination region of the insulating film; And a sealing resin for sealing a peripheral region of the semiconductor chip including a boundary portion between the leads and the insulating film.

In the semiconductor package having the above configuration,
The bending positions of the multiple leads extending from the wiring film are reinforced by the insulating film, and the reinforced portions are embedded in the sealing resin integrally with the leads. Even if it is applied to the bending position of the lead, disconnection of the lead is prevented by the reinforcing effect of the insulating film.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a lead frame and a semiconductor package according to the present invention will be described below in detail with reference to the drawings along with the manufacturing procedure. First, in manufacturing a lead frame, as shown in FIG. 1A, a metal base 1 made of a laminated plate having a three-layer structure is prepared. This metal base 1 is formed by forming an aluminum film 3 having a thickness of about 4.5 μm on a surface of a substrate (hereinafter, referred to as a copper substrate) 2 made of copper or a copper alloy having a thickness of about 150 μm, for example, by vapor deposition. A nickel film 4 having a thickness of about 1 to 2 μm is formed.

Of these, the copper substrate 2 does not itself become a lead, but is ultimately cut away except for an outer ring portion (described later). However, in forming a very fine lead pattern, Indispensable. The aluminum film 3 corresponds to an etching stop film for preventing the surface side of the metal base 1 from being etched when the copper substrate 2 is etched in a subsequent step. The nickel film 4 corresponds to a base of electrolytic plating for forming a lead pattern on the surface of the metal base 1, that is, a plating base film.

As the metal base 1, a chromium film having a thickness of, for example, about 0.5 μm is formed as an adhesion film between the aluminum film 3 and the nickel film 4 in order to enhance the adhesion between them. Is also good. Further, a thin copper film may be formed instead of the nickel film 4 as the plating base film.

Next, as shown in FIG. 1B, a plurality of lead patterns 5 made of copper are formed on the surface of the metal base 1, ie, the surface of the nickel film 4 by a selective plating method. The selective plating here is performed by selectively covering the surface of the metal base 1 with a resist pattern and performing electrolytic copper plating using the resist pattern as a mask. Thereby, the lead pattern 5 having a good film quality and a fine pattern can be obtained.

Next, as shown in FIG. 1C, the metal base 1 is selectively etched from both sides,
A slit S for defining the outer shape of each chip of the lead frame and a hole (not shown) for facilitating manufacture are formed. Next, as shown in FIG. 1D, an insulating film 6 is laminated on the lead pattern 5 formed by selective plating, whereby a wiring film 7 including the lead pattern 5 and the insulating film 6 is formed. Insulating film 6
Is made of, for example, a photosensitive resin such as an epoxy-based, polyimide-based, or polyolefin-based resin, or a polyimide film. By selectively etching this, a large number of holes 8 are formed in a lattice pattern on the film.

Here, a plurality of leads 9 extend from the wiring film 7 in a form in which the previously formed lead pattern 5 is extended. These leads 9 have their extended ends, that is, the tips of the leads serving as connecting portions to the electrode pads of the semiconductor chip. In connecting the leads 9, each lead 9 is bent at a predetermined position L as a boundary. It is supposed to be. Therefore, in the present embodiment, when laminating the insulating film 6, the film laminating region is extended to the lead extending end side (lead end side) from the above-described lead bending position L, thereby forming a lead described later. At the time of bending, a part of the insulating film 6 was also bent together with each lead 9. Incidentally, the size of the protrusion of the insulating film 6 from the lead bending position L may be set as large as possible within a range that does not hinder the lead bending to be described later.

Subsequently, as shown in FIG. 1 (e), at the end of the lead pattern 5 covered with the insulating film 6 (directly above the hole 8), the insulating film 6 is used as a mask to form an external device made of, for example, a solder ball. The connection terminal 10 is formed. The external connection terminal 10 is formed by forming a base film made of a metal material such as copper, nickel, or gold by, for example, electrolytic plating at the end of the lead pattern 5 exposed on the insulating film 6, and then forming the base film. It is obtained by laminating a tin-lead alloy solder material thereon by electrolytic plating, and reflowing the solder material to form a ball shape.

Subsequently, as shown in FIG. 1F, the copper substrate 2 of the metal base 1 is removed by selective etching so that the outer ring 11 is left. In this etching, the aluminum film 3 acts as an etching stopper, and only the copper substrate 2 is removed. Next, FIG.
As shown in (1), the aluminum film 3 of the metal base 1 is removed by selective etching, and the nickel film 4 is further removed by selective etching to separate and separate the lead patterns 5 (including the leads 9). 1G, the wiring film 7 and the outer ring 11 are represented as being separated from each other, but actually, they are integrally formed by hanging leads (not shown) formed simultaneously with the lead pattern 5. Are linked. Then, as shown in FIG. 1 (h), a bump 12 made of aluminum is formed on the tip of each lead 9 extending from the wiring film 7 by, for example, a sputtering method or a vapor deposition method. Thus, the lead frame 13 before the mounting of the semiconductor chip is completed.

Thereafter, when assembling the semiconductor chip to the lead frame 13, as shown in FIG. 2A, the semiconductor chip 15 is positioned and fixed to the back surface of the wiring film 7 via the adhesive layer 14. At this time, the tips (bumps 12) of the leads 9 extending from the insulating film 6
Are in a state of facing the electrode pads 16 on the semiconductor chip 15.

Next, as shown in FIG. 2B, the tips of the leads 9 are connected to the semiconductor chip 15 via the bumps 12.
By single point bonding. In this single point bonding, each lead 9 is moved by a wedge tool (not shown).
It is bent at the above-described lead bending position L and pressed against the electrode pad 16. At this time, lead frame 1
Due to the structure of No. 3, the laminated region of the insulating film 6 is extended to the lead tip side (lead extending end side) from the lead bending position L, whereby the lead bending position L is arranged inside the film laminated region. Therefore, when bending the leads 9 by single point bonding, a part of the insulating film 6 is bent together with each lead 9.

Next, as shown in FIG. 2C, a sealing resin 17 such as an epoxy resin or a silicone resin is applied to a peripheral region of the semiconductor chip 15 including a boundary portion between each lead 9 and the insulating film 6. Each component is integrated by injecting by potting and curing it. Finally, as shown in FIG. 2D, unnecessary portions are cut off at the outer edge of the outer ring 11 to complete the semiconductor package 18 having a super multi-pin structure.

In the semiconductor package 18 thus obtained, as shown in FIG. 3, the bending position L of each lead 9 is reinforced by the insulating film 6, and the reinforced portion is integrally sealed with the lead 9. The shape is embedded in the resin 17. Accordingly, the strength of the lead 9 at the bending position L is sufficiently ensured. Therefore, even when an environmental stress due to a temperature cycle or the like is applied to the bending position L of the lead 9, the effect of reinforcing the insulating film 6 of the lead 9. Disconnection can be prevented.

As a further preferred embodiment, a resin material having good adhesion to the insulating film 6 is provided on the side opposite to the insulating film 6.
For example, a resin film (not shown) made of, for example, polyimide is formed (backed), and the lead pattern 5 (including the base of the lead 9) is sandwiched between the resin film and the insulating film 6. In addition, the reinforcing effect at the base of the lead is further enhanced, and the separation of the lead 9 from the insulating film 6 can be reliably prevented even when the lead 9 is bent.

In the above embodiment, the lead pattern 5 is formed on the metal base 1 by electrolytic copper plating, and the insulating film 6 is laminated on the lead pattern 5 as an example. Although described above, the present invention is not limited to this, and can be similarly applied to a film base formed by etching a film base such as polyimide.

[0029]

As described above, according to the lead frame of the present invention, when connecting a plurality of leads extending from the wiring film to the electrode pads of the semiconductor chip,
A part of the insulating film is also bent together with each lead. Thereby, since the bending position of each lead is reinforced by the insulating film, the strength of the lead can be increased.

According to the semiconductor package of the present invention, the bending positions of the plurality of leads extending from the wiring film are reinforced by the insulating film, and the reinforced portions are embedded in the sealing resin integrally with the leads. It will be in a state where it was lost. As a result, the strength at the lead bending position is sufficiently ensured, so that disconnection of the lead due to environmental stress can be reliably prevented. As a result, the reliability of the semiconductor package against environmental stress is significantly improved.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram for explaining a lead frame according to the present invention.

FIG. 2 is a manufacturing process diagram for explaining a semiconductor package according to the present invention.

FIG. 3 is a partially enlarged view of a semiconductor package according to the present invention.

FIG. 4 is a cross-sectional view of a conventional BGA package.

FIG. 5 is a manufacturing process diagram of a lead frame for a super multi-pin structure.

FIG. 6 is a manufacturing process diagram of a semiconductor package for a super multi-pin structure.

FIG. 7 is a partially enlarged view of a semiconductor package having a super multi-pin structure.

[Explanation of symbols]

Reference Signs List 5 lead pattern 6 insulating film 7 wiring film 9 lead 13 lead frame 15 semiconductor chip 16 electrode pad 17 sealing resin L lead bending position

Claims (2)

[Claims] 1. A semiconductor device comprising: a wiring film formed by laminating an insulating film on a lead pattern; and a plurality of leads extending from the wiring film and having extended ends serving as connecting portions to electrode pads of a semiconductor chip. A lead frame, wherein a lamination region of the insulating film is extended to a lead extending end side from the lead bending position with respect to a lead bending position when connecting the plurality of leads to the electrode pads of the semiconductor chip. A lead frame, comprising: a lead frame; 2. A semiconductor chip having a plurality of electrode pads formed on a peripheral portion of a chip surface, wherein the semiconductor chip is arranged and fixed on the surface side of the semiconductor chip.
A wiring film formed by laminating an insulating film on a lead pattern, and extending from the wiring film, the extended end of which is connected to the electrode pad of the semiconductor chip by predetermined bending and the bending position is A plurality of leads arranged inside the laminated region of the insulating film; and a sealing resin for sealing a peripheral region of the semiconductor chip including a boundary portion between the plurality of leads and the insulating film. A semiconductor package characterized by the above-mentioned.