JPH1062492A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve an AC performance test that requires neither expensive LSI testing machines nor measures against noise required for executing a high- frequency test. SOLUTION: An output signal 111 of a selector 105 is distributed to a test information generation part 201, a test result judgment part 204, and a logic circuit 203 that is a circuit to be tested as an operation clock when performing a self-diagnosis test of the logic circuit 203 that is a circuit to be tested. Further, the output signal 111 of the selector 105 is inputted to a frequency-divider 107, and the frequency-divider 107 outputs a signal 131 obtained by dividing the clock signal to an output terminal Fo . Output signals 141, 151, 161, and 171 of a clock generator 106 and a selector control signal 121 inputted from an input terminal Sc are inputted to the selector 105 and either output signal 141, 151, 161, or 171 is selected and outputted to the output signal 111 according to the setting from the outside of a semiconductor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having a built-in self-diagnosis circuit.

[0002]

2. Description of the Related Art In accordance with recent miniaturization and high integration of semiconductor manufacturing technology, an external terminal of a semiconductor integrated circuit has been changed from an external terminal to an internal circuit.
The number of logic stages up to a functional unit such as an AM has increased dramatically. Therefore, it is difficult to create a test pattern having a sufficient failure detection rate by a test method in which a test pattern is input from an external terminal. In addition, when testing many functional units, multiple functional unit tests may be executed in parallel to reduce the test time.However, due to the physical limitation of the number of external terminals, the parallelism can be improved. There is a limit. Further, a wiring area for distributing a test signal from each functional unit to an external terminal also contributes to a reduction in the degree of freedom of the layout of the integrated circuit. For the reasons described above, a method of incorporating a built-in self-diagnosis circuit in a semiconductor integrated circuit is often adopted as a method of facilitating test of the semiconductor integrated circuit.

FIG. 4 shows an example of a semiconductor integrated circuit having a built-in self-diagnosis circuit. FIG.
1 is an example of a semiconductor integrated circuit having a built-in self-diagnosis circuit proposed in Japanese Patent Application Laid-Open Publication No. HEI 10-163, 1988. Hereinafter, a method of testing the logic circuit 203 as the circuit under test will be briefly described with reference to FIG.

[0004] An input signal 21i (i = 0 to n) and a test pattern output signal 22i of the test information generation unit 201 are input to a test switching unit 202, respectively. The output signal 23i of the test switching unit 201 is input to the logic circuit 203. Logic circuit 20
The third output signal 24i becomes the output of the terminal To and is input to the test result determination unit 204. Test start instruction input S
t is input to the test information generation unit 201, the test switching unit 202, and the test result determination unit 204. The output Tt of the test result determination section 204 is output from a test output terminal. When the test start instruction input St is not valid, the test switching unit 202 outputs the terminal input signal 21i as the output signal 23i of the test switching unit 202, and the LSI performs a normal operation. When the test start instruction input St becomes valid, the test information generation unit 201
Outputs a test pattern signal 22i from the test switching unit 2
02 outputs the input signal 22i as 23i, and the test result determination section 204 determines whether the input signal 24i is good or not, and outputs it to the test output terminal Tt. The operation clock is input from a clock input terminal CLK, and supplies a clock to the test information generation unit 201, the logic circuit under test 203, and the test result determination unit 204.

As described above, in FIG. 4, the logic circuit 203 is tested by the self-diagnosis circuit built in the LSI.

In Japanese Patent Application Laid-Open No. Hei 5-241882, a test vector is generated using a linear feedback shift register (LFSR), and the output of a circuit under test is taken into the LFSR to generate a test signature. There has been proposed a method of compressing a circuit output result and using the test signature as a test vector. This allows
In addition to simplifying the creation of test vectors, the determination of test results is also simplified.

Further, in Japanese Patent Application Laid-Open No. 4-208880, a function for judging pass / fail of test results is incorporated in the semiconductor integrated circuit, thereby simplifying pass / fail judgment and reducing the number of test terminals.

[0008]

In the above-described prior art built-in self-diagnosis circuit, the operation clocks of the circuit under test and the self-diagnosis circuit are supplied from outside. In general, an LSI tester is used for testing.
An operation clock is supplied from the tester. Therefore, when performing not only a simple functional test but also an AC performance test, speed selection, rank classification, etc., it is necessary to set the frequency of the clock supplied from the LSI tester to the integrated circuit under test to a desired value. There is.

On the other hand, with the recent increase in the speed of semiconductor integrated circuits, there is an increasing demand for speed tests in a high frequency region, and further, a rank classification of AC performance is required as in general-purpose memory products. Products are also on the rise.

However, generally, high frequency, high precision LS
The I tester is more expensive than a low-frequency, low-accuracy LSI tester because of the large number of design steps and the use of expensive components. Also, compared to the test in the low frequency range, the test in the high frequency range requires sufficient noise countermeasures such as adding a bypass capacitor and shielding the signal line. It is necessary to pay attention to the setting of.

As described above, a semiconductor integrated circuit that requires a test in a high frequency range has a problem that the cost required for the test including the cost of an LSI tester is increased.

Further, in a method of supplying an operation clock from the outside as in the prior art, a clock distributed to not only the circuit under test but also the entire semiconductor integrated circuit is generally used in many cases. However, in that case, there is a problem that a logic circuit other than the circuit under test also operates, which causes an increase in power consumption and noise amount during the test.

In the conventional method, when a plurality of functional units are tested at the same time, even if the AC performance originally required for each functional unit is different, the test conforms to the strictest required performance. For other functional units, it becomes an over spet, which increases the cost of non-defective products.

In addition to the three conventional examples described above, there are examples of a semiconductor integrated circuit in which a clock generator is built in the semiconductor integrated circuit. However, none of them is intended for an AC performance test. Alternatively, it is very difficult to perform a test at a desired frequency due to a manufacturing variation peculiar to a semiconductor integrated circuit.

[0015]

According to the present invention, in a semiconductor integrated circuit having a built-in self-diagnosis circuit, a plurality of clock generators for generating clock signals of different frequencies, A self-diagnosis test for a logic circuit, which is a circuit under test, including a selector for selecting one of the outputs and a frequency dividing circuit for dividing and outputting the clock signal selected by the selector; A semiconductor integrated circuit characterized in that the semiconductor integrated circuit is used as an operation clock when performing the operation.

According to the present invention, in a semiconductor integrated circuit having a built-in self-diagnosis circuit, a clock generator;
A frequency dividing circuit for dividing and outputting a clock signal output from the clock generator, wherein an operation power supply of the clock generator is separated from other circuit parts, and the clock signal is transmitted to a circuit under test by a circuit under test. A semiconductor integrated circuit characterized in that it is used as an operation clock when performing a self-diagnosis test of a certain logic circuit is obtained.

[0017]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. FIG. 1 shows an example of a semiconductor integrated circuit having a self-diagnosis circuit for performing an AC performance test on a logic circuit 203 as a circuit under test and performing a ranking of low-speed products and high-speed products.

In FIG. 1, a test method of a logic circuit 203 which is a circuit under test uses a selector 10 as an operation clock.
5 is the same as the example of FIG. 4 described in the section of the prior art except that the output signal 111 of FIG. The following mainly describes differences from the above-described conventional technology.

In FIG. 1, as an operation clock for performing a self-diagnosis test of a logic circuit 203 as a circuit under test,
The output signal 111 of the selector 105 is supplied to the test information generator 2
01 and the test result determination unit 204 and the logic circuit 203 which is the circuit under test. Further, the selector 105
Is an input signal of the frequency divider 107,
The frequency divider 107 converts the frequency of the clock signal into a signal 131,
Output to the output terminal Fo. Also, the clock generator 106
Output signals 141, 151, 16 of (A, B, C, D)
1, 171 and the selector control signal 121 input from the input terminal Sc are input signals of the selector 105, and 141, 151,
One of 161 and 171 is selected and output to 111. The clock generator 106 receives a control signal 181 from the input terminal Fc so as to stop the operation except during the test. This enables a self-diagnosis test without supplying an operation clock from an external device (usually an LSI tester).

The clock signals 141, 151, 161, and 171 generated inside the semiconductor integrated circuit are affected by manufacturing variations, and the generated frequency values also show variations. Therefore, in FIG. 1, it is possible to correct the test speed by observing the clock signal frequency value of the actual device through the Fo terminal, and to easily perform appropriate ranking into low-speed products and high-speed products. Become. As described in the section of the prior art, in order to observe a high-frequency signal, it is necessary to consider noise countermeasures and the like. Is converted to a frequency signal.

Next, referring to FIG. 2, a brief description will be given of the correction of the test speed and the ranking according to the manufacturing variation.
First, with regard to the criteria for ranking, in the semiconductor integrated circuit of FIG. 1, when the logic circuit 203, which is the circuit under test, operates at a frequency of 200 MHz or more, a high-speed product is used.
If it operates only at less than 200 MHz, it is defined as a low-speed product.

In FIGS. 1 and 2, the designed center values of the frequencies of the clock signals generated by the internal clock generation circuits A, B, C, and D of the semiconductor integrated circuit are 50 MHz, respectively.
z, 100 MHz, 200 MHz, and 400 MHz.

However, due to variations in semiconductor manufacturing,
Variations occur between the frequencies of the clock signals in the actual device. Referring to an example of a general CMOS type semiconductor integrated circuit or the like, here, it is assumed that the variation is about 0.5 to 2 times the central value of the design.

Taking the case of the clock generator A as an example, the output clock signal of the clock generator A has a design center value of 50.
MHz, the worst value with the slowest speed is 2
A value of about 5 MHz is shown, and a value of about 100 MHz is shown as the best value with the highest speed.

Hereinafter, the same applies to the clock generators B, C and D. Therefore, when the test is executed in a state where the output clock signal 171 of the clock generator D is selected by the setting of the selector 105, the test is performed at a high frequency of 200 MHz or more even in the worst case. It can be said. Therefore, if the test result in a state where D is selected is good, the device is ranked as a high-speed product.

Conversely, when A is selected, even if the best case is considered, only the test at 100 MHz passes, and the test result is good only when A is selected. If the test result is negative if this clock generator is selected, then the device is ranked as slow.

In cases other than the case described above, the type of the clock generator selected at the time of the test, the result of pass / fail, and the frequency division output are back calculated based on the frequency division ratio. From the clock frequency information on the device,
High-speed products and low-speed products are ranked.

Next, a second embodiment of the present invention will be described. FIG. 3 shows a second embodiment of the present invention. The frequency variation of the clock signal caused by the manufacturing variation
Only the clock generator 106 is corrected by adjusting the voltage applied to the power supply terminal Vc that supplies the power supply voltage.
The power supply voltage supplied from the power supply terminal Vc is supplied only to the clock generator 106, and the power supply line is separated from other circuit parts.

In one semiconductor integrated circuit, FIG.
Alternatively, by preparing a self-diagnosis circuit capable of performing an AC performance test as shown in FIG. 3 for each functional unit, a test is performed at a clock frequency required for each functional unit, and a test target other than the test target is executed. The operation of the unit can be easily stopped to reduce power consumption and noise.

The AC performance test and ranking in the above-described embodiment do not require an expensive LSI tester which requires high frequency and high precision, and a low frequency and low precision inexpensive LSI test. It can be easily implemented with a machine or a frequency counter and a simple test jig.

[0031]

As described above, according to the present invention, an inexpensive low-frequency, low-accuracy LSI tester or high-frequency With a counter and a simple test jig, an AC performance test and ranking can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating AC performance ranking according to the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 105 selector 107 frequency divider 201 test information generation unit 202 test switching unit 203 logic circuit 204 test result determination unit

Claims (3)

[Claims] 1. A semiconductor integrated circuit having a built-in self-diagnosis circuit, comprising: a plurality of clock generators for generating clock signals of different frequencies; a selector for selecting one of outputs from the plurality of clock generators; A frequency divider circuit for dividing and outputting the clock signal selected by the selector,
A semiconductor integrated circuit, wherein a clock signal selected by the selector is used as an operation clock when a self-diagnosis test is performed on a logic circuit to be tested. 2. A semiconductor integrated circuit having a built-in self-diagnosis circuit, comprising: a clock generator; and a frequency divider for dividing and outputting a clock signal output from the clock generator. A semiconductor integrated circuit having a configuration in which an operation power supply is separated from another circuit portion, wherein the clock signal is used as an operation clock when a self-diagnosis test is performed on a logic circuit to be tested. 3. A semiconductor integrated circuit comprising a plurality of combinations of a self-diagnosis circuit and a circuit under test having the configuration according to claim 1 or 2.