JPH11237443A - Test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit where the increase in a circuit scale is minimized. SOLUTION: On a test mode, inverted output QB of an F/F 2 is inputted to data input D of the F/F 2 to set a selection signal (b) of a selector circuit 1 to 'H', and a waveform with the I/2 frequency of a clock input waveform (c) of the F/F 2 is outputted from the F/F 2 (d). When the F/F 2 that does not operate due to a test pattern for selecting a semiconductor integrated circuit or has a low operation rate exists, the selector circuit 1 is connected to the data input D of the F/F 2 and the inverted output QB of the F/F 2 is inputted to the data input D of the F/F 2 on a test mode, thus operating the F/F 2 in a toggle for doubling the frequency and operating a group of logic circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit,
In particular, it relates to a test circuit for a digital semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a (digital) semiconductor integrated circuit, as a method of testing it, a test pattern (a signal having a special test waveform) is inputted, and an output signal corresponding thereto is analyzed to determine whether the circuit operates normally. There is a way to test. . On the other hand, creating a test pattern with a high failure detection rate requires an extremely large amount of time and effort. Furthermore, recent semiconductor integrated circuits are becoming more and more highly integrated, and it has become virtually impossible to increase the fault detection rate with a limited number of test patterns as before.

In general, a semiconductor integrated circuit has a main logic circuit group 4, a large number of data input terminals (D1 to Dm) and a large number of data output terminals (Q
1Qp) on a semiconductor chip (substrate). The data input terminals include those that include F / Fs (flip-flops) 2 and 2 ′ in the input section (D1, D2) and those that do not (F3).

Further, the data output terminal has an F /
Some include F7 (Q1) and some do not (F2). The input / output terminals not including the F / F can be sufficiently tested and evaluated by the test patterns. However, at the input / output terminal including the F / F, when the test pattern is input, the F / F may not operate depending on the test pattern, so that sufficient test and evaluation may not be performed.

Japanese Patent Application Laid-Open No. 7-180736 discloses a method in which a selector circuit is inserted on the data input side of all F / Fs in a semiconductor integrated circuit, and all the F / Fs have a shift register configuration in a test mode. Campus test method) has been proposed.

[0006]

Problems to be Solved by the Invention
In the case of the proposal described in Japanese Patent Application Laid-Open No. 6-206, there is a problem that the circuit scale increases. That is, since the selector circuits are provided on the data input sides of all the F / Fs, when the semiconductor integrated circuit has a general circuit configuration, the circuit scale increases by 20 to 30%. In addition, there is a problem that power consumption increases. That is, since the circuit scale increases, the power consumption also increases accordingly.

Further, these problems are described in JP-A-7-18
The same applies to the cross-check method or BIST (Built-In Self Test) method, which is a commonly used fault detection rate improving method, as well as the proposal described in Japanese Patent No. 0736.

[0008] With the increase in the scale of semiconductor integrated circuits, LSI
Due to the limited memory of the tester and the efficiency of LSI selection time, it is difficult to create a test pattern with a high failure detection rate with a limited test pattern length (amount). As an improvement method, a scan path test method, a cross check method, a BIST method, and the like have been implemented. If these methods are used, it is possible to improve the failure detection rate, but at the same time, there is a problem that the circuit scale and power consumption are increased.

An object of the present invention is to provide a test circuit for a semiconductor integrated circuit in which an increase in circuit size is minimized.

[0010]

According to the present invention, there is provided a test circuit for a semiconductor integrated circuit wherein an external input signal is supplied to a group of internal logic circuits via a flip-flop circuit. And a selector for selectively deriving an output of the flip-flop circuit and supplying the output to a data input of the flip-flop circuit, and controlling the selector to select an output of the flip-flop circuit in a test mode. Is obtained.

The flip-flop circuit includes a plurality of cascade-connected flip-flops, the flip-flop circuit includes a D-type flip-flop, and an output of the flip-flop circuit. Is an inverted output.

The operation of the present invention is as follows. An F / F that does not operate or has a low operation rate in the semiconductor integrated circuit selection test pattern is operated in the test mode. That is, the selector circuit is connected to the F / F data input that does not operate or has a low operation rate in the semiconductor integrated circuit selection test pattern, and performs the counter operation in the test mode. As a result, the operation rate increases, and the functional blocks having a low operation rate including the peripheral logic circuits operate, thereby improving the failure detection rate.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a test circuit according to the present invention. Referring to FIG. 1, in the input test circuit according to the present invention, a selector circuit 1 is connected to a data input side of a D type F / F2 in an input / output unit which does not operate or has a low operation rate in a semiconductor integrated circuit selection test pattern. I do. The selection signal S of the selector circuit 1 is connected to the input terminal b, one of the data input signals A is connected to the normal input terminal a, and the other data input B is F
/ F2 is connected to the inverted output QB.

Referring to FIG. 3, the input test circuit according to the second embodiment of the present invention of the test pattern for selecting a semiconductor integrated circuit does not operate with the test pattern or has a low operation rate. The selector circuit 1 is connected to the data input side of the most input side F / F 2a of the register configuration circuit. This shift register configuration circuit includes a plurality of F
/ F2a to 2n are cascaded.

The selection signal S of the selector circuit 1 is supplied to an input terminal b.
, One of the data input signals A is connected to the input terminal a as usual, and the other data input B is connected to the inverted output QB of the F / F2n on the output stage side of the shift register configuration circuit. Is done.

FIG. 5 shows a circuit example in which the test circuit according to the third embodiment of the present invention is applied to a rising edge detection circuit. The selector circuit 1 is connected to the data input of the F / F 2a at the preceding stage of the edge detection circuit, and the selection signal S of the selector circuit 1 is connected to the external terminal b. For example, the logic of the external terminal b is set to “low (L)” in the normal mode and “high (H)” in the test mode.

When the selection signal b is "L" (normal mode),
The selector circuit 1 connects the input signal a to the data input D of the F / F 2a. When the selection signal b is "H" (test mode), the selector circuit 1 outputs the (inverted) output signal Q of the F / F 2b.
B is connected to the data input D of the F / F 2a.

The operation of the embodiment of the present invention will be described with reference to FIGS. 2, 4 and 6, respectively. FIG. 2 is a waveform chart in the test mode of the first embodiment shown in FIG. In test mode,
Since the selection signal b of the selector circuit 1 is set to “H”, F /
An inverted output QB of the F / F2 is input to the data input D of the F2, forming a kind of 1/2 counter, and a waveform having a frequency of 1/2 of the clock input waveform c of the F / F2 is obtained from the F / F2. Output d.

FIG. 4 is a waveform chart in the test mode of the second embodiment shown in FIG. In the test mode, the selection signal b of the selector circuit 1 is set to “H”. Therefore, the inverted output QB of the F / F 2n is input to the data input D of the F / F 2a, and the shift register configuration circuits 2a to 2n are n. Step F / F
And a counter 1 / of the clock input waveform c.
A waveform d having a frequency of (2 × n) is output.

FIG. 6 is a waveform diagram of the rising edge circuit of the third embodiment shown in FIG. Normal mode (external terminal b
Is "L"), when a rising waveform is input to the data input D of the F / F 2a, the NAND gate 3 outputs "L".
Is output. Therefore, when the rising waveform is not input to the data input D of the F / F 2a, that is,
When a falling waveform or a “H” or “L” level waveform is input, the output d of the NAND gate 3 does not change.

In this case, the test mode is switched by setting the external terminal b to "H", and the inverted output QB of the F / F 2b is input to the data input D of the F / F 2a. As a result, a two-stage counter is constituted by the shift register constituted by the F / F 2a and the F / F 2b, and the signal obtained by dividing the frequency of the clock input signal c by 1/4 is applied to the F / F 2a and the F / F 2a.
F2b is output from NAND gate 3 and "H"
The signal "L" is output.

Next, a first modification of the first embodiment of the present invention will be described with reference to FIG. If the F / F2 does not operate with the test pattern for semiconductor integrated circuit selection or if there is an F / F2 with a low operation rate, the data input D of the F / F2
Is connected to the selector circuit 1 and the F / F
2 is input to the data input D of the F / F2, so that the F / F2 is a toggle F of 2
/ F, and the logic circuit group 4 is operated.

A second modification of the first embodiment of the present invention will be described with reference to FIG. In the case where the test pattern for semiconductor integrated circuit selection does not operate or the F / F2 with a low operation rate exists, the logic circuit group 4 is operated by the test circuit for improving the fault detection rate as shown in FIG. If the result is difficult to observe from the external terminal due to the logic of the subsequent stage, the output of the logic circuit group 4 is output from the output terminal e through the other internal signals that are difficult to observe and the compression circuit 5.

Examples of the compression circuit 5 include a P / S (parallel / serial conversion) circuit and a parity circuit as shown in FIG.

[0026]

As described above, the present invention has the effect that the fault coverage can be improved by increasing the minimum circuit scale. That is, since the selector circuit is added only to the F / Fs that do not operate with the semiconductor integrated circuit selection test pattern or that have a low operation rate, the conventional failure detection that uniformly adds the selector circuits to all the F / Fs The number of additional circuits is smaller than that of the test circuit for improving efficiency.

Further, there is an effect that an increase in power consumption by the test circuit for improving the fault detection rate is minimized. In other words, the increase in power consumption can be suppressed to a minimum since the circuit scale can be minimized as compared with the conventional test circuit for improving the failure detection rate.

This has the effect of reducing the trouble of designing test patterns for improving the failure detection rate. That is, in the test mode, a circuit with a low operation rate automatically operates at a high operation rate, so that it is not necessary to consider a logical circuit operation in test pattern design.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a waveform chart of the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a waveform chart of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a third embodiment of the present invention.

FIG. 6 is a waveform chart of a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a first modification of the first embodiment of the present invention.

FIG. 8 is a circuit diagram of a second modification of the first embodiment of the present invention.

FIG. 9 is a conceptual circuit diagram of an embodiment of the present invention.

FIG. 10 is a conceptual circuit diagram of a semiconductor integrated circuit related to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Selector circuit 2 F / F 4 Logic circuit group 5 Compression circuit

Claims (4)

[Claims] 1. A test circuit for a semiconductor integrated circuit in which an external input signal is supplied to an internal logic circuit group via a flip-flop circuit, wherein the test circuit selects between the external input signal and an output of the flip-flop circuit. A test circuit, comprising: a selector which is uniquely derived and supplied to a data input of the flip-flop circuit, and controls the selector to select an output of the flip-flop circuit in a test mode. 2. The test circuit according to claim 1, wherein the flip-flop circuit has a plurality of cascade-connected flip-flops. 3. The test circuit according to claim 1, wherein said flip-flop circuit comprises a D-type flip-flop. 4. The test circuit according to claim 1, wherein an output of said flip-flop circuit is an inverted output.