JPH1056565A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use memory whose bit width is small as a storage device without causing the deterioration of an image and to reduce costs. SOLUTION: A computing element 1 binarizes inputted image data, adds correction data which is inputted from a computing element 2 and outputs pixel data of a bit number m to a data bus 5. Data of upper n bits of all data on the bus 5 is inputted in a storage device 3, and the device 3 outputs the data of n bits at a prescribed timing to a data bus 6. A bit complementary element 4 generates complementary data of the same bit number as a bit number (m-n) and outputs the complementary data at a timing at which it follows the low order of the data which is outputted from the device 3 to the bus 6. The bus 6 deals with both data as one pixel data with the output data of the device 3 as upper bits and the output data of the element 4 as lower bits, and the pixel data is inputted in the element 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing predetermined processing on image data read by an image reading apparatus such as a scanner or image data created in a workstation.

[0002]

2. Description of the Related Art An image processing apparatus performs processing such as shading correction and gradation correction on image data output from an image reading device or a workstation. This image processing apparatus includes a storage device for temporarily storing image data input and output before and after the processing. Generally, since image data has a large capacity, a large-capacity storage device is required to execute the processing at a high speed, resulting in an increase in cost.

Therefore, in a conventional image processing apparatus, as disclosed in JP-A-3-261575 and JP-A-7-319666, first-in first-out (hereinafter, referred to as FIFO) is used as a storage device. Some use a FIFO memory that performs processing. FIFO
By using a memory, image processing can be performed at high speed regardless of the external data processing speed. As shown in FIG. 3, an image processing apparatus using a FIFO memory has a FIFO memory.
Arithmetic units 31 and 32 are connected to a storage device 33 as a memory via data buses 35 and 36.

[0004]

However, as the functions of scanners and workstations become more sophisticated, the number of gradations of image data handled by the image processing apparatus also increases, and image data temporarily stored in the storage device of the image processing apparatus is increased. The bit width also tends to increase. If image data having a large bit width is stored in the storage device as it is, the cost of the storage device increases in proportion to the bit width. Further, if the bit width of the image data is reduced by reducing the number of gradations of the image data to be input to the image processing apparatus or by simplifying the content of the calculation, the image quality is degraded.

For example, consider a case where the image processing apparatus shown in FIG. 3 converts multi-gradation image data into two-gradation image data. The image processing device performs an error diffusion process prior to the two-tone conversion. First, in the error diffusion process,
The arithmetic unit 32 compares the image data near the pixel to be processed with a threshold value and outputs error data of the image data of the pixel to be processed to the arithmetic unit 31 based on the comparison result. Arithmetic unit 31
Adds the error data to the image data of the pixel to be processed. Next, in the two-tone conversion process, the arithmetic unit 32 compares the image data, for which the error diffusion process has been completed, with a threshold value again,
It outputs image data of either “0” or “255” gradation.

More specifically, when the pixel data of the pixel to be processed is input to the arithmetic unit 31, the arithmetic unit 32 determines whether the corresponding pixel is located one line before the pixel to be processed and the pixels located on the left and right of the corresponding pixel. Is compared with a threshold value. That is, in FIG. 5, the pixel data Da is the pixel data of the processing target pixel input to the arithmetic unit 31, and the pixel data D
b, Dc and Dd are pixel data existing in the arithmetic unit 32.

[0007] The arithmetic unit 32 generates pixel data Db, Dc, Dd.
If the threshold value to be compared with is 128, the pixel data D
If b, Dc, Dd are less than “128”, the pixel data D
The contents of b, Dc, and Dd are directly output as error data to the arithmetic unit 31, and the pixel data Db, Dc, and Dd are set to "12".
If it is 8 "or more, a value obtained by subtracting a predetermined value" 255 "from the contents of the pixel data Db, Dc, Dd is output as error data to the arithmetic unit 31. The arithmetic unit 31 outputs the error data output from the arithmetic unit 32. Is the pixel data Da of the pixel to be processed.
Is added to.

For the image data Da to Dd shown in FIG. 5, since the image data Db, Dc and Dd are smaller than the threshold value 128, the arithmetic unit 31 calculates: Da = Da + Db + Dc + Dd = 255 + 127 + 12
7 + 127 = 636 is output. When the output of the arithmetic unit 31 is represented by a binary number, it becomes 10-bit data of "10011111100". The 10-bit data is supplied to the arithmetic unit 3 via the storage device 33 for two-tone conversion processing and subsequent error diffusion processing.
2 is input. The arithmetic unit 32 compares “636” with the threshold “255” in the two-tone conversion process, and 636> 25
5 outputs “255” as image data Da. The arithmetic unit 32 determines “63” in the next error diffusion process.
6 ”is compared with the threshold“ 128 ”, and 6 is obtained from 636> 128.
36-255 = 381 is output to the arithmetic unit 31 as error data. In the image processing apparatus having the configuration shown in FIG. 3, if the bit width of the storage device 33 is 8 bits, the 10-bit data output from the arithmetic unit 31 is stored in the storage device 3.
3 cannot be stored. Therefore, as shown in FIG. 4, an arithmetic unit 37 is inserted between the arithmetic unit 31 and the storage device 33, and the arithmetic unit 37 performs overflow / underflow processing. The overflow / underflow process is, for example, a process in which data below “0” is set to “0” and data above “255” is set to “255”.

By the overflow / underflow processing, 1 representing “636” output from the arithmetic unit 31
The 0-bit data is input to the arithmetic unit 32 via the storage device 33 as 8 bits representing “255”. As a result, in the two-gradation conversion process in the arithmetic unit 32, the image data Da is “25” from 255 = 255.
5 "is output, and the same result as the configuration shown in FIG. 3 is obtained. However, in the next error diffusion processing, 255-255 = 0 is output to the arithmetic unit 31 as error data from 255> 128. Is significantly different from "381" in the configuration shown in FIG.

As described above, if the 10-bit data is to be directly stored in the storage device 33 for the two-gradation conversion processing and the next error diffusion processing in the arithmetic unit 32,
An expensive memory having a bit width of at least 10 bits is required as the storage device 33, which leads to an increase in cost. On the other hand, if a memory having a smaller bit width is used by performing a FIFO process or the like, a large difference occurs in the image processing result, resulting in image deterioration.

An object of the present invention is to provide an image processing apparatus which can use a memory having a small bit width as a storage device without causing image deterioration, and can realize cost reduction.

[0012]

According to a first aspect of the present invention, when the number of bits m of the pixel data output from the arithmetic unit is larger than the bit width n of the storage device, the storage device stores the higher-order pixel data. A storage device for storing data from bit to n bits, characterized in that a bit complementer for outputting (mn) -bit complement data to be added to the lower order of pixel data output from the storage device is provided. And

Therefore, the lower bit data of the pixel data that has not been stored in the storage device is complemented by the complement data output from the bit complementer, and the number of bits of the pixel data input / output to / from the storage device. Matches.

[0014] The invention described in claim 2 is characterized in that the bit complementer outputs complementary data generated by using part or all of the pixel data of a pixel adjacent to the processing target pixel.

Therefore, complementary data generated by using part or all of the pixel data of the neighboring pixels is added to the lower bits of the pixel data output from the storage device.

[0016] The invention described in claim 3 is characterized in that the bit complementer outputs complementary data generated based on a result of the region separation processing.

Therefore, the complementary data generated based on the result of the region separation processing is added to the lower bits of the pixel data output from the storage device.

[0018]

FIG. 1 is a diagram showing a configuration of an image processing apparatus as an example of an embodiment of the present invention. The image processing device 10 includes a computing unit 1, a computing unit 2, a storage device 3, a bit complementer 4, a data bus 5, and a data bus 6. When the image processing device 10 is provided in a digital copying machine, image data read by a CCD line sensor included in an image reading device of the digital copying machine is input to the arithmetic unit 1. The arithmetic unit 1 performs predetermined image processing on the input image data using the correction data input from the arithmetic unit 2. The image data output from the arithmetic unit 1 is input to the storage device 3 via the data bus 5. The storage device 3 outputs image data to the data bus 6 at a predetermined timing. The bit complementer 4 outputs complementary data to the data bus 6. The data output from the storage device 3 on the data bus 6 and the complementary data output from the bit complementer 4 are input to the arithmetic unit 2. The computing unit 3 binarizes the input data and outputs it as image data, and also creates correction data and outputs it to the computing unit 1.

FIG. 2 is a PAD showing a processing procedure of the image processing apparatus. The arithmetic unit 1 has “0” to “255”
The image data of n bits (8 in this case) representing the gradation of the luminance is input (s1). The arithmetic unit 1 compares the input image data with the threshold “128” and sets “0” or “2”.
The image data of 55 "is binarized, the correction data input from the arithmetic unit 2 is added to the binarized value of" 0 "or" 255 ", and the result is output to the data bus 5 (s2). The bit width of the data output from the device 1 is m
(M> n).

Of the data on the data bus 5, upper n bits of data determined by the bit width of the storage device 3 are input to the storage device 3 (s3). The storage device 3 outputs n-bit data to the data bus 6 at a predetermined timing (s4). Next, the bit complementer 4 outputs complementary data to the data bus 6 in synchronization with the data output timing of the storage device 3 (s5). That is, the bit complementer 4
Generates complementary data having the same number of bits as the number of bits (mn) that could not be input to the storage device 3 among the data on the data bus 5, and outputs the complementary data from the storage device 3. The data is output at a timing continuous below the data. At this time, the bit complementer 4 recognizes the bit number m of the pixel data based on the contents of the upper two bits of the pixel data input from the arithmetic unit 1. That is, when the upper two bits of the pixel data are "11" or "10", the bit number of the pixel data is the maximum value m, and when it is "01", the bit number of the pixel data is (m- 1)
If “00”, the number of bits of the pixel data is (m−
2). The bit width n of the storage device 3 is a fixed value,
It can be set in the bit complementer 4 in advance.

The data bus 6 treats the output data of the storage device 3 as upper bits and the output data of the bit complementer 4 as lower bits and treats both as one pixel data. (S6). Arithmetic unit 2
Sets the pixel data input from the data bus 6 to the threshold “1”.
28 ”(s7), and 2 in“ 0 ”or“ 255 ”.
It is converted into a value and output as image data (s9, s11).
At the same time, the arithmetic unit 2 determines that the pixel data has a threshold “12”.
If it is less than 8 ", the value is outputted as it is, and if it is more than the threshold value" 128 ", a value obtained by subtracting a predetermined value" 255 "from the value is outputted to the arithmetic unit 1 as correction data (s8 to s1).
0).

In the output processing of the complementary data from the bit complementer 4 in s5, the bit complementer 4
−n) A value obtained by adding 0.5 to the average value of positive integers that can be represented by bits is output as complementary data. That is, the bit complementer 4 obtains complementary data Dr to be output according to Dr = {(2 ^(mn) -1) / 2} +0.5.

Hereinafter, a case where the storage device 3 having a bit width of 8 bits is used will be described as an example. The arithmetic unit 2 is
In the processes of s7, s8, and s10, pixel data for three pixels is always stored. That is, as shown in FIG. 5, when the pixel data of the processing target pixel Da is input to the arithmetic unit 1, the arithmetic unit 2 includes the pixel data of the pixels Db, Dc, and Dd. The arithmetic unit 2 includes pixels Db, Dc,
The pixel data of Dd is compared with a threshold “128”. If the pixel data is smaller than the threshold, the value of the pixel data is output as it is to the arithmetic unit 1 as correction data. A value obtained by subtracting a predetermined value “255” from the value is output to the arithmetic unit 1 as correction data. FIG.
In the example shown in (1), pixel data “127” is output as it is for the pixels Db, Dc, and Dd.

The arithmetic unit 1 adds the correction data input from the arithmetic unit 2 to the binarized pixel data of the pixel A to be processed in the process of s2. When the pixel data of the binarized processing target pixel A is “255”, the addition result is A + B + C + D = 255 + 127 + 127 + 127 = 636, which is represented by a binary number of “10011111100”.
This becomes 0-bit pixel data. Of the pixel data, the upper 8 bits of data “10011111” are input to the storage device 3 having a bit width of 8 bits via the data bus 5. In the process of s4, the storage device 3
It outputs bit data to the data bus 6.

On the other hand, since the bit number m of the pixel data is 10 bits and the bit width n of the storage device 3 is 8 bits, the bit complementer 4 sets the value of the complement data Dr: Dr = ｛(2 ^{(10 -8)} -1) / 2} +0.5 = {(2 ² -1) / 2} + 0.5 = (4-1) /2+0.5=2 If this value is represented by (mn) bits, that is, 2 bits, it becomes "10". The bit complementer 4 outputs the “10” data to the data bus 6. The data output from the bit complementer 4 is the 8-bit data “100” output from the storage device 3 on the data bus 6.
11111 ", thereby adding" 1 ".
001111110 ″ 10-bit pixel data is input to the arithmetic unit 2.

Here, when the pixel data output from the arithmetic unit 1 and the pixel data input to the arithmetic unit 2 are compared,
Pixel data “100111111” input to the arithmetic unit 2
When "0" is represented by a decimal number, it becomes "638", and the error from the pixel data "636" output from the arithmetic unit 1 is extremely small, so that the bit width is larger than the maximum bit number of the pixel data generated in the arithmetic unit 1. Even when the storage device 3 having a small value is used, it is possible to suppress a possibility that a difference occurs in a result of the final binarization process in the arithmetic unit 2.

In the above example, the complement data output from the bit complement unit 4 is obtained by calculation based on the number of bits of the pixel data output from the arithmetic unit 1 and the bit width of the storage device 3. However, a fixed value set in advance can be output from the bit complementer 4 as complement data. For example, by outputting complementary data in which all (mn) bits are either “0” or “1”, the pixel data can be made darker or lighter as a whole, and the state of the printing apparatus can be reduced. Can be corrected.

Further, by configuring the bit complementer 4 with a register of (mn) bits, complementary data can be set arbitrarily. In this case, the larger the value of (mn), the larger the adjustment range of the brightness of the pixel data.

Further, as the bit complementer 4, a device provided with means for generating complementary data using a part or all of the neighboring pixel data can be used. As an example, upper (mn) bits of binary data of a neighboring pixel are output as complementary data. Thus, for example, a white background portion of the document is highlighted by “2” due to a reading error of the image reading device.
Even if the value cannot be read as "55" and becomes a value close to "255", "1" can be added to the lower (mn) bits of the pixel data, and the brightness of the pixel data is increased so that a white background portion of the original is increased. Can be made more white because, when a value close to “255” is represented by a binary number, the upper several bits always become “1”.

In addition, as the bit complementer 4, a device provided with a region separating means can be used. That is, the pixel data input to the arithmetic unit 1 is also input to the bit complementer 4, and the bit complementer 4 executes a region separation process using the input pixel data. As a result of this region separation processing, when an edge portion is detected in the image data, the upper (mn) bits of the pixel to be processed are output as complementary data, and when no edge portion is detected in the image data, the processing is performed. The upper (mn) bits of the target pixel are inverted and output as complementary data. This makes it possible to perform edge enhancement processing on the pixel data using the complementary data.

[0031]

According to the first aspect of the present invention, it is possible to complement the lower-order bit data of the pixel data that has not been stored in the storage device with the complement data output from the bit complementer, The number of bits of pixel data input / output to / from the storage device can be matched. Therefore, even if a storage device having a bit width smaller than the maximum number of bits of pixel data generated in the arithmetic unit is used, a large error does not occur in the pixel data, and the cost of the device is reduced without deteriorating the image. it can.

According to the second aspect of the present invention, by adding complementary data generated by using part or all of the pixel data of the neighboring pixels to the lower bits of the pixel data output from the storage device, An error generated in the pixel data before being input to the image processing device can be absorbed to obtain clearer image data.

According to the third aspect of the invention, the edge portion of the image is emphasized by adding the complementary data generated based on the result of the region separation processing to the lower bits of the pixel data output from the storage device. can do.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an image processing apparatus that is an example of an embodiment of the present invention.

FIG. 2 is a PAD showing a processing procedure of the image processing apparatus.

FIG. 3 is a diagram illustrating a configuration of a conventional image processing apparatus.

FIG. 4 is a diagram illustrating a configuration of another conventional image processing apparatus.

FIG. 5 is a diagram showing pixel data in an error diffusion process of a computing unit of a general image processing device.

[Explanation of symbols]

 1-arithmetic unit 2-arithmetic unit 3-storage device 4-bit complementer 5-data bus 6-data bus

Claims (3)

[Claims] 1. An image processing apparatus comprising: an arithmetic unit for performing predetermined processing on pixel data; and a storage device for temporarily storing pixel data input to and output from the arithmetic unit. A storage device for storing n-bit data from the upper bits of the pixel data when the number of bits m of the pixel data output from the arithmetic unit is larger than the bit width n of the storage device, wherein the pixel output from the storage device is An image processing apparatus comprising: a bit complementer for outputting complement data of (mn) bits to be added to the lower part of data. 2. The image processing apparatus according to claim 1, wherein the bit complementer outputs complementary data generated by using part or all of pixel data of a pixel adjacent to the pixel to be processed. 3. The image processing apparatus according to claim 1, wherein the bit complementer outputs complementary data generated based on a result of the region separation processing.