JPH08130644A - Image processing unit - Google Patents

Abstract

PURPOSE: To obtain a binarized image operated at a high speed by applying error diffusion processing to weighting arithmetic operation for an error of a just preceding picture element through data conversion with a 2nd memory means. CONSTITUTION: A register 6 being a 1st memory means latches error data produced when a picture element signal of a preceding line to a noticed picture element is binarized. A current line error data conversion section 10 applies weighting arithmetic operation to data of a picture element just precedingly to a noticed picture element through data conversion by a 2nd memory means. An adder block 2 reflects data from a preceding line error weighting block 1 and data from the conversion section 10 onto the noticed picture element to correct the luminance. Thus, the weighting arithmetic operation for the error of the preceding picture element is conducted through data conversion by the 2nd memory means in this way to eliminate the need for complicated processing such as multiplication, division and comparison discrimination and a gray level image is subjected to error diffusion processing at a high speed to obtain a binary image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for binarizing a grayscale image signal by an error diffusion method.

[0002]

2. Description of the Related Art Conventionally, as a binarizing method for expressing a halftone in a digital printer, a digital copying machine, etc., in 1975, Floid and Steinberg,
“An Adaptive Algorithm for Spatial Grayscale”
(Proceeding of the SID Vol. 17/2 Second
There is an error diffusion method proposed in a paper called Quater 1975). This binarization method is characterized in that the error generated in the binarization process is dispersed to surrounding pixels and the image density is preserved. A block diagram of a general circuit configuration for implementing this technique is shown in FIG. In FIG. 3, 1 is a front line error weighting block for performing a product-sum operation of the error of the previous line and a weighting coefficient, 2 is an addition block for adding the peripheral error amount to the pixel of interest, and 3 is the luminance of the pixel of interest. An error calculation processing block for calculating binary data and an error amount with respect to the corrected brightness data, 4 is a current line error weighting block for performing a sum of products operation of an error of the current line and a weighting coefficient, Reference numeral 5 is an n-line delay line having a line memory for the number of lines of the pixel matrix of the sensor for delaying n lines. Reference numeral 6 is a register composed of one stage D flip-flop.

Regarding the operation of the error diffusion processing circuit configured as described above, Japanese Patent Application No.
As described in No. -106219, consider a two-line matrix size as shown in FIG. 4A as an example of binarization. In this case, when P is the pixel data of interest, G1, G2, G3, and GP1 represent the error amount when binarizing at that position, and (B) of FIG. 4 represents the weighting coefficient for the error amount. Here, α is represented by the following equation (1). α = K1 + K2 + K3 + K4 (1)

Next, the operation of the error diffusion processing circuit shown in FIG. 3 will be described based on this matrix. In the previous line error weighting block 1, the errors G1, G2 and G3 one line before, which are delayed by the line delay line 5, are multiplied by K1 / α, K2 / α and K3 / α, respectively,
I'm taking a sum. The calculation in this block 1 is expressed by the following equation (2). Previous line error sum = (K1 / α) · G1 + (K2 / α) · G2 + (K3 / α) · G3 (2) On the other hand, regarding the error of the current line, the current line error weighting block 4 is used. Then, the calculation as in the following equation (3) is performed. Current line error sum = (K4 / α) · GP1 (3) In this example, since the error of the current line uses only the data one pixel before, the current line error weighting block 4 is shown in FIG. The circuit configuration is as shown in. In FIG. 5, 7 is a multiplier for multiplying the error and the weighting coefficient.
If the pixel matrix and the weighting coefficient are as shown in FIGS. 6A and 6B, the current line error weighting block 4 has a configuration as shown in FIG. If the reference pixel error of the current line is large in this way, the multiplier 7 for that pixel is required, and n stages of D-stages are required for the error of the nth previous pixel.
You need a flip-flop.

The error weighted by the previous line error weighting block 1 and the current line error weighting block 4 is
In the addition block 2, the luminance data of the pixel of interest is added,
The peripheral error information is reflected in the luminance data of the pixel of interest. The data corrected by the addition block 2 is subjected to the error calculation processing block 3 to determine whether the pixel of interest is white / black, and the error amount at that time is calculated, and when the subsequent pixel is binarized. It is designed to be used as the error of.

In order to realize these operations for the matrix shown in FIG. 4, the block diagram shown in FIG.
It is embodied as shown in. In FIG. 8, 21-1 to 21
-8 is a one-stage register, 22-1 to 22-4 are multipliers for integrating the weighting coefficient and the error amount, 23-1 to 23-4 are adders, and 24 is a threshold level of the d signal. ), A comparator for outputting "H", 25 is a subtractor, 26 is an output of the subtractor 25 when the S terminal is "L",
A selector for selecting the d signal when it is "H", and a line memory 27 for storing an error for one line.

Next, the operation of the error diffusion processing circuit having the above configuration will be described with reference to the timing chart of FIG. When considering binarizing the pixel data of the pixel of interest P, the error amounts G1 to G3 of the periphery (one line before) are G1 at time t0, G2 at time t1, and time t2 as shown in FIG.
If G3 is input as error data in, the a signal is a signal that is output through the register 21-2 after the error amount G1 and the coefficient K1 / α are integrated in the multiplier 22-1, and the b signal is Is the error amount G2 and the coefficient K2 in the multiplier 22-2.
/ Α is integrated, the a signal is added to the integrated signal by the adder 23-1, and is output through the register 21-3. Similarly, the c signal is output by the multiplier 22-3. The error amount G3 and the coefficient K3 / α are integrated, the b signal is added to the integrated signal by the adder 23-2, and the register 21-4 is added.
Is a signal output via. The c signal at this time represents the sum total of the calculation of the error amount of the periphery (one line before).
(Time t4)

At the next time t5, the pixel data d is corrected by the peripheral error with respect to the pixel of interest P. The corrected pixel data d is binarized, and the corrected pixel data d corresponds to the binarized threshold level (Thresh) preset in the comparator 24. When compared, the output is determined to be "L" when it is higher than the threshold level, and white ("L") is output as the binary output D1 at time t6. Similarly, when the pixel data d is smaller than the threshold level, black (“H”) is output as the binary output D2 at time t7.

When the comparator 24 makes a judgment of white ("L"), the selector 26 selects the output of the subtractor 25. In the subtractor 25, the pixel data d
And White (the maximum white level) are subtracted, and the error from White is sent from the selector 26 as the error amount in the pixel of interest P. When the comparator 24 determines that the pixel is black (“H”), the selector 26 selects the pixel data d, and the error from the maximum black level (“0”), that is, the pixel data d It is sent as an error amount at P. This error amount is fed back as an error amount GP1 on the left side when processing the next pixel, and is stored in the line memory 27 to be used as an error of the next line. By performing such processing, it is possible to obtain a binary image by performing error diffusion processing on the grayscale image.

[0010]

However, in the error diffusion processing circuit having such a configuration, the error value calculated by the error calculation processing block is required at the time of error calculation of the next pixel of interest, and the video signal Was difficult to process in real time. In this case, the weighting calculation of the error at the immediately preceding pixel position (one pixel before) takes the longest processing time. Specifically, in the block diagram shown in FIG. 3, the error calculation processing block 3 → current line error weighting block 4 → addition block 2 → register 6
In the circuit configuration diagram shown in FIG. 8, the subtractor 25
→ Selector 26 → Multiplier 22-4 → Adder 23-3 → Adder 23
-4 → Register 21-5 is a signal system, and speeding up the operation of this signal system has led to high-speed processing of the system.

The present invention is based on the conventional error diffusion processing method.
The object of the present invention is to provide a binarized image processing device using an error diffusion method that can be operated at high speed, and has been made in order to solve the above problems in the binarized image processing device.

[0012]

In order to solve the above problems, the present invention acquires a grayscale image signal of a subject by a sensor and obtains a binarized image signal from the image signal by an error diffusion method. In the image processing apparatus described above, a first memory means for holding error data generated when a signal of a pixel on a line before the pixel of interest is binarized, and a means for weighting the preceding line error data. When,
A means for weighting the error data of the immediately preceding pixel of the pixel of interest by data conversion by the second memory means, the data from the preceding line error weighting means and the data from the immediately preceding pixel error weighting means are reflected in the pixel of interest. And adding means for correcting the luminance to correct the brightness, and means for binarizing the corrected pixel data from the adding means at the threshold level and calculating the error data at that time. The image processing apparatus is configured to perform the error diffusion processing obtained by the data conversion by the memory means. A line memory, a shift register or the like is used as the first memory means, and a ROM, a RAM or the like is used as the second memory means.

In the image processing apparatus configured as described above, the weighting calculation of the error of the immediately preceding pixel, which becomes the most bottleneck in speeding up the processing, is performed by the data conversion by the second memory means. High-speed error diffusion processing can be realized. Since the weighting calculation of the error of other pixels does not cause any problem in the processing, the RO calculation is performed by using the conventional arithmetic unit.
Perform error diffusion processing with a simple configuration without using M,
A binary image can be obtained.

[0014]

EXAMPLES Next, examples will be described. FIG. 1 is a block configuration diagram showing a basic configuration of an image processing apparatus according to the present invention, and the same or corresponding members as those of the conventional example shown in FIG. 3 are designated by the same reference numerals. In FIG.
1 is a front line error weighting block for performing a product-sum operation of the error of the previous line and a weighting coefficient, 2 is an addition block (target pixel correction block) for adding the peripheral error amount to the target pixel, and 3 is the target pixel An error calculation processing block for calculating binary data and an error amount with respect to the brightness data in which the brightness data is corrected, 5 has a line memory for the number of lines in the matrix, and an n-line delay line for delaying n lines, 6 is a one-stage register (D flip-flop),
Reference numeral 10 is a current line error data conversion unit (lookup table).

Next, FIG. 2 shows a specific circuit configuration of the basic configuration shown in FIG. The circuit configuration shown in FIG.
The description is omitted because it is the same as the conventional example shown in FIG. 8 except that the M28 is provided. The ROM 28 is a memory capable of reading out the previously input data by inputting an address, receives the corrected pixel data d from the register 21-5 as an input, and has its output connected to the adder 23-3.

Next, the operation of the circuit shown in FIG. 2 will be described. If the pixel of interest is represented by 8-bit data, the maximum level (white level) is 255. Adder 23
At -4, corrected pixel data is output by adding the target pixel to the surrounding error data. If the corrected pixel data added with the error data exceeds "255" here, "25"
The value of the corrected pixel data d is always 8 bits, so that the value of the corrected pixel data d is always 8 bits. Is input as the address of the ROM 28, and the previously input data of the ROM 28 is read out.
That is, the ROM 28 has an equivalent function when the error weighting calculation of the immediately preceding pixel is performed and the error pixel weighted value is converted based on the corrected pixel data.

The data to be converted by the ROM 28 should have the following values for the corrected pixel (luminance) data d. When 0 ≦ d ≦ Thresh ・ ・ ・ (K4 / α) × d Thresh ≦ d ≦ White ・ ・ ・ (K4 / α) × (d-
White) K4 / α is a constant determined by the system (error matrix), White is a fixed value of "255", and Thresh is a fixed value of "128".
Can be used.

It is well known that the brightness of an image can be changed by changing White as shown in the above-mentioned Japanese Patent Application No. 6-106221. Generally, the smaller the value of White, that is, Th
The closer to resh, the brighter the image.

When this principle is applied to the present invention, for example,
Set the White value to "255", "223", "191", "159".
Assuming that it is made variable in four levels of “, as shown in Table 1, (K4 / α) × (d−) corresponding to each White
The value of (White) should be stored in ROM.

[0020]

[Table 1]

That is, if the value of White is set to n stages, it is preferable to use a ROM of 256 × n words.

In the above embodiment, the correction pixel data d is used as an address and used as it is. However, by using only the upper bits of the 8 bits of the correction pixel data d as an address, the ROM The capacity can be reduced. That is, for example, in the case of 8 bits, a capacity of 2 ⁸ = 256 words is required, but the lower 2 bits are not used and are discarded, and only the upper 6 bits are stored in the ROM.
If it is used as the address of, a ROM with a capacity of 2 ⁶ = 64 words can be used. In this case, the error of the adjacent one pixel becomes somewhat inaccurate, but it has been confirmed that there is no particular problem in appearance even if the lower 2 bits are discarded. If ROM is used as the memory, RO
The access time of M is set to a time shorter than (processing time of error diffusion processing / 1 pixel).

Further, in the above embodiment, the ROM is used only for the error weighting calculation of the immediately preceding pixel, but the ROM can be used for the error weighting calculation of other portions.

[0024]

As described above on the basis of the embodiments,
According to the present invention, the weighting calculation of the error of the previous pixel is performed in the ROM.
Since it is performed by the data conversion by the second memory means such as, the complicated processing such as multiplication, division and comparison determination is unnecessary, and the binary image is obtained by performing the error diffusion processing on the grayscale image at high speed. You can

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a basic configuration of an image processing apparatus according to the present invention.

FIG. 2 is a circuit configuration diagram showing a specific embodiment of the present invention.

FIG. 3 is a block configuration diagram showing a basic configuration of a binary image processing apparatus using a conventional error diffusion method.

FIG. 4 is a diagram showing an error matrix and a weighting coefficient for explaining the error diffusion processing.

5 is a diagram showing a configuration example of a current line error weighting block in the basic configuration shown in FIG.

FIG. 6 is a diagram for explaining a general pixel matrix.

7 is a diagram showing a circuit configuration example for realizing the current line error weighting block shown in FIG. 3 with the matrix shown in FIG. 6;

FIG. 8 is a diagram showing a specific circuit configuration example of the basic configuration shown in FIG.

9 is a time chart for explaining the operation of the circuit configuration example shown in FIG.

[Explanation of symbols]

 1 Previous Line Error Weighting Block 2 Addition Block 3 Error Calculation Processing Block 5 n Line Delay Line 6 Register 10 Current Line Error Data Converter

Claims (1)

[Claims] 1. An image processing apparatus, wherein a grayscale image signal of a subject is obtained by a sensor, and a binarized image signal is obtained from the image signal by an error diffusion method. First memory means for holding error data generated when binarized, means for weighting the preceding line error data, and error of the pixel immediately preceding the pixel of interest by data conversion by the second memory means. Data weighting means, adding means for correcting the luminance by reflecting the data from the previous line error weighting means and the data from the immediately preceding pixel error weighting means on the target pixel, and the correction pixel from the adding means And binarizing the data at a threshold level and calculating the error data at that time. The error weighting data of the immediately preceding pixel is stored in the second memory. An image processing apparatus characterized in that error diffusion processing is performed by data conversion by means.