JP3249348B2 - Image data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus, and more particularly to an image data processing apparatus for converting image data including a multi-tone image into binary data by using an error diffusion method.

[0002]

2. Description of the Related Art In recent years, with the growing demand for natural and high-quality image display, display of multi-tone images including halftones has been required instead of displaying only black and white binary images.
Here, when displaying a multi-tone image using a binary display system (such as a printer capable of printing only black or white binary), a pseudo-tone processing technique using a binary image must be used. . An error diffusion method is well known as a high-performance pseudo gradation processing technique.

In the error diffusion method, a density value to be image-displayed at an arbitrary pixel point and a predetermined threshold value for determining whether to display all white (full scale white) or all black (full scale white) are determined. Is added to or subtracted from the data of pixel points around the pixel point, thereby realizing a pseudo display of a multi-tone image. More specifically, as represented by Expression (1), the density g to be image-displayed for the pixel point at x row and y column
An error E (x, y) is generated by subtracting the density (display value) P to be actually displayed from (x, y). And the error E
(X, y) is divided by an appropriate division ratio and added to pixel points around the pixel point in x rows and y columns.

E (x, y) = g (x, y) -P (1) When the error diffusion method is used, macroscopic resolution is sacrificed, but when a binary display system is used. However, a display that allows a person to visually perceive a multi-tone image becomes possible.

FIG. 3 shows a block circuit of a conventional image data processing apparatus using the error diffusion method. The image data processing device 11 includes a numerical value conversion circuit 16, an adder / latch 12,
3, a binarization circuit 14, and an error calculation circuit 15,
Input data (image data) to output data (binary data)
Convert to The image data corresponds to the density g (x, y) to be image-displayed with respect to the pixel point at the x-row and y-column, and the binary data corresponds to the display value P.

The input image data is digital data representing a multi-tone image, and is obtained by A / D converting analog data of the density at a pixel point using an A / D converter (not shown). The numerical value of the input image data is handled as an offset binary not including a sign bit.
For example, if the low-potential side of the analog data of the density at the pixel point is black and the high-potential side is white, when the analog data is A / D converted using a 6-bit A / D converter, it is treated as offset binary. When the code of the present image data is 00H, it is blackest (all black), becomes gradually whiter as the code increases, and becomes whitest (full white) when it is 3FH.

The input image data is converted to a numerical value conversion circuit 1
6 to the binarization circuit 14 via the adders / latches 12 and 13 sequentially. That is, when the first input image data is transferred to the binarization circuit 14, the adder / latch 13 latches the second input image data, and the adder / latch 12 The image data that is input first is latched.

The sign bit adding circuit 16 adds a sign bit to the highest order of the image data handled in the offset binary to extend the number of bits. That is, as shown in FIG. 4, X represented by a numerical value range of 0 to (+2 ^X −1).
The bit image data has a sign bit S added to the most significant bit and has an expression value width of -2 ^X to (+2 ^X -1) (X
+1) -bit image data. However, since the content of the image data itself does not change, the image data does not fall within the range of -2 ^X to -1 even at the time of input to the sign bit adding circuit 16.

The binarization circuit 14 performs binarization by comparing a predetermined threshold value with image data to which a sign bit has been added. That is, if the image data to which the sign bit is added is less than the threshold value, binary data corresponding to all black is generated, and if the image data converted to two's complement is equal to or greater than the threshold value, binary data corresponding to all white is generated. Generate data. Normally, the threshold is set to half the value of the numerical value range of the image data.
The threshold is (+2 ^X -1). For example, when the image data handled in the offset binary is 6 bits, the expressed numerical value width is 0 to +63 (= + ²⁶ -1), and the threshold value is 31 (= ²⁵ -1).

An error calculating circuit 15 calculates a deviation (error data) between the binary data generated by the binarizing process in the binarizing circuit 14 and the image data, and appropriately weights the error data. It is distributed to each adder / latch 12 and 13. This error data is obtained by calculating the error E (x,
y).

Here, when the image data is larger than the threshold, the error data becomes negative when the image data exceeds the image data representing all white, and when the image data falls below the image data representing all white, the error data becomes negative. Is a plus. When the image data is smaller than the threshold value, the error data becomes negative when the image data exceeds the image data representing all black, and becomes positive when the image data falls below the image data representing all black. . Since the image data handled by the binarization circuit 14 is obtained by adding error data, the image data may exceed the image data representing all white or may fall below the image data representing all black.

The distribution ratio (error diffusion ratio) of the error data is, for example, 1/4 of the error data for each adder / latch 12, and 3/3 of the error data for each adder / latch 12. For example, / 4 is set so that the total becomes 1.

The adders / latches 12 and 13 are respectively
The distributed error data is added to the latched image data. That is, the error data is stored in each adder / latch 1
Diffusion (error diffusion) is performed on the image data latched in 2 and 13.

Therefore, even if the image data input from the sign bit adding circuit 16 is smaller than the threshold value, if the plus error data is added to each of the adders / latches 12 and 13 and becomes larger than the threshold value, The value conversion circuit 14 converts the image data into binary data corresponding to all white. Conversely, even if the image data is equal to or greater than the threshold value, if the value becomes less than the threshold value due to the addition of the negative error data in each of the adders / latches 12 and 13, the binarization circuit 14 converts the image data into all data. Convert to binary data corresponding to black. That is, the larger the value of the image data handled in the offset binary, the higher the density of the white display by the binary data, and the smaller the value of the image data, the higher the density of the black display. As a result, the gray (gray scale) of the original image data can be approximated by the difference in the density of white display, and a smooth gradation can be obtained.

The reason why the sign bit adding circuit 16 is provided is that negative error data is generated in the error calculating circuit 15 as described above. That is, since negative error data is used in the addition processing in each of the adders / latches 12, 13, a sign bit is added to the image data.

[0016]

As shown in FIG. 3, the numerical value representation area of the image data converted into two's complement in the numerical value conversion circuit 16 is biased toward the positive number side. Therefore, when the adder / latch 12 or 13 adds the plus error data to the image data converted into the two's complement, the added image data tends to overflow on the positive number side. Therefore, the bit width of each of the adders / latches 12 and 13 needs to be set large in advance in consideration of the overflow. As a result, there is a problem that the circuit scale of each adder / latch 12, 13 increases.

In addition, the expression numerical value area of the image data after addition is also biased toward the positive side, and the negative side is hardly used. The utilization efficiency of the devices / latches 12 and 13 is extremely low.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve the efficiency of use of an arithmetic circuit for performing an error diffusion process and to reduce the circuit scale of the arithmetic circuit to a necessary minimum. An object of the present invention is to provide an image data processing device capable of performing the following.

[0019]

According to the first aspect of the present invention, a sign bit is added to image data handled in binary notation of an appropriate number of bits without a sign bit, and a representation numerical width of the image data is defined. The gist of the invention is to provide a numerical value converting means for shifting the image data by a half in the negative direction and an error diffusion processing means for performing an error diffusion process on the numerically converted image data to generate binary data.

According to a second aspect of the present invention, in the image data processing apparatus according to the first aspect, the conversion means inverts the most significant bit of the image data and has the same numerical value as the inverted most significant bit. Is added as a sign bit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In the present embodiment, the same components as those of the conventional embodiment shown in FIGS. 3 and 4 have the same reference numerals, and detailed description thereof will be omitted.

The present embodiment is different from the conventional embodiment in that the sign bit adding circuit 16 is replaced by a numerical value converting circuit 17. Then, the threshold value set in the binarization circuit 14 is set to 0. The numerical value conversion circuit 17 of the present embodiment adds a sign bit to image data handled in offset binary, and converts the image data into 1 /
Shift by two in the negative direction. That is, as shown in FIG. 2, the X-bit image data represented by the expression value width of 0 to (+2 ^X -1) is obtained by inverting the most significant bit to become Xt bits, and the sign bit S is placed at the higher order. By being added, (X has an expression value width of −2 ^X to (+2 ^X −1))
+1) -bit image data. However, the numerical width that the input image data can actually take is −2 ^X−1 to (+2
^X-1 -1).

For example, when the image data handled in the offset binary is 6 bits, the expressed value width is 0 to
+63 (= + ²⁶ -1). Then, the sign data S is added to the image data converted by the numerical value conversion circuit 17 to become 7 bits, and the expressed numerical value width is −64 (= −).
2 ⁶ ) to +63 (= + 2 ⁶ −1). Among them, a range in which image data can actually take is -32 (= - 2 ⁵⁾
To +31 (= + ²⁵ -1). Thus, in the binarization circuit 14, the threshold value is set to 0 in accordance with the numerical value width of the image data.

According to the present embodiment configured as described above, the following operations and effects can be obtained. By inverting the most significant bit of the image data handled in the offset binary and adding a sign bit, the image data is shifted in the negative direction by の of the expressed value width. As a result, the possible range of the image data converted by the numerical value conversion circuit 17 is equal on the positive number side and the negative number side. Therefore, each adder / latch 1
In steps 2 and 13, even when the plus error data is added to the image data, the added image data does not overflow on the positive number side. Therefore, each adder / latch 1
The bit widths of the adders / latches 12 and 13 can be set to the minimum necessary.

Since the expression value area of the image data after addition is also equal on the positive side and the negative side, the addition of each adder / latch 12, 13 can be made extremely efficient.

The processing in each of the circuits 12 to 15 is the same as in the conventional embodiment, and each of the adders / latches 12, 1
3 hardly overflows, so that accurate error diffusion processing can be performed.

The above-described embodiment is applied to an image data processing apparatus which performs more complicated error diffusion processing (for example, two-dimensional error diffusion processing) than the image data processing apparatus 11. Such an error diffusion processing method is (R.FLOYD &
L.STEINBERG; SID75.Dig, pp36-37), JP-A-63-1
No. 02473 (IPC; H04N1 / 40, G06K9 / 38) and the like.

By the way, in this specification, the members according to the constitution of the invention are constituted by the following members in the embodiment. (A) The error diffusion processing means includes an adder / latch 12, 1
3, a binarizing circuit 14, and an error calculating circuit 15.

(B) The numerical value conversion means comprises a numerical value conversion circuit 17.

[0030]

As described above in detail, according to the present invention, it is possible to improve the utilization efficiency of the arithmetic circuit for performing the error diffusion process and to minimize the circuit scale of the arithmetic circuit. A processing device can be provided.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of one embodiment.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 3 is a block circuit diagram of a conventional mode.

FIG. 4 is an explanatory diagram for explaining the operation of the conventional embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Image data processing apparatus 12, 13 ... Adder / latch 14 ... Binarization circuit 15 ... Error calculation circuit 16 ... Sign bit addition circuit 17 ... Numerical conversion circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/405 G06T 5/00 200

Claims (2)

(57) [Claims] 1. Numerical conversion means for adding a sign bit to image data handled in a binary representation of an appropriate number of bits without a sign bit and shifting the image data in a negative direction by a half of the expressed value width of the image data. An image data processing apparatus comprising: an error diffusion processor that performs an error diffusion process on the numerically converted image data to generate binary data. 2. The image data processing apparatus according to claim 1, wherein the conversion means inverts the most significant bit of the image data and adds the same numerical value as the inverted most significant bit as a sign bit.