JPH1056436A - Digital signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process a plurality of signals with different data rates with a small sized inexpensive device. SOLUTION: A video signal processing circuit 34 samples and digitally encodes a video signal received by an input terminal 30 by a prescribed frequency and an voice signal processing circuit 36 applies digital coding to a voice signal received at an input terminal 32. The circuits 34, 36 sample the input signal and output a memory access request signal to an arbitration circuit 48. The arbitration circuit 48 takes precedence of the circuit 34 over the circuit 36 to enable write to a RAM 38. After the video signal and the voice signal are written in the RAM 38, a data output circuit 40 reads data stored in the RAM 38 and stores the data tentatively in an internal memory. Then the circuit 40 reads the stored data from the internal memory so that the speed of the data outputted from an output terminal 42 is in matching with a speed of an external transmission system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processing method for digitally processing a plurality of signals having different data rates.

[0002]

2. Description of the Related Art In order to transmit several kinds of data, usually,
A time-division multiplexing method is used, and when the data rates of the data are different, the time axis is compressed by a time axis compressor to make the transmission rates uniform.

FIG. 4 is a block diagram showing a configuration of a conventional example of an apparatus for transmitting video and audio. A video signal is input to the input terminal 10, and an audio signal is input to the input terminal 12. The video signal input to the input terminal 10 is digitized by the video signal processing circuit 14, and the audio signal input to the input terminal 12 is digitized by the audio signal processing circuit 16.

In the case of a video signal and an audio signal, a video signal having a wider signal band has a higher data rate.
6 cannot be multiplexed as they are, and are respectively multiplexed by the multiplexer 22 after the time axis conversion by the time axis converters 18 and 20 respectively. Then, in order to match the transmission speed of the transmission path, the time axis is further converted by the time axis converter 24 and transmitted from the output circuit 26 to the transmission path. The time axis converters 18, 20, 24 are composed of random access memories, and a memory control circuit 28 controls writing and reading.

[0005]

As described above, in a system for processing a plurality of data having different data rates and data obtained by multiplexing the plurality of data, a time is required for each of the plurality of data having different data rates. Since a circuit for axis processing is required, it has been a factor that hinders miniaturization and cost reduction of the entire system.

Accordingly, an object of the present invention is to provide a digital signal processing method which can be manufactured more compactly and inexpensively.

[0007]

SUMMARY OF THE INVENTION A digital signal processing method according to the present invention is a digital signal processing method for handling a first digital signal.
Means for handling a second digital signal, and third means for handling a digital signal obtained by time-division multiplexing the first digital signal and the second digital signal.
And a storage means connected to each of the first means, the second means, and the third means via a bus, wherein the storage means of the first means is provided. A request for access to the storage means of the second means and a request for access to the storage means of the third means are selectively permitted.

With such a configuration, the time axis conversion means can be reduced, and the circuit can be downsized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment in which the present invention is applied to a data transmitting apparatus, and FIG. 2 is a block diagram showing the configuration of a corresponding receiving apparatus.

In FIG. 1, reference numeral 30 denotes an input terminal for an analog video signal, 32 denotes an input terminal for an analog audio signal, 30 denotes a video signal processing circuit for digitizing a video signal input to the input terminal 30, and 36 denotes an input terminal. An audio signal processing circuit 38 for digitizing the input audio signal is a random access memory (RA) for time axis conversion processing.
M) and 40 are data output circuits for outputting data input irregularly in time to a transmission line for a fixed time, and include a random access memory. Reference numeral 42 denotes an output terminal connected to the transmission line.

The video signal processing circuit 34, the audio signal processing circuit 36, the RAM 38 and the data output circuit 40
They are interconnected by a bus 44 and an address bus 46. Reference numeral 48 denotes an arbitration circuit for arbitrating the use request of the RAM 38 from the video signal processing circuit 34, the audio signal processing circuit 36, and the data output circuit 40.

The operation of FIG. 1 will be described. The video signal processing circuit 34 samples and digitally encodes the video signal input to the input terminal 30 at a predetermined frequency, and the audio signal processing circuit 36 digitally encodes the audio signal input to the input terminal 32. Since the video signal has a wider frequency band than the audio signal, the sampling frequency of the video signal is higher than the sampling frequency of the audio signal. Upon sampling the input signal, the video signal processing circuit 34 and the audio signal processing circuit 36 output a memory access request signal to the arbitration circuit 48. The arbitration circuit 48 permits writing to the RAM 38 in accordance with a predetermined priority (in this embodiment, the video signal processing circuit is given priority over the audio signal processing circuit). Although the writing of the audio signal into the RAM 38 is performed after the writing of the video signal, there is no problem because the sampling frequency of the audio signal is considerably lower than the sampling frequency of the video signal.

After the video signal and the audio signal have been written into the RAM 38, the data output circuit 40 reads out the data stored in the RAM 38 and temporarily stores it in an internal memory. And
The stored data is read from the internal memory so that the data speed output from the output terminal 42 matches the speed of the external transmission system. It goes without saying that the bit rates of the video data and the audio data are set to be lower than the bit rates of the external transmission system.

Next, the receiving apparatus shown in FIG. 2 will be described. 50 is an input terminal to which a reception signal from the transmission line is input;
52, a data input circuit; 54, a RAM; 56, an audio signal processing circuit for converting received audio code data to an analog signal; 58, a video signal processing circuit for converting received video code data to an analog signal; An output terminal, an output terminal for an analog video signal; a data bus for interconnecting a data input circuit, a RAM, an audio signal processing circuit, and a video signal processing circuit;
66 is an address bus for interconnecting the data input circuit 52, the RAM 54, the audio signal processing circuit 56 and the video signal processing circuit 58, and 68 is a RAM 54 composed of the data input circuit 52, the audio signal processing circuit 56 and the video signal processing circuit 58.
Arbitration circuit that arbitrates access to

The operation of FIG. 2 will be described. The data input from the transmission path to the input terminal 50 is based on the data rate of the transmission path and the RA.
The data is temporarily stored in an internal memory of the data input circuit 52 in order to absorb a difference from the processing speed of the M54 or the like. The data input circuit 52 issues a memory access request to the arbitration circuit 68 in order to transfer the data stored in the internal memory to the RAM 54, and when the arbitration circuit 68 has a memory access permission,
The data stored in the internal memory is written into the RAM 54.

Next, the video signal processing circuit 58 and the audio signal processing circuit 56 issue a memory access request to the arbitration circuit 68 to read the data stored in the RAM 54. The arbitration circuit 68 gives priority to the request from the video signal processing circuit 58 in the same priority order as in the case of transmission, that is, gives priority to the request. The memory access to the RAM 54 by the audio signal processing circuit 56 is performed after the memory access by the video signal processing circuit 58, but there is no problem due to the difference in data speed. The video signal processing circuit 58 having received the memory access permission
The video data is read from the AM 54, converted into an analog video signal, and output to the output terminal 62. Further, the audio signal processing circuit 56 having received the memory access permission
And only the audio data is read out, and converted back to an analog audio signal and output to the output terminal 60.

The transmission data is divided into blocks on the transmitting side in advance, and the audio data and the video data can be easily distinguished by adding an address to each block with an identification flag.

FIG. 3 shows a flowchart of the priority determining process in the arbitration circuits 48 and 68. The priority order is determined by the video signal processing circuits 34 and 58 and the audio signal processing circuit 3
6, 56, and the output circuit 40 or the input circuit 52.

[0020]

As can be easily understood from the above description, according to the present invention, when handling each of a plurality of data having different data rates and data obtained by multiplexing the plurality of data, the matching of the time axes of the data is performed. Since such a circuit is not required, the size and cost of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a transmission device according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a receiving device.

FIG. 3 is a flowchart of an arbitration process of arbitration circuits 48 and 68.

FIG. 4 is a configuration block diagram of a conventional example.

[Explanation of symbols]

 30, 32, 50: input terminal 34, 58: video signal processing circuit 36, 56: audio signal processing circuit 38, 54: random access memory 40: data output circuit 42, 60, 62: output terminal 44, 64: Data bus 46, 66: Address bus 48, 68: Arbitration circuit 52: Data input circuit

Claims (1)

[Claims] 1. A first means for handling a first digital signal, a second means for handling a second digital signal, and a time division multiplex of the first digital signal and the second digital signal. The third that handles digital signals
And a storage unit connected to each of the first unit, the second unit, and the third unit via a bus, wherein the storage unit of the first unit is A digital signal processing method characterized by selectively permitting an access request to the storage means of the second means and an access request to the storage means of the third means.