JPH1056364A - Pwm modulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the PWM modulator circuit easy to adjust and vary the response speed. SOLUTION: A data width adjusting circuit 3 adjusts the data width of data for modulation according to a data width adjustment control signal. The count value of a variable counter 5 varies according to the data width adjustment control signal. According to the count number and adjusted data width, a PWM modulating and converting circuit 4 generates a PWM modulation output. The PWM modulating and converting circuit 4 preferably includes a zero detector 12 which detects the initial value of the count value and generates a zero- detection signal, a comparator 11 which compares the count number with the said adjusted data width and generates a comparison result signal, and a PWM waveform output unit 13 which generates a PWM modulation output according to the zero-detection signal and comparison result signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM modulation circuit, and more particularly to a PWM for a transmission signal receiving device and other electronic devices.
The present invention relates to a modulation circuit.

[0002]

2. Description of the Related Art Generally, a circuit for providing digital data to a PWM modulation circuit and smoothing the output of the PWM modulation circuit by a low-pass filter to obtain an analog waveform transfers data between the digital circuit and the analog circuit. It is used when doing. This PWM modulation circuit replaces the amount of digital data with the pulse width and converts the level of the data into a pulse length (for example, Japanese Patent Laid-Open No. 7-177).
No. 038).

FIG. 8 shows an example of a conventional PWM modulation circuit. This PWM modulation circuit includes a counter 71 having N bits, and a PWM modulation conversion circuit 4 for converting N-bit digital input data into a PWM modulation output based on the count information of the counter 71.

FIG. 9 shows an example of a pulse output waveform in a conventional example. In the pulse output of the PWM modulation circuit when N is 8, one pulse period is constant at 2 8 counts, that is, 256 counts. Depending on the size of the data for modulation, the ratio between the H level and the L level, so-called, A PWM waveform having a duty ratio of 256 types is obtained.

In FIG. 9, A is an offset binary value, and MBS represents a code. When converted to a binary number, it represents the same value range as B.

[0006]

However, there is a close relationship between the number of bits of digital data to be PWM-modulated and the counter period. If only the period of the pulse is changed, a mismatch between the modulation data and the modulation data will result. Therefore, the pulse period of the modulation cannot be easily changed by the conventional PWM modulation circuit. Therefore, the response speed of the D / A conversion circuit that smoothes the output of the PWM modulation circuit with a low-pass filter cannot be easily adjusted or changed.

It is therefore an object of the present invention to provide a PWM modulation circuit capable of easily adjusting and changing the response speed.

It is another object of the present invention to provide a PWM modulation circuit suitable for use in a circuit for smoothing the output of a WM modulation circuit with a low-pass filter and performing D / A conversion.

[0009]

According to the present invention, the bit length of input data is adjusted, the output pulse period is set according to the bit length, and the output pulse is adjusted according to the value of the input data after the bit length adjustment. A PWM modulation circuit having a variable duty is obtained.

According to the present invention, the bit length of the input data is adjusted, and the positive or negative of the output pulse is inverted by an arbitrary value of the output of the counter which is a count number corresponding to the bit length,
When the output of the counter matches the input data after bit length adjustment, the sign of the output pulse is inverted.
A WM modulation circuit is obtained.

According to the present invention, data width adjusting means for adjusting the data width of modulation data in accordance with a data width adjustment control signal, a variable counter whose count number changes in accordance with the data width adjustment control signal, A PWM modulation circuit comprising PWM modulation conversion means for generating a PWM modulation output according to the count number and the adjusted data width is obtained.

[0012] The PWM modulation conversion means includes a zero detector for detecting an initial value of the count number and generating a zero detection signal;
A comparator for comparing the count number with the adjusted data width and generating a comparison result signal; and a P for generating a PWM modulation output according to the zero detection signal and the comparison result signal.
And a WM waveform output device.

It is preferable that the apparatus further includes a data width adjustment control signal generation circuit for generating the data width adjustment control signal in accordance with the modulation data.

The data width adjustment control signal generating circuit compares the modulation data with an integrator for integrating the modulation data, and compares the error data with a predetermined threshold value. It is preferable that the apparatus further includes an additional comparator that compares the result again with the reference data and outputs the result as the control width adjustment control signal.

[0015]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a P according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a WM modulation circuit. This PWM modulation circuit diagram includes a data width adjustment circuit 3 for changing the data width of modulation data 1 composed of a digital signal by amplification or the like in accordance with the data width adjustment control signal 2, and a calculation time according to the data width adjustment control signal 2. Variable counter 5 that can change
And PWM according to the count number and the adjusted data width
And a PWM modulation conversion circuit 4 for generating a modulation output 6.

That is, the PWM modulation data 1 is input to the PWM modulation conversion circuit 4 via the data width modulation circuit 3 and
A modulation output 6 is obtained. At this time, the data width adjustment circuit 3 changes the number of effective bits of the data for PWM modulation in accordance with the data width adjustment control signal 2. The PWM modulation conversion circuit 4 uses the output of the variable count number counter 5 as an index of the modulation pulse period and the inversion operation of the PWM output waveform. The count variable counter 5 changes the count by the data width adjustment control signal 2 in response to the change of the effective bit number of the data width adjustment circuit 3. In the above series of operations, the pulse width of the PWM signal having the variable pulse period is controlled by the control signal 2 without being affected by the total bits of the PWM modulation data 1.
M modulation output 6 can be obtained.

FIG. 2 shows the PWM modulation circuit of FIG. 1 more specifically, and FIG. 3 shows a waveform diagram of the PWM modulation output 6.

In FIG. 2, the PWM modulation data 1 is 8-bit data. Further, the PWM modulation conversion circuit 4 includes a first comparator 11, a zero detector 12, and a PWM waveform output unit 13.

Next, the operation will be described. 8-bit P
The WM modulation data 1 is converted to PWM data via the data width adjustment circuit 3.
Input to the modulation conversion circuit 4 to obtain a PWM modulation output 6. PW
The zero detector 12 in the M modulation circuit 4 generates a zero detection signal when detecting the count initial value “0” of the count data from the count variable counter 5. This zero detection signal is supplied to the PWM waveform output device 13 as a set signal. The PWM waveform output unit 13 performs the setting according to the set signal, and turns the PWM modulation output 6 to the H level. This operation is executed once per one pulse cycle of the PWM modulation waveform, and becomes the starting point of the pulse cycle.

The first comparator 11 compares the signal output of which the effective bit has been adjusted by the data width adjusting circuit 3 with the count data from the counter variable counter 5, and the count data becomes larger. Then, an H-level pulse is output as the comparison result signal. This comparison result signal is supplied to the PWM waveform output device 13 as a reset signal. The PWM waveform output unit 13 performs reset according to the reset signal, and turns the PWM modulation output 6 to L level.

Here, if the data width adjustment circuit 3 adjusts the data width so that the effective bit in the signal output is eight bits, a PWM waveform having one pulse cycle of 256 clocks and a duty ratio of 256 kinds is obtained. Will be obtained.

If the number of valid bits is set to 7 bits, as shown in a waveform 22 in FIG. 3, one pulse period is 128 clocks, and the duty ratio is 128.
If it is set to bits, the pulse period is 6 like the waveform 21 in FIG.
There are 4 clocks and 64 duty ratios. In this way, by sequentially changing the number of effective bits of the data width adjusting circuit 3 and adjusting the count number of the counter 5 in response to the change, the cycle of one pulse can be easily changed.

In FIG. 3, A is an offset binary value, and MBS represents a code. When converted to a binary number, it represents the same value range as B. The first comparator 11 compares the binary values.

Next, as a specific example of a system using the PWM modulation circuit 41 according to the present invention, a QPSK demodulation system is shown in FIG. 4 and will be described in detail.

In FIG. 4, a PWM modulation circuit 41 includes a clock phase detection circuit 39, a loop filter 40, a low-pass filter 34, and a digital-to-analog circuit in a clock recovery loop for QPSK demodulation constituted by a VCO 35 and the like. Used in the signal transfer section.

In general, in QPSK demodulation, there is no signal for synchronization in transmitted data, and a clock is extracted from the state of signal transition. The clock recovery loop plays this role.

The IF input 46 is supplied to the IQ demodulator 31
The signal that has been Q-demodulated and converted to a digital value by the A / D converter 32 is input to the QPSK demodulator 33. QPSK
In the demodulator 33, after passing through the complex multiplier 37 and the roll-off filter 38, the clock phase detector 39 extracts the phase error of the clock, and
After passing through 0, the signal is subjected to PWM modulation and propagated to a low-pass filter 34 connected to a QPSK demodulator 33. After that, the clock signal 42 output from the VCO 35 is
A series of loops is configured by using the clocks of the converter 32 and the QPSK demodulator 33.

When attention is paid to the operational connection of this loop, the output 45 of the PWM conversion circuit has a large influence on the input 43 of its own PWM conversion circuit because of the formation of the feedback loop. Should be able to grasp.

If the above-described loop control is performed with a constant pulse period without using the PWM modulation circuit of the present invention, the circuit shown in FIG.
As shown by the waveform 51, the loop also takes time to stabilize. If it takes a long time to converge, it may oscillate and become unable to converge.

Considering the case where the PWM modulation circuit of the present invention is used, in the initial stage of convergence as shown by the waveform 52 in FIG. 5B, the pulse period is shortened by reducing the number of effective bits to reduce the convergence. It is possible to speed up the operation, increase the number of effective bits when the stable period is reached, and quickly realize a stable loop control such as extending the pulse period.

FIG. 6 is a diagram showing a PWM modulation circuit according to a second embodiment of the present invention. The PWM modulation circuit includes a data width adjustment control signal generation circuit 61 that generates a data width adjustment control signal 2 necessary for adjusting the data width from the modulation data 1, and amplification based on the data width adjustment control signal 2. Modulation data 1 consisting of digital signals
A data width adjustment circuit 3 for changing the data width of the data, a counter circuit 5 for which the calculation time can be changed in accordance with the data width adjustment control signal 2, and a PWM modulation output 6 in accordance with the count number and the adjusted data width. And a PWM modulation / conversion circuit 4 for generating. Here, the data width adjustment signal generation circuit 61 automatically generates the data width adjustment control signal 2 based on the PWM modulation data 1 based on how the signal changes.

FIG. 7 shows an example of the internal configuration of the data width control signal generation circuit 61.

In FIG. 7, the data width control signal generation circuit 6
1 is an integrator 62 and a second comparator (additional comparator) 63
And reference data 64. Integrator 62 uses PW
It integrates the M modulation data 1 to generate an integrated output. The second comparator 63 calculates the integration output from the integrator 62 and P
The data is compared with the WM modulation data 1, the error data is compared again with the reference data 64 which is a preset threshold, and the result is output as the control width adjustment control signal 2.

For example, when the amount of change in the PWM modulation data 1 is large during the unstable period, the data width adjustment control signal generation circuit 61 compares the error data with the reference data 64 and increases the data width. It functions to reduce the data width of the adjustment circuit 3, and conversely, PWM
When the change amount of the modulation data 1 is small, the reference data 64
In comparison with the above, the error data becomes smaller and functions to increase the data width of the data width adjusting circuit 3.

As described above, by including the data width adjustment control signal generation circuit 61, the PWM for automatically changing the pulse period according to the transition state of the PWM modulation data input 1 is provided.
A modulation circuit can be realized.

[0037]

As described above, according to the PWM modulation circuit of the present invention, the pulse period can be easily changed by changing the width of the data used for PWM modulation and the width of the counter. It can be easily changed.

Further, since there is provided a means for observing a transition state of data used for PWM modulation and adjusting a pulse width by comparing with a threshold value, it is possible to automatically change response sensitivity.

In a configuration having a loop in which the PWM modulation output is fed back to the modulation input, quick and stable loop control can be realized. The reason is that, since the pulse period can be changed according to the signal state of the modulation input, efficient PWM modulation in which the pulse period can be changed between the stable period and the transition period to the stable state can be performed. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a PWM modulation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram specifically showing a PWM modulation circuit of FIG. 1;

FIG. 3 is a diagram illustrating an example of a waveform of a PWM modulation output by the PWM modulation circuit of FIG. 2;

FIG. 4 is a diagram showing Q as an application example of the PWM modulation circuit of FIG. 2;
It is a block diagram showing a PSK demodulation system.

5 shows an example of an output waveform of the QPSK demodulation system in FIG. 4; FIG. 5 (a) shows a case where a conventional PWM modulation circuit is used;
(B) The case where the PWM modulation circuit of FIG. 2 is used.

FIG. 6 is a block diagram illustrating a PWM modulation circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a data width adjustment control signal generation circuit included in the PWM modulation circuit of FIG. 6 in detail;

FIG. 8 is a block diagram illustrating an example of a conventional PWM modulation circuit.

FIG. 9 is a diagram illustrating an example of a waveform of a PWM modulation output of the PWM modulation circuit of FIG. 8;

[Explanation of symbols]

Reference Signs List 1 PWM modulation data 2 Data width adjustment control signal 3 Data width adjustment circuit 4 PWM modulation conversion circuit 5 Count variable counter 6 PWM modulation output 12 Zero detector 13 PWM waveform output device 21 PWM when effective bits are 6 bits Modulation output waveform 22 PWM modulation output waveform when effective bits are 7 bits 31 IQ demodulator 32 A / D converter 33 QPSK demodulator 34 Low-pass filter 35 VCO (voltage controlled oscillator) 36 Error corrector 37 Complex multiplication Device 38 roll-off filter 39 clock phase detection circuit 40 loop filter 41 PWM modulation circuit 42 clock signal 43 PWM modulation circuit input 45 PWM modulation circuit output 46 IF input 47 demodulation output 51 The convergence process by the conventional PWM modulation circuit P
WM Modulation Output Waveform 52 P of Convergence Process by PWM Modulation Circuit According to the Present Invention
WM modulation output waveform 61 Data width adjustment control signal generation circuit 62 Integrator 63 Second comparator 64 Reference data 71 Counter 81 PWM modulation output waveform according to conventional example

Claims (6)

[Claims] 1. The method according to claim 1, wherein the bit length of the input data is adjusted, the output pulse period is set according to the bit length, and the duty of the output pulse is made variable according to the value of the input data after the bit length adjustment. PWM modulation circuit. 2. A method for adjusting the bit length of input data, inverting the sign of the output pulse by an arbitrary value of the output of the counter to be a count number corresponding to the bit length, and adjusting the output of the counter and the input data after the bit length adjustment A PWM modulation circuit for inverting the sign of the output pulse when が matches. 3. A data width adjusting means for adjusting a data width of modulation data in accordance with a data width adjustment control signal, a variable counter whose count number changes in accordance with the data width adjustment control signal, A PWM modulation conversion means for generating a PWM modulation output in accordance with the adjusted data width. 4. The PWM modulation and conversion unit detects a count value and an adjusted data width by comparing the count value with the adjusted data width and a zero detector that detects an initial value of the count number and generates a zero detection signal. 4. The PWM modulation circuit according to claim 3, further comprising: a comparator that generates a PWM waveform output device that generates a PWM modulation output according to the zero detection signal and the comparison result signal. 5. The PWM modulation circuit according to claim 3, further comprising a data width adjustment control signal generation circuit that generates the data width adjustment control signal according to the modulation data. 6. The data width adjustment control signal generation circuit,
An integrator for integrating the modulation data, comparing the integration output of the integrator with the modulation data, comparing the error data again with reference data that is a preset threshold, and comparing the result with the control width. 6. The PWM modulation circuit according to claim 5, further comprising an additional comparator that outputs the adjustment control signal.