JPH1056087A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is lessened in operating voltage and where both the writing and erasing of data are carried out through hot carriers. SOLUTION: A source 32a and a drain 32b are provided in a semiconductor layer 32 of polysilicon or the like which is usually used as a control gate for the formation of a MOS. Writing is carried out by ion implantation as usual, and erasing is carried out by canceling electrons inside a floating gate 31 with hot holes generated in the MOS pinch-off region of the semiconductor layer 32, whereby writing/erasing action can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device in which both writing and erasing operations are performed using hot carriers.

[0002]

2. Description of the Related Art Conventionally, in a NOR type flash memory, for example, in data writing, channel hot electrons (CHE) accelerated to a high energy by a drain electric field are applied to a barrier of an oxide film (about 3 eV). ) Is injected into the floating gate electrode. On the other hand, in erasing data, electrons in the floating gate are extracted by utilizing the Fowler-Nordheim (FN) type tunnel phenomenon.

The data erasing using the FN tunnel current consumes a small amount of current per cell and enables erasing at a time for each erase sector. However, the erasing speed per cell is slow and a high electric field of 10 MV / cm is required. For this reason, there is a problem that the operating voltage cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device capable of performing both data writing and data erasing by using a hot carrier and achieving a lower operating voltage.

[0005]

In order to achieve the above object, the present invention provides a floating gate laminated on a substrate surface via an insulating film and insulated from the periphery, and a floating gate provided on the substrate. And a semiconductor layer wired on a floating gate via an insulating film and having a source / drain formed using the floating gate as a gate electrode. Provide equipment.

In this case, the source / drain formed on the substrate is an n-type impurity diffusion layer, and the source / drain formed on the semiconductor layer is a p-type impurity diffusion layer. Further, information is written by injecting hot electrons generated in the substrate into the floating gate to write information, and information is erased by injecting hot holes generated in the semiconductor layer into the floating gate and combined with electrons existing in the floating gate. I do.

In the semiconductor memory device of the present invention, a MOS is formed by forming a source / drain in a semiconductor layer such as polysilicon usually used as a control gate. Writing is performed by hot electron injection as usual, and erasing is achieved by canceling electrons in the floating gate using hot holes generated in the pinch-off region of the MOS in the semiconductor layer, thereby achieving a write / erase operation. It is.

[0008] Therefore, since both writing and erasing use hot carriers, a lower operating voltage can be achieved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below, but the present invention is not limited to the following embodiments. FIG. 1 shows a cross-sectional structure of one embodiment of the semiconductor memory device of the present invention. In the semiconductor memory device 1, for example, a floating gate 31 is provided on a p-type substrate 10 with a gate insulating film 21 interposed therebetween.
1 is a lower gate insulating film 21 and side walls 2
2. It is covered with an insulating film 23 covering the upper part and is insulated from the surroundings. The substrate 10 includes an n-type source 11 connected to a channel formed below the floating gate 31,
A drain 12 is provided. On the floating gate 31, a semiconductor layer 32 made of, for example, polysilicon is wired via an insulating film 23. When the floating gate 31 is used as a gate electrode, impurities are introduced into both sides of a region where a channel is formed in the semiconductor layer 32, so that a p-type source 32a and a drain 3 are formed.
2b is formed. Further, an interlayer insulating film 14 is provided to fill them, and a contact 33 penetrating the interlayer insulating film 14 is connected to the drain 32b of the semiconductor film 32. Note that, in FIG. 1 and FIGS. 3 to 5 illustrating the operation thereof, the semiconductor layer (word line) 3 is shown for convenience of explanation.
2 is wired above the source 11 and the drain 12 formed on the substrate 10, but the semiconductor layer 32 is actually orthogonal to the paper surface and does not overlap with the source 11 and the drain 12 of the substrate 10.

The semiconductor memory device 1 includes an n-type source 11 and a drain 1 in which a semiconductor layer 32 is formed on a substrate 10.
It functions as a second gate electrode and corresponds to a control gate, and an NMOS is formed on the substrate. In addition, the floating gate 31 functions as a gate electrode for the p-type source 32a and the drain 32b formed in the semiconductor layer 32 that normally functions only as a control gate, and the semiconductor layer 32 includes a PMOS. ing. Thus, the present semiconductor memory device 1
The structure is such that both the OS and the PMOS are configured in one cell.

FIG. 2 shows an example of a cell configuration of a semiconductor memory device having such a memory cell. This cell configuration is NOR
Type cell configuration, in which one memory cell has an NMOS formed on a substrate and a PM formed on a semiconductor layer.
OS, and has a floating gate FG. The drain D of the NMOS is connected to the bit lines BL1 and BL2, and the source S is connected to GND. Also,
The drain D of the PMOS is connected to the word lines WL1 and WL2, and the source S is connected to the lines L1 and L2.

The writing, reading, and erasing operations of the cell 21 shown in FIG. 2 will be described below with reference to FIGS. The following FIGS. 3 to 5 correspond to FIG. 1 and are simplified diagrams. As shown in FIG. 3, for example, as shown in FIG. 3, for example, 8 V is applied to each of the word line WL1 and the line L1 to apply 8 V to both the source PS and the drain PD of the semiconductor layer CG. 8V is supplied to the gate (CG). In this case, a positive voltage is applied to the gate electrode (semiconductor layer) as viewed from the NMOS formed on the substrate. Further, as in the conventional case, for example, 4 V is applied to the drain ND of the NMOS,
0 V is supplied to the source NS of the NMOS.

As a result, some of the electrons accelerated in the pinch-off region near the drain become hot electrons, and the hot electrons are injected into the floating gate to perform writing. Since the floating gate is insulated from the surroundings, the injected electrons are captured. When the electrons are captured by the floating gate, the threshold value of the NMOS formed on the substrate rises, and the presence or absence of the change in the threshold voltage is determined by the information “1”.
Corresponds to the “0” level.

On the other hand, although 8 V is applied to the semiconductor layer (control gate) of the cell 11, no voltage is applied to BL1, so that electron injection does not occur. Further, since no voltage is applied to the semiconductor layer (control gate) of the cell 22, electrons are not injected into the floating gate of the cell 22.

For reading, as shown in FIG. 4, for example, 5 V is applied to both the word line WL1 and the line L1 and P is applied.
5V is supplied to each of the source PS and the drain PD of the MOS. Further, for example, 1 V is applied to the bit line BL2 to
1 V is supplied to the drain ND of the MOS. As shown in FIG. 4, when electrons are captured by the floating gate FG, the threshold value increases, so that the NMOS is turned off and no read current flows. On the other hand, floating gate FG
If no electrons are injected into the NMOS, the NMOS turns on and a read current flows. The voltage drop due to the read current is detected by a sense amplifier connected to the drain electrode (bit line BL) and output.

On the other hand, 5 V is also applied to the semiconductor layer (control gate) of the cell 11 shown in FIG.
Since no voltage is applied to L1, it is not read. Although 1 V is applied to the bit line BL2 of the cell 22 and 1 V is supplied to the drain, no reading is performed since no voltage is applied to the control gate.

In erasing, as shown in FIG. 5, when electrons are injected into the floating gate FG, a negative potential is applied to the gate electrode (floating gate) viewed from the PMOS formed in the semiconductor layer. The PMOS is turned on. Word line WL of semiconductor layer
For example, -5 V is applied to 1 to supply -5 V to the drain PD of the PMOS, and 0 V is applied to the source PS of the PMOS. Further, 0 V is applied to the bit line BL2, 0 V is supplied to the drain ND of the NMOS, and the source NS of the NMOS is supplied.
Is applied with 0V.

As a result, some of the holes accelerated in the pinch-off region near the drain become hot holes, which are injected into the floating gate FG and combined with the electrons in the floating gate FG to combine with the electrons in the floating gate FG. The electrons in the FG are canceled, and the threshold value of the memory cell is shifted toward the initial value. When the number of electrons in the floating gate FG decreases, the absolute value of the voltage of the floating gate FG decreases, so that a channel is hardly formed and a hot hole is hardly formed. As a result, excessive hot holes are not injected.

When no electrons are injected into the floating gate, no voltage is applied to the gate electrode (floating gate) as viewed from the PMOS, so that no channel is formed in the semiconductor layer and hot holes are generated. do not do. Therefore, holes are not accidentally injected into the floating gate.

On the other hand, in the cell 11, the PMOS of the semiconductor layer
, But no voltage is applied to the NMOS of the substrate, so that hot holes are not injected into the floating gate. In the cell 22, the NMOS
, No voltage is applied to the drain and no voltage is applied to the PMOS, so that hot holes are not injected into the floating gate.

As described above, the semiconductor memory device of the present invention
By configuring both the NMOS and the PMOS in one cell, electron injection and hole injection into the floating gate can be generated in the pinch-off region, so that low voltage operation becomes possible. Next, a method of manufacturing the semiconductor memory device having the structure shown in FIG. 1 will be described with reference to FIG. FIG. 6 shows an original structure in which the semiconductor layer (word line) extends in a direction perpendicular to the paper surface.

The steps leading to the structure shown in FIG. 6A will be described. An element isolation insulating film (not shown) is formed on the surface of the substrate 10 according to a conventional method, and then a gate insulating film made of silicon oxide by a thermal oxidation method or the like. 21 is formed to a thickness of, for example, about 10 nm. Next, after depositing polysilicon, patterning is performed to form a floating gate 31.

Subsequently, as shown in FIG. 6B, an n-type impurity such as phosphorus is ion-implanted to form an LDD. Then, after depositing an oxide film by CVD or the like, the sidewall 22 is formed on the side of the floating gate 31 by etching back. Further, an n-type impurity is ion-implanted to form a source / drain. The conditions of the ion implantation at this time are, for example, P, energy 10 k
eV, dose amount is about 3 × 10 ¹⁵ / cm ³ .

Next, a silicon oxide film 23 is formed as an insulating film to a thickness of about 15 to 20 nm so as to cover the floating gate, for example, by CVD. This silicon oxide film 23 is used as a PMOS gate insulating film. Then, polysilicon or the like is deposited for 100 to 2 by CVD or the like.
The film is formed with a thickness of about 00 nm. After that, for example, a resist is patterned according to the shape of the floating gate to form the semiconductor layer 32. Thereafter, BF ₂ is ion-implanted using a resist covering a region corresponding to the floating gate as a mask to form a PMOS source 32a and a drain 32b. The conditions of the ion implantation at this time are: energy: 20 keV, dose: 3 × 10 ¹⁵ / cm
^{About three} .

Thereafter, as shown in FIG. 1, after depositing an interlayer insulating film, a contact hole is formed, an aluminum film is formed, and patterning is performed to form a word line 33, thereby forming the structure shown in FIG. Can be obtained. The semiconductor memory device of the present invention is not limited to the above-described embodiment. For example, in the above-described embodiment, the example in which the present invention is applied to the NOR type is described. However, it is needless to say that the present invention can be applied to other cell structures. In addition, various changes can be made without departing from the spirit of the present invention.

[0026]

According to the semiconductor memory device of the present invention, since the data writing and erasing operations use the hot channel, a low voltage can be achieved for both writing and erasing.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is an equivalent circuit diagram illustrating one embodiment of a cell structure of a semiconductor memory device of the present invention.

FIG. 3 is a schematic diagram illustrating a write operation of the semiconductor memory device of the present invention.

FIG. 4 is a schematic diagram illustrating a read operation of the semiconductor memory device of the present invention.

FIG. 5 is a schematic diagram illustrating an erasing operation of the semiconductor memory device of the present invention.

FIGS. 6A to 6C are cross-sectional views each showing a manufacturing process of the semiconductor memory device of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... board | substrate, 11 and 12 ... source / drain, 21 ... gate insulating film, 22 ... sidewall, 23 ... insulating film, 3
1: floating gate, 32: semiconductor layer, 32a ...
Source, 32b drain, FG floating gate, L1, L2 line, WL1, WL2 word line,
PD: PMOS drain, PS: PMOS source,
ND: NMOS drain, NS: NMOS source

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/115

Claims (3)

[Claims] A floating gate laminated on a substrate surface via an insulating film and insulated from surroundings; a source / drain formed on the substrate corresponding to the floating gate; And a semiconductor layer in which a source and a drain are formed using the floating gate as a gate electrode, and a semiconductor layer wired through a film. 2. The semiconductor memory according to claim 1, wherein the source / drain formed on the substrate is an n-type impurity diffusion layer, and the source / drain formed on the semiconductor layer is a p-type impurity diffusion layer. apparatus. 3. The information is written by injecting hot electrons generated in the substrate into the floating gate.
2. The semiconductor memory device according to claim 1, wherein information is erased by injecting hot holes generated in said semiconductor layer into said floating gate and combining them with electrons existing in said floating gate.