JPH1051322A - Error correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction device in which an error including a burst error is efficiently corrected. SOLUTION: A de-interleave buffer section 2 outputs a signal W1 in which interleaving is released. In a first correction stage, the signal W1 passes an exclusive OR arithmetic section 11 as it is and the error is corrected by an error correction section 3. In the case of correcting the error, an error location estimate section 13 counts number of times of errors for each correction position and when correction is disabled, a timing control section 14 stores it address. When any error is detected in a slot, a de-interleave buffer section 2 outputs again data of the slot. The error location estimate section 13 identifies the correction position having a highest correction number of times and the timing control section 14 allows the exclusive OR arithmetic section 11 to correct the corrected position when the current address is coincident with the stored address. The error correction section 3 corrects the error of the signal W2 after the correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device for correcting an error in a data string received via a transmission line,
In particular, when transmitted on a transmission path, for example, a slot,
The present invention relates to an error correction device for correcting an error in a data string to be subjected to an interleaving process for changing the transmission order for each predetermined element such as each bit within a predetermined range.

[0002]

2. Description of the Related Art In a digital communication system such as a digital cellular phone system, for example, bit interleave processing, BC
Various protection means such as an H (Bose-Chaudhuri-Hocquenghem code) code and a CRC (Cyclic Redundancy Check) parity check code are applied. Here, as an example of a conventional digital communication system, a data communication system employed in a time-division multiple access (TDMA) digital mobile phone system will be briefly described.

[0003] In other words, the transmitting apparatus divides information to be transmitted for each predetermined length and adds a CRC code to form a slot. Further, a data sequence forming a slot is encoded using a BCH code. Further, when transmitting the data sequence, the transmitting device uses a bit interleaving process to change the order for each bit in each slot and then sequentially transmits the data sequence. On the other hand, the receiving apparatus rearranges the order of the received bit strings to the original order by de-interleaving. After the data sequence generated by this process is error-corrected by BCH decoding, it is detected by a CRC parity check whether or not there is an error.

In the above data transmission method, even when a burst error occurs in the transmission path, the bit in which the error has occurred is distributed to each codeword by de-interleaving. This allows the receiving apparatus to correct the burst error by BCH decoding, as in the case where a random error has occurred.

[0005] If an error that exceeds the correction capability of the BCH code occurs in the transmission path, the error is detected in the CRC parity check. In this case, the receiving device sends a request for retransmission of the slot to the transmitting device, and the transmitting device retransmits the slot based on the request. When the slot is retransmitted, the receiving device invalidates the previously received slot and repeats the above-described processing such as error correction on the newly received slot. The transmitting device and the receiving device repeat the same processing until error-free data is obtained, so that the transmitting device can transmit accurate data to the receiving device.

[0006]

However, in the above-described conventional error correction method, the generated burst error spreads in the slot as a random error. Therefore, when a random error further occurs in the slot, there is a very high possibility that the error correction capability of the BCH code or the like will be exceeded. As a result, a retransmission request is frequently generated, which causes a problem that the transmission path cannot be used effectively.

[0007] In particular, in a digital communication system such as a digital cellular phone that uses radio as a transmission path, the quality of the transmission path frequently changes as the mobile phone moves. Therefore, compared to other digital communication systems using a wired or the like, the frequency of burst errors is high,
The effect of the above problem is extremely large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to efficiently remove an error including a burst error without retransmitting data when a burst error occurs in a transmission path. An object of the present invention is to provide an error correction device that can correct the error.

[0009]

In order to solve the above-mentioned problems, an error correction apparatus according to the first aspect of the present invention provides a de-interleave means for deinterleaving a plurality of codewords which are interleaved and transmitted on a transmission line. And an error correction unit that decodes each code word and corrects the error, characterized in that the error correction device includes the following units.

That is, an error position estimating means for estimating an error position caused by a burst error for a code word for which an error cannot be corrected based on a correction position of a code word correctly corrected by the error correcting means; A correction means is provided which corrects the estimated position estimated by the error position estimating means for a code word which could not be corrected at the time of error correction, and then sends the corrected word to the error correcting means again.

[0011] In the above configuration, the de-interleaving means deinterleaves the received data sequence, and converts a plurality of codewords transmitted on the transmission path after the interleaving into:
Restore to original codeword. Thus, when a burst error occurs in the transmission path, the bits in which the burst error has occurred are distributed to the respective codewords in accordance with the method adopted by the de-interleaver for deinterleaving. For example, in each codeword, when bits at a specific bit position are collected and continuously transmitted, the de-interleaving means sequentially arranges a bit string received at a specific bit position of each codeword, , The received bit string is sequentially arranged at the next bit position.

The error correction means decodes each of the interleaved codewords using, for example, BCH (Bose-Chaudhuri-Hocquenghem code) decoding, and performs error correction. By using the de-interleaving process and the error correction together, the error correction device can correct the error even when a burst error occurs on the transmission path. For example, when decoding an extended BCH (8,4) code, the error correction means determines whether the error occurred in each codeword is due to a burst error or a random error. If it is a single error, the error can be corrected, and if it is a double error, it can be detected.

Incidentally, burst errors occur continuously in the transmission path. Therefore, an error occurring in another codeword due to a series of burst errors can be estimated from the error occurring in the codeword due to the burst error and the processing method of the de-interleaving means. For example, when the de-interleaving means sequentially arranges the received bit string at a specific bit position of each codeword as described above, errors due to burst errors concentrate on a specific bit position.
Therefore, in this case, the error position estimating means can estimate the error position of another codeword caused by the burst error from the correction position where the number of corrections is large. When the error position estimating unit estimates the error position, the correcting unit corrects the estimated position of the codeword. Further, the corrected codeword is sent to error correction means, where the error is corrected.

Therefore, when the codeword used in calculating the estimated position and the codeword before correction include an error caused by a series of burst errors, the correction means sends the codeword to the error correction means. , The error of the code word can be reduced. Therefore, the error correction means can correct the error of the code word that could not be corrected at the time of the first correction at the time of re-correction. Since the correction capability of the error correction means can be improved, the frequency of occurrence of retransmission requests can be reduced, and the utilization efficiency of the transmission path can be improved. In addition, since the interleaving method and the encoding method are the same as those in the related art, it is not necessary to change the device on the transmission side to improve the utilization efficiency of the transmission path.

According to a second aspect of the present invention, in the configuration of the first aspect of the present invention, the de-interleaving means is configured to transmit each of the codewords when each of the codewords is transmitted through a transmission path. When a plurality of elements constituting a word are collected and transmitted for each position in each codeword, the interleaving is solved by changing the order of the respective elements, and the error position estimating means includes the error correcting means. A counter that counts the number of error corrections for each correction position of each codeword, and a correction position with the highest correction frequency is selected based on the count value of each counter, and is instructed to the correction means as the estimated position. And a sorting means.

[0016] In the above configuration, the transmitting device is, for example,
As in the interleaving method used in digital mobile phone systems, each codeword is divided for each element such as a bit, and is collected and transmitted for each element at a specific position.
The de-interleaving means changes the order of the data received via the transmission path for each element and restores the original codeword.

On the other hand, the error position estimating means is provided with a counter corresponding to each correction position of the code word. When the error correcting means corrects a codeword error, the count value of the counter corresponding to the correction position changes, for example, by incrementing by one. The selection unit selects a correction position with the highest correction frequency based on the count value of each counter. For example, when each counter is an up counter, the counter having the largest count value corresponds to the most frequent correction position. Further, the selection unit instructs the correction unit to use the corrected position as the estimated position.

When the above interleave method is adopted,
When a series of burst errors occur in the transmission path, the de-interleaving means distributes the erroneous elements to specific positions of each codeword. Therefore, the selection unit can estimate the error position based on the count value of each counter. Further, each of the counters and the sorting means may be, for example,
Binary counter, maximum value selection circuit, decoder, etc.
It can be realized with a simple configuration. As a result, it is possible to realize an error correction device corresponding to the interleave method with a simple configuration.

Further, in the error correction device according to the third aspect of the present invention, in the configuration of the second aspect, each of the counters resets, for example, the count value to 0 for each slot serving as a transmission unit. , And the count value is initialized.

By the way, when the interval for initializing the count value is shortened, the count value of each counter, that is, the number of times the error correction means corrects an error, decreases. Further, the ratio of random errors included in each count value increases.
As a result, the sorting means may incorrectly estimate the error location,
Alternatively, there is a possibility that estimation cannot be performed. On the other hand, if the interval is longer than the length of the slot, burst errors that occur in other slots and are not related to the slot are also counted. As a result, the accuracy of error position estimation also decreases.

In the above configuration, since the count value is initialized for each slot, the accuracy of the error position estimating means for estimating the error position can be further improved, and the utilization efficiency of the transmission path can be further improved.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
7 is as follows. That is, the error correction device according to the present embodiment includes a digital device including a transmitting device such as a base station and a receiving device such as a mobile phone, such as a digital mobile phone system of a time division multiple access system (TDMA system). It is provided to a receiving device of a communication system and is used for correcting an error in received data.

In the digital communication system according to the present embodiment, the transmitting device divides information to be transmitted for each predetermined size, and uses, for example, a CRC (Cyclic Redundancy Check) code or the like to divide each data sequence. Is added to the bits for error detection. Further, the transmitting device is, for example, a BC
Using a Hose (Chosehuri-Hocquenghem code) code or the like, an error correction code is applied to the data sequence to which the error detection code is added. After that, the bit sequence generated by the error correction encoding is transmitted to the transmission line with the order changed for each bit in the slot. As a result, even if a burst error occurs in the transmission path, the bit string in which the error has occurred is distributed to each codeword, so that the receiving apparatus can correct the error as in the case where a random error has occurred.

Hereinafter, the case where the following codes are used will be described as an example of the error detection code and the like.
That is, the data length per slot is set to 10 bytes, and each slot is formed by adding a CRC check bit of 2 bytes (16 bits) serving as an error detection code to 8 bytes of information. Thereby, the receiving device can detect an error. Therefore, as shown in FIG. 4B, each slot has a slot start address of N.
Then, each byte is composed of one byte of data B corresponding to each of the addresses N to N + 9.

In the present embodiment, an extended BCH (8, 4) code is used as an error correction code. As shown in FIG.
Is divided into upper 4-bit data BH and lower 4-bit data BL.
H and WL (generally referred to as W). Thus, a one-bit error can be corrected for each codeword W and a two-bit error can be detected. Note that FIG. 4 shows slots received by the receiving apparatus, as described later. Therefore, in the code word W and the data B, a burst error or a random error generated in the transmission path is displayed as an x mark. I have.

Further, in the bit interleaving process employed in the digital communication system according to the present embodiment, when transmitting a bit string of one slot, bits at the same position in each codeword W are collected and transmitted. Therefore,
For example, bits at a specific position for each codeword, such as the most significant bit in each codeword W, are continuously transmitted. As a result, if a burst error occurs during transmission, the bit in which the error has occurred is distributed to each codeword W. Further, in this case, the error position caused by a series of burst errors is the same between each codeword W.

As shown in FIG. 1, an error correction device 1 according to the present embodiment includes a de-interleave buffer unit (de-interleave means) 2 for deinterleaving received data, and a de-interleaved data sequence. An error correction unit (error correction means) 3 for correcting errors for each code word, an error detection unit 4 for detecting whether or not there is an error in the error-corrected data sequence for each slot, and controlling the entire error correction device 1 And a CPU (Central Processing Unit) 5.

The de-interleave buffer unit 2 comprises:
For example, a random access memory (RAM) is provided, and a bit string received from a transmitting device (not shown) is
At least one slot can be held. Also,
The interleaving is canceled by changing the order of the received bit string in a predetermined order, and the interleaved codewords W can be transmitted in parallel according to the address signal Aa provided from the CPU 5. As described above, each address corresponds to an 8-bit code word WH · WL. Therefore, the de-interleave buffer unit 2 outputs 8-bit width signals W1H and W1L (generally referred to simply as W1) corresponding to each address. Further, the de-interleave buffer unit 2 according to the present embodiment can update the content of the code word W stored at a desired address according to an instruction from the CPU 5.

As described above, in the bit interleaving method according to the present embodiment, bits at specific positions in each codeword W are collected. Therefore, in the de-interleave buffer unit 2 according to the present embodiment, for example, a RAM having mesh memory cells is used.
Bit strings are sequentially accumulated along one direction of the cells.
Furthermore, when accessing the RAM in parallel, such as when sending data to the error correction section 3, memory cells along other directions are accessed in parallel. As a result, the deinterleave buffer unit 2 which is relatively high speed and has a small circuit scale can be realized.

Further, the error correction unit 3 performs the extended BCH
(8, 4) Error correction circuits 7.7 for decoding codes are provided. Each error correction circuit 7 outputs a signal indicating a code word WH or WL having an 8-bit width from the de-interleave buffer unit 2 through an exclusive OR operation unit (hereinafter referred to as an EXOR unit) 11 described later. W2H or W2
L and the upper data BH or lower data BL
Can be decrypted respectively. Thereby, each code word WH
If a 1-bit error has occurred in WL,
Correction can be made normally, and if a two-bit error has occurred, it can be detected that there was an error. Both error correction circuit 7
Are transmitted in parallel to the error detection unit 4 and the CPU 5 as 8-bit data B in total.

Further, the error correction circuit 7 according to this embodiment
Can correct the single error of each codeword W and output a correction position signal E1 indicating the correction position. In this embodiment,
As shown in FIG. 4A, it has a 4-bit data part D, and the correction position signal E1 changes when the corresponding bit is corrected.
Consists of Therefore, for example, it is possible to determine whether or not the bit at the corresponding position has been corrected, based on the signal level of each of the correction position signals E1a to E1d. When counting from the most significant bit of the data portion D, the first bit corresponds to the correction position signal E1a, and the second to fourth bits correspond to the correction position signals E1b to E1d.

In addition, the error correction circuit 7 can output a double error detection signal E2 indicating whether a double error has been detected in each codeword W. When correcting an error, the conventional error correction circuit 7 also calculates which position to correct and whether or not an error has been detected. Therefore, a circuit that outputs the correction position signal E1 and the double error detection signal E2 can be easily realized by combining, for example, a logic circuit and the like.

The error detection unit 4 is provided with the error correction unit 3
Receives each data B after error correction, and detects an error for each slot by using a CRC parity check.
In the digital communication system according to the present embodiment, since the 2-byte CRC parity code is added to the 8-byte information, the error detection unit 4 can detect an error. Upon detecting an error, the error detection unit 4 can send an error detection signal E indicating that the error has been detected to the CPU 5.

On the other hand, when the error correction device 1 processes each code word W in the slot, the CPU 5 can instruct the de-interleave buffer unit 2 the address to be processed at present. In addition, by transmitting the read signal R, the operation timing can be instructed to each member of the error correction device 1 such as the error detection unit 4. Further, in the present embodiment, when the error detection signal E is received from the error detection unit 4, the de-interleave buffer unit 2
, The address signal Aa indicating the slot can be sent again. As a result, the error correction device 1 can retry the error correction for the received slot. When the error detection unit 4 detects an error after re-correction, the CPU 5 requests a transmission device (not shown) to re-transmit the slot.

Further, in the present embodiment, an exclusive OR operation is provided between the de-interleave buffer unit 2 and the error correction unit 3 so that the signal W2 after correcting the signal W1 can be sent to the error correction unit 3. Section (EXOR section) 11 and the EX
A control unit 12 for applying a correction signal S indicating a correction location to the OR unit 11 is provided. The control unit 12 corrects the correction position signal E1 given from the error correction unit 3 at the time of the first correction.
Error position estimating unit 13 for estimating the error position of code word W that could not be corrected based on the above, and when processing code word W that could not be corrected at the first time during re-correction, error position estimating unit 13 Timing control unit 1 for transmitting error position signal Y to be output to EXOR unit 11 as correction signal S
4 is provided. Note that the EXOR unit 11 corresponds to the correcting unit described in the claims, and the error position estimating unit 13 corresponds to the error position estimating unit.

Thus, when an error is detected in the received slot, the error correction device 1 determines the error position estimated at the first error correction for the data of the slot stored in the de-interleave buffer unit 2. After correction, error correction can be attempted again. As a result,
If it is possible to predict an error that could not be corrected from another codeword in the slot, such as when a burst error has occurred, the error can be predicted without requesting the transmitting apparatus to retransmit the slot. Can be corrected. The above EXOR
The unit 11, the error position estimating unit 13, and the timing control unit 14, as in the error correction circuit 7, also
And two for the lower data BL.

As shown in FIG. 2, the error position estimator 1
Numeral 3 denotes counters 21a to 21d for counting the respective pulse numbers based on the correction position signals E1a to E1d applied by the error correction circuit 7 during the first correction (referred to collectively as 21). And comparators 22a to 22c for outputting a signal Y indicating the counter having the highest count value among the counters 21, and a selector 23a corresponding to the selecting means described in the claims.
And 23b, and a decoder 24.

The comparator 22a includes a counter 21
a and the count value Cb of the counter 21b
And when Ca ≧ Cb, the high-level signal X
a (Xa = 1) can be output. On the other hand, when Ca <Cb, the comparator 22a outputs the low-level signal Xa (X
a = 0) is output.

Further, the selector 23a can output, as the signal Va, the larger one of the count value Ca of the counter 21a and the count value Cb of the counter 21b based on the signal Xa. Specifically, when Xa = 1, the selector 23a outputs the count value Ca,
When Xa = 0, the count value Cb is output.

Similarly, the comparator 22b compares the count value Cc of the counter 21c with the count value Cd of the counter 21d, and outputs Xb = 1 if Cc ≧ Cd, and outputs Xb = Cc <Cd. 0 signal can be output.
The selector 23b can output the count value Cc as the signal Vb when Xb = 1, and can output the count value Cd when Xb = 0.

Further, the comparator 22c can compare the output Va of the selector 23a with the output Vb of the selector 23b and output a signal Xc indicating which is larger.
Specifically, when Va ≧ Vb, Xc is 1, and Va is Va.
In the case of <Vb, Xc is 0.

On the other hand, the decoder 24 determines the counter 21 having the largest count value among the counters 21 based on the outputs Xa to Xc of the comparators 22a to 22c, and determines the highest correction frequency in the slot. A signal Y indicating the corrected correction position, that is, the estimated error position, can be output.

For example, when the error correction unit 3 corrects the first bit most frequently in the slot, the (1000) correction position signal E1 is output most frequently in order from the first bit. Therefore, the counter value Ca of the counter 21a becomes larger than the count values of the other counters 21. As a result, each of the comparators 22a to 22c
Output signals Xa, Xb, and Xc all become 1. In this case, the decoder 24 outputs the signals Xa to Xc
, And outputs a signal Y of (1000) in order from the most significant bit. Similarly, the decoder 24 outputs (0100) when the counter 21 having the largest count value is the counter 21b, and outputs (0010) or (0001) as the signal Y when the counter 21c or 21d is the counter 21b. Are output.

On the other hand, the timing control unit 14 performs the EXOR unit 1 shown in FIG. 1 only when re-correcting and processing an address that could not be corrected during the first correction.
1, the signal Y is transmitted as the correction signal S. More specifically, for example, as shown in FIG. 3, the timing control unit 14 generates an address buffer 31 for storing an address that could not be corrected and a timing for storing the address at the time of the first correction. An AND circuit 32,
An all match circuit 33 for determining whether each address stored in the address buffer 31 matches the address currently being processed, and an all match circuit 33.
And an AND gate 35 for passing the signal Y only when instructed by the OR circuit 34.

The address buffer 31 stores, for example, R
It is composed of an AM, a register, and the like, and can store each address when a double error occurs in one slot. The storage capacity of the RAM or the like is set such that all addresses where a double error has occurred in one slot, such as one slot, can be stored. The address buffer 31 is reset to 0 for each slot,
Each time the ND circuit 32 indicates a timing, the current address signal Aa can be stored. Further, each address stored in the address buffer 31 is stored in the corresponding all match circuit 3.
3 respectively.

The AND circuit 32 ANDs the double error detection signal E2 and the read signal R of the CPU 5 to generate the read timing of the address buffer 31. As shown in FIG. 5, the double error detection signal E2 becomes one level only when the error correction unit 3 detects a double error during the first correction by the error correction unit 3. Also,
The read signal R changes only when the address signal Aa is stable. Therefore, by accumulating the address signal Aa at the timing indicated by the logical product of the two, the address buffer 31 can stably take in the address.

On the other hand, the all match circuit 33 compares the address Ab applied from the address buffer 31 with the address Aa currently being processed, and outputs a one-level signal only when all bits are the same. it can. All match circuit 33
The number of addresses is, for example, even if the largest number of addresses, such as for one slot, are stored in the address buffer 31,
It is set so that it can be determined whether or not the current address is an address stored in the address buffer 31.

Thus, at the time of re-correction, the CPU 5
Only when the sequentially applied address signal Aa is the same as any of the addresses stored in the address buffer 31, the AND gate 35 is opened, and the signal Y estimated by the error position estimating unit 13 is converted to the EXOR unit 11. Can be conveyed to. Since the address buffer 31 is reset to 0 at the time of the first correction, each of the all match circuits 33 is reset.
Does not detect a full match no matter what address is applied.

Here, as an example of the operation of the error correction device 1, a case of processing the data shown in FIG. 4 will be described. A code word W shown in FIG. 4A indicates a signal W2 input to the error correction unit 3, and an error occurrence position is indicated by a cross. In this example, due to the burst error,
An error mainly occurs in the third bit of the data part D. In the following, for convenience of description, the description will be focused on the processing for decoding the upper data BH in each codeword W, and the description of the lower data BL that performs the same processing will be omitted.

As shown in FIG. 5A, the CPU 5
Address signals Aa from N to N + 9 are sequentially transmitted. Based on this, the de-interleave buffer unit 2
Outputs a signal W1H in synchronization with each address, as shown in FIG. Address buffer 3 shown in FIG.
1 is reset to 0 for each slot. Therefore, at the time of the first correction, the control unit 12 controls the EXOR unit 1
1 is not instructed to correct. As a result, the signal W1H becomes
The signal is transmitted as it is to the error correction unit 3 as a signal W2H.

The error correction circuit 7 corrects the error for each address, and as shown in FIG.
Is output. Since the error correction circuit 7 can correct a single error, the address where the single error has occurred, that is,
In N, N + 2, N + 3, N + 4, N + 6, and N + 9, the error of the upper data BH has been corrected to be correct data. Further, when the error can be corrected, the CPU 5
Corrects the data in the de-interleave buffer unit 2 in accordance with an instruction from the error correction circuit 7.

When correcting a single error, the error correction circuit 7 outputs a correction position signal E 1 indicating a correction position to the error position estimating unit 13. Error position estimator 1 shown in FIG.
In 3, the counters 21a to 21d are reset to 0 for each slot, and count the number of corrections for each correction position. Therefore, as shown in (e) to (h) of FIG. 5, the count values Ca to Cd of each counter 21 are:
The number of corrections at the corresponding correction position in the slot is shown.

For example, the error correction circuit 7 corrects the fourth bit at N + 3 among the above addresses. Therefore, as shown in FIG.
Outputs (0001) as the correction position signal E1 at the address. At the address of N + 3,
Since the correction position signal E1d changes, the count value Cd of the counter 21d becomes N + 3, as shown in FIG.
Is 0 at the time before the address No. 1, and changes to 1 after the address N + 3.

The error correction circuit 7 corrects the third bit in the remaining addresses among the above addresses. Therefore, as shown in FIG. 5D, for each of the addresses, (0010)
Is output. As a result, as shown in FIG.
The count value Cc of the counter 21c increases for each address. As a result, the count value Cc is 5 at the time when the processing for one slot is completed (at the time when the processing for the address of N + 9 is completed).

In the slot shown in FIG. 4A,
No single error has occurred in the first and second bits of the codeword WH. Therefore, error correction circuit 7 does not output correction position signals E1 (1000) and (0100). As a result, as shown in FIGS. 5E and 5F, the count value Ca of the counter 21a and the count value Cb of the counter 21b are always 0.

On the other hand, as shown in FIG. 5B, a double error has occurred at the addresses N + 1, N + 5, and N + 8 in the slot. The error correction circuit 7
Since the double error cannot be corrected, an error remains at the address in the upper data BH as shown in FIG. 5C. At the address, the correction position signal E
1 is set to (0000) or the like, or the correction position signal E
1 is prevented from being transmitted to the counters 21a to 21d (indicated by **** in FIG. 5D). Thus, as shown in FIGS. 5E to 5H, the count values Ca to Cd are kept constant.

Further, if a double error has occurred, the error correction circuit 7 sends a double error detection signal E2 to the timing control section 14, as shown in FIG. On the other hand, as shown in FIG. 5 (j), the CPU 5 sends the read signal R while the address signal Aa is stable in order to instruct the error detection unit 4 and the like on the timing of data processing.
Is changing. The AND circuit 32 calculates the logical product of the double error detection signal E2 and the read signal R,
It is possible to generate a signal that falls while the double error detection signal E2 is at one level and the address signal Aa is stable. The address buffer 31 sequentially stores the address values when the signal falls. As a result, N + 1, N + 5 and N + are stored in the address buffer 31 at the time when the first correction is completed, as shown in FIG.
8 are stored.

The same processing is performed on the lower data BL, and the error correction circuit 7 outputs the data B containing the error as shown in FIG. 4B. The data B
Is output to the error detection unit 4 and the CPU 5. In this case, the error detection unit 4 detects that an error has occurred in the slot, and outputs an error detection signal E. As a result, the CPU 5 instructs an address to the de-interleave buffer unit 2 to output the data of the slot again. Thereby, the error correction device 1 can try to correct the data again.

Specifically, at the time of re-correction, as shown in FIG. 6A, the CPU 5 sequentially applies addresses from N to N + 9 as the address signal Aa. The address buffer 31 outputs, to the corresponding all-matching circuit 33, each address Ab... That could not be corrected by the error correction circuit 7 at the time of the first correction, as shown in FIG. . Further, the all-match circuit 33 determines whether or not the given address signal Aa matches the current address signal Aa. Therefore, when the address is N + 1, N + 5, or N + 8, the output of the corresponding all matching circuit 33 becomes 1. Further, the OR circuit 34
Calculates the gate signal G by the logical sum of the all matching circuits 33. As a result, as shown in FIG. 6C, the gate signal G becomes 1 at each of the above addresses.

On the other hand, as shown in (e) to (h) of FIG. 5, when the first correction is completed, the count values Ca to Cd of the counters 21 are 0,
0, 5, and 1. As a result, the comparator 22
a outputs a signal Xa = 1 indicating Ca ≧ Cb.
Also, based on this, the selector 23a outputs the output signal V
The count value Ca is output as a. Similarly, the comparator 22b outputs a signal Xb = 1 indicating Cc ≧ Cd, and the selector 23b outputs a count value Cc as an output signal Vb. Further, the comparator 22c
Compares the signal Va with the signal Vb and indicates a signal X indicating that Va <Vb.
Outputs c = 0. The decoder 24 has 1, 1,.
The signals Xa to Xc indicating 0 are decoded, and the signal Y = (0010) indicating the correction position with the largest number of times is selected. During re-correction, since the correction position signal E1 is not input, each count value does not change. Therefore, as shown in FIG. 6D, the error position estimating unit 13 outputs the signal Y =
(0010) is always output.

As shown in FIG. 3, the timing control unit 14
The AND gate 35 passes the signal Y only when the gate signal G shown in FIG.
Output as As a result, as shown in FIG. 6E, the EXOR unit 11 shown in FIG. 1 applies the correction signal S (0010) to the EXOR unit 11 only during a period in which an address whose error could not be corrected at the first correction is applied. Is entered. In the remaining period, since the timing control unit 14 blocks the signal Y, the correction signal S is (0000) indicating that there is no corrected portion.

The EXOR unit 11, as shown in FIG. 6 (f), receives the signal W1H output from the de-interleave buffer unit 2 in synchronization with the address and the correction signal S shown in FIG. 6 (e). Signal W2 calculated by taking the exclusive OR of
H is sent to the error correction circuit 7. As a result, as shown in FIG. 6G, the double error is corrected to a single error at the addresses (N + 1, N + 5, and N + 8) where the double error has occurred at the time of the first correction. The error correction circuit 7 corrects a single error and outputs error-free upper data BH, as shown in FIG.

For the lower data BL, the upper data B
H, the error correction circuit 7 sends the EXOR unit 11 to the error correction circuit 7 at the time of re-correction, as shown in FIG.
The codeword W after correcting the heavy error into a single error is applied. As a result, the error correction unit 3 can output error-free data B as shown in FIG.

As in the present embodiment, when bits at specific positions in each codeword W are collected and transmitted, if a burst error occurs during transmission of a slot, the error due to the burst error is It is biased to a specific position. Therefore, when a burst error has occurred, the correction signal Y = (001) indicating the position most frequently corrected at the time of the first correction.
0) is an error position caused by a burst error. As a result, errors caused by a series of burst errors can be effectively removed. As a result, at the time of the first correction,
Even if the error correction unit 3 cannot correct all errors and the error is detected in the slot, normal data B can be obtained by retrying error correction. As a result, the occurrence of a retransmission request can be prevented.

When a burst error has not occurred, or when a random error has occurred beyond the error correction capability of the error correction unit 3, the error cannot be corrected by re-correction. Therefore, the receiving device including the error correction device 1 requests the transmitting device to retransmit the slot as in the related art. As a result, the receiving device can obtain correct data.

As described above, the error correction device 1 according to the present embodiment includes a de-interleave buffer unit 2 for deinterleaving a plurality of codewords W that are interleaved and transmitted on a transmission path, and each codeword W And an error correction unit 3 that decodes the error and corrects the error. The codeword W whose error cannot be corrected based on the correction position of the codeword W that the error correction unit 3 has correctly corrected is caused by the burst error. An error position estimating unit 13 for estimating an error position, interposed between the de-interleave buffer unit 2 and the error correction unit 3,
When re-correcting a code word W that could not be corrected at the time of the first error correction, the EXOR unit 11 that corrects the correction position Y indicated by the error position estimating unit 13 and sends it to the error correcting unit 3
And

In the above configuration, the de-interleave buffer unit 2 changes the order of the received bit string for each bit and restores each codeword W forming the slot.
Thus, when a burst error occurs in the transmission path, the bit in which the burst error has occurred is distributed to each codeword W. Further, the error correction unit 3 converts each codeword W into BC
H decoding is performed to generate data B. As a result, even when a burst error occurs in the transmission path, the error can be corrected in the same manner as when a random error occurs.

When correcting an error, the error correction unit 3 sends a correction position signal E 1 indicating a correction position to the error position estimating unit 13. The error position estimating unit 13 calculates, based on the corrected position signal E1 that is applied every time each codeword W is corrected,
For a code word W whose error could not be corrected at the time of the first correction, an error due to a burst error is estimated.

For example, when the transmitting apparatus transmits a slot as in the digital communication system according to the present embodiment,
When bits at specific positions of a code word W forming the slot are collected and sequentially transmitted, errors caused by a series of burst errors concentrate on specific bit positions in each code word W. Therefore, as shown in FIG. 2, the error position estimating unit 13 outputs the counters 21a to 21a corresponding to each correction position.
1d, comparators 22a to 22c, selector 2
3a and 23b, and a decoder 24, and the estimated position signal Y indicating the counter 21 having the highest count value.
, The error position estimating unit 13 can estimate an error caused by a burst error.

If the error correction unit 3 cannot correct the error, the de-interleave buffer unit 2 sends out the code word W of the slot again. When the signal W1 indicating the code word W that cannot be corrected at the time of the initial correction is input, the EXOR unit 11 calculates an exclusive OR of the code word and the estimated position signal Y to correct the error position. I do. The corrected signal word W2 is sent to the error correction unit 3, where the error is corrected.

Therefore, if the codeword W used in calculating the estimated position and the codeword W before correction include an error caused by a series of burst errors, the EXOR unit 11
Can reduce the error of the code word W by one before giving the code word W to the error correction unit 3. Therefore,
At the time of re-correction, the error correction unit 3 can correct an error in the code word W that could not be corrected at the time of the first correction. As a result, since the error correction capability of the error correction unit 3 can be improved, the frequency of occurrence of retransmission requests can be reduced, and the efficiency of use of the transmission path can be improved.

In addition, since the interleaving method and the encoding method are the same as those in the related art, it is not necessary to change the device on the transmission side in order to improve the utilization efficiency of the transmission path. Since a conventional transmitting device can be used, communication can be performed without any problem even when a conventional receiving device and a receiving device including the error correction device 1 according to the present embodiment are mixed. Only when a transmission path on which retransmission requests frequently occur is used, the receiving device provided with the error correction device 1 can be used. Therefore, when improving the error correction capability as compared with a case where the device on the transmission side is changed, Costs required for

In this embodiment, the error correction unit 3 corrects an error in the code word W by BCH decoding, but the present invention is not limited to this. Error correction may be performed using another code. When a correctable error is detected, the error correction unit 3
Can instruct the error position estimating unit 13 of the correction position, the same effect as in the present embodiment can be obtained. Further, the error detection unit 4 performs a CRC parity check for each slot and determines whether re-correction is necessary, but the present invention is not limited to this. For example, the determination may be made based on whether the error correction unit 3 detects an error that cannot be corrected. If the necessity of re-correction can be determined at predetermined intervals, such as at each slot, the same effect as in the present embodiment can be obtained.

Further, in the digital communication system according to the present embodiment, as the interleaving method, a method of collecting bits at the same position is adopted, but the present invention is not limited to this. Even when another interleave method is adopted, a pattern when a series of burst errors is distributed to the codeword W is determined by the adopted interleave method. Therefore, the error caused by the same burst error as the error can be estimated from the correction position when the error correction unit 3 corrects the error correctly. As a result, similarly to the present embodiment, the error correction capability of the error correction unit 3 can be improved.

However, when the same interleave method as that of the present embodiment is employed, the error position estimating unit 13 can be realized by a relatively simple circuit such as the counter 21 or the decoder 24 as described above. Therefore, the error correction device 1 with improved error correction capability can be realized with a simple configuration.

Further, in the present embodiment, the count value of each counter 21 is initialized for each slot in the error position estimating unit 13, but the present invention is not limited to this. For example, the initialization may be performed at an interval shorter than the slot. However, in this case, the count value of each counter 21 decreases. In general, an error caused by a burst error is biased to a specific position over each codeword W, and an error caused by a random error is not biased to a specific position. Therefore, when the count value decreases, the possibility that a mistake caused by a random error is mistaken for an error caused by a burst error increases. As a result, when the error position estimating unit 13 estimates the error position, the accuracy is reduced.

On the other hand, when initialization is performed at intervals longer than the slot, the count value includes an error in a different slot. Since different slots are transmitted at different times, burst errors occurring in both slots are not continuous with each other. When burst errors are continuous between both slots, all codewords W cannot be error-corrected. Therefore, even if the error correction device 1 according to the present embodiment is used, error correction cannot be performed. As a result, when the decoder 24 estimates an error position caused by a series of burst errors using the count value, the accuracy is reduced as compared with the case where the count value in a slot is used.

On the other hand, when initialization is performed for each slot as in the counter 21 according to the present embodiment, an error in the estimated position due to the occurrence of a random error and an error in the estimated position due to an error in another slot are determined. Can be prevented. As a result, an error position can be estimated more reliably than when initialization is performed at another interval.

In the present embodiment, when re-correction is performed, the de-interleave buffer unit 2 outputs all codewords W of the slot, and the error correction device 1 supplies the de-interleave buffer While the unit 2 is transmitting the codeword W that does not need to be re-corrected, the timing control unit 14 prevents the EXOR unit 11 from correcting the codeword W.
Is provided. Thereby, it is possible to correct only the code word W whose error could not be corrected at the time of the first correction.

Note that the timing control unit 14
Is not limited to the configuration shown in FIG. For example, FIFO (First
In First Out) Address buffer 31 using memory
May be configured. In this case, at the time of the first correction, the addresses that could not be corrected are sequentially accumulated, and at the time of re-correction, the address that has been accumulated the earliest is compared with the address currently being processed. The address is stripped. As a result, the timing shown in FIG. Further, the OR circuit 34 becomes unnecessary.

On the other hand, at the time of re-correction, the timing control unit 14 causes the EXOR unit 11 to correct the code word W only while the code word W requiring re-correction is being processed. Even if only the address of the code word W that needs re-correction is specified to the de-interleave buffer unit 2 and only the code word W whose error could not be corrected at the time of the first correction is processed, this embodiment is omitted. Similar effects can be obtained. In this case, the processing amount of the error correction device 1 at the time of re-correction can be further reduced.

However, in this case, the timing control unit 1
4 becomes unnecessary, and a storage device such as a memory is required to store normal data B for the remaining addresses. When only the address data in which a double error has occurred at the time of re-correction is corrected, the error detection unit 4 cannot check the CRC error only with the data processed at the time of re-correction. Therefore, in order to determine whether an erroneous correction has been made at the time of re-correction, another means must be taken from that at the time of the first correction.

On the other hand, as in the present embodiment, when the de-interleave buffer unit 2 sends out all the addresses,
Since the de-interleave buffer unit 2 stores the code word W of the slot, the storage device is not required. Further, since the error correction unit 3 outputs the data of one slot in order, the error detection unit 4 performs
It can be determined whether an incorrect correction has been made.

The error correction device 1 according to the present embodiment
Is used for correcting an error in received data in a digital communication system in which data is transmitted via a wireless transmission path, such as a digital mobile phone, but is not limited thereto. INDUSTRIAL APPLICABILITY The present invention can be widely applied to digital communication systems in which data is transmitted via various transmission paths such as other wireless systems and wired systems. However, in the case of the wireless system, a burst error frequently occurs because the quality of the transmission path greatly changes as the receiving apparatus moves. Therefore, the effect of applying the present invention to a wireless system is particularly great.

[0085]

According to the first aspect of the present invention, there is provided an error correction apparatus comprising:
As described above, the error position estimating means for estimating the error position caused by the burst error for the code word for which the error cannot be corrected based on the correction position of the code word corrected correctly by the error correcting means, A correction means is provided which corrects the estimated position estimated by the error position estimating means for a code word which could not be corrected at the time of correction, and then sends the corrected word to the error correcting means again.

Therefore, if the codeword used in calculating the estimated position and the codeword before correction include an error caused by a series of burst errors, the correction means sends the codeword to the error correction means. , The error of the code word can be reduced. Therefore, the correction capability of the error correction means can be improved without changing the configuration of the transmission device.
As a result, there is an effect that the frequency of occurrence of retransmission requests can be reduced and the utilization efficiency of the transmission path can be improved.

As described above, in the error correction device according to the second aspect of the present invention, in the configuration of the first aspect of the present invention, the de-interleaving means is configured such that when each of the codewords is transmitted through a transmission path, When a plurality of elements constituting each codeword are collected and transmitted for each position in each codeword, the order of each element is changed to solve the interleave, and the error position estimating means includes: A counter that counts the number of times the error correction unit corrects the error for each correction position of each codeword, and a correction position with the highest correction frequency is selected based on the count value of each counter, and the correction unit is used as the estimated position. And a selection unit for instructing the selection.

In the above configuration, as a method of interleaving when transmitting a transmission path, when a method of dividing each code word for each element such as a bit and collecting and transmitting each element at a specific position is adopted, an error position is determined. The estimating means can correctly estimate the error position. Further, the counter and the sorting means may be
It can be realized by a relatively simple circuit. As a result, there is an effect that an error correction device corresponding to the interleave method can be realized with a simple configuration.

According to a third aspect of the present invention, as described above, in the configuration of the second aspect, each of the counters initializes a count value for each slot serving as a transmission unit. It is.

Therefore, the error position estimating means can estimate the error position with higher accuracy than when the initialization is performed at an interval shorter than the slot or when the initialization is performed at an interval longer than the slot. As a result, there is an effect that the utilization efficiency of the transmission path can be further improved.

[Brief description of the drawings]

FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a main part of an error correction device.

FIG. 2 is a block diagram illustrating a configuration example of an error position estimating unit in the error correction device.

FIG. 3 is a block diagram illustrating a configuration example of a timing control unit in the error correction device.

FIG. 4 is an explanatory diagram showing an example of an error occurrence position in a data string input to the error correction device.

FIG. 5 is a timing chart showing the operation of each unit of the error correction device at the time of first correction when the data string is input.

FIG. 6 is a timing chart showing the operation of each unit of the error correction device at the time of re-correction when the data string is input.

FIG. 7 is an explanatory diagram showing an error position of a data string input to the error correction device at the time of re-correction.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Error correction apparatus 2 De-interleave buffer part (de-interleave means) 3 Error correction part (error correction means) 11 Exclusive OR operation part (correction means) 13 Error position estimation part (error position estimation means) 21 Counter 24 Decoder (selection means)

Claims (3)

[Claims] 1. An error correction apparatus comprising: a de-interleave means for deinterleaving a plurality of codewords transmitted through a transmission path after being interleaved; and an error correction means for decoding and correcting each codeword. Based on the correction position of the codeword for which the error correction means has correctly corrected the error, for the codeword for which the error could not be corrected,
Error position estimating means for estimating an error position caused by a burst error; and a code word that cannot be corrected at the time of the first error correction.
An error correction device comprising: a correction unit that corrects the estimated position estimated by the error position estimation unit and sends the corrected position to the error correction unit again. 2. The deinterleaving means according to claim 1, wherein said plurality of elements constituting each code word are collected and transmitted for each position in each code word when said code words are transmitted through a transmission path. And the interleave is solved by changing the order of the respective elements. The error position estimating means includes a counter for counting the number of errors corrected by the error correcting means for each correction position of each codeword; 2. The error correction device according to claim 1, further comprising: a selection unit that selects a correction position with the highest correction frequency based on the count value of the above, and instructs the correction unit as the estimated position. 3. The error correction device according to claim 2, wherein each of said counters initializes a count value for each slot serving as a transmission unit.