JPH0795163A - Data transmitter - Google Patents

Abstract

PURPOSE:To provide the data transmitter in which data are efficiently sent against a periodic error. CONSTITUTION:The transmitter is provided with a coding means 1 coding an information series to obtain a transmission data series, a transmission means 3 sending the transmission data series to a receiver side, a decoding means 5 receiving the signal sent by the transmission means 3 and decoding the received signal into a decoded data series, and error timing estimate means 6, 7 receiving at least one of the reception signal, the decoded data series, and output from the decoding means 5 other than the decoded data series to estimate a timing when an error takes place in the received signal, and at least one of the decoding and coding methods is corrected based on an error timing estimated by the error timing estimate means 6, 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device used for correcting a periodic error of a digital signal in a digital information transmission system or a recording system.

[0002]

2. Description of the Related Art Conventionally, in a digital communication system as shown in FIG. 7, for an error occurring on a transmission line, an FEC method (FEC) in which an error correction code is used to correct the transmission line error on the receiving side. error c
As shown in FIG. 8, with respect to data determined to be erroneous by the receiving side, the receiving side requests the transmitting side to retransmit the ARQ method (ARQ; automa).
tic repeat request)
Further, as shown in FIG. 9, there is an interleaving technique as a burst error countermeasure in which an error that cannot be corrected while being concentrated is diffused into a correctable error.

On the communication path, periodic errors may occur due to interference from other communication systems. As an example, FIG. 10 shows a case where one periodic error occurs. Generally, it is assumed that some periodic errors with different periods occur. For example, if there is a periodic burst error with a transmission rate of 5 Mbps, an error period of 1 ms, and a burst error length of 5 μs, in this case, one error period is 5000 bits, and a long error occurs during this one period. A 25-bit burst error will occur.

If FEC is used for this error as shown in FIG. 7, FEC corresponding to a burst of 25 bits is used.
EC must be fairly redundant. This increases the amount of bits to be added for error correction with respect to the amount of information bits to be transmitted, and reduces the amount of information bits that can be transmitted. Also, the high redundancy of FEC has the drawback of making the decoder rather complex.

Next, consider the case where ARQ is used as shown in FIG. Information is transmitted for each frame, and retransmission is requested when an error is contained in the frame. If one frame is 1000 bits, one cycle of error is 5000 bits, so at least 1 in 5 frames. The frame will contain burst errors. Therefore, one-fifth of all transmitted frames will be retransmitted, and the transmission efficiency will be reduced.

Further, consider the case where interleaving is used as shown in FIG. In this, the order of the encoded data is exchanged by an interleaver and transmitted, and the order is restored by the deinterleaver before decoding.
For example, in the block type interleaving method, the data input to the interleaver is 1, 2,
3, ..., Nm are sequentially written in the memory in the horizontal direction in the order of numbers, while the data are read out by sequentially reading in the vertical direction of the memory matrix in FIG. Deinterleaving on the receiving side performs the reverse operation to restore the order of data, but the burst error added on the transmission path is spread by deinterleaving.

However, if the cycle in which the error occurs is synchronized with the interleave cycle, the error is concentrated, and the effect of error diffusion due to interleaving is lost. For example, as shown in FIG. 12, the error period is 6
If two of these bits are burst errors,
When the number of memories in the writing direction of the deinterleaver is 6, which is the same as the error period, the errors are rather concentrated after deinterleaving. Generally speaking, if an error in a certain cycle is equal to a multiple of the number n of memories in the write direction of the deinterleave, the cyclic burst errors in the communication channel will be concentrated when reading. Occurs.

As described above, in any of the above-mentioned methods, if an attempt is made to correct a periodic error added on the transmission line, a problem becomes apparent.

The same applies to a data transmission device in which the transmission line is replaced with a recording medium.

Next, the structure and operation of the conventional interleave apparatus will be described in more detail. The interleaving technique is used to spread burst errors generated in a communication path or a recording medium and improve the correction capability of a decoder for error correction codes.

Generally, a digital information communication system is modeled as shown in FIG. In FIG. 21,
The data to be transmitted is output from the information source 220 and error correction coded by the error correction coder 221.
The error correction encoder 221 encodes the data using, for example, a convolutional code, and after the transmission order is changed in the interleaver 222, the data is modulated by the modulator 223 and transmitted through the communication path 224.

Since the received signal is affected by noise and interference, the data demodulated by the demodulator 225 has an error. In the deinterleaver 226, the order of the received signals is changed so as to be the same as that at the time of outputting the error correction encoder 221. The deinterleaved data is input to the error correction decoder 227, subjected to error correction decoding, and then passed to the reception purpose 228.

Further, if the communication path is considered as a recording device, FIG.
1 is a model of a digital recording system.

Here, it is assumed that a burst error occurs on the communication path 224. Generally, when many errors concentrate on a part of the received signal sequence, the error correction decoder cannot correct the errors correctly. However, when the interleaver and the deinterleaver are used, the burst error generated in the communication channel is spread like a random error, so that the error correction capability of the decoder can be improved.

In the interleaver or the dinterleaver, the coded information is once stored in the memory circuit and then read out in a specific order different from that at the time of writing, thereby changing the order of the transmission data. The interleaver of the interleave system used conventionally considers the memory circuit to be an n × m matrix as shown in FIG. 22, and sequentially writes encoded data in the row direction, and the data is written in all the matrices. Later, it is read out in the column direction. Also, in the deinterleaver, as shown in FIG. 23, the received signal is written in the column direction of the memory circuit of n × m matrix and read out in the row direction. By such processing, data in any n consecutive bits on the communication path are separated from each other by at least (m-1) bits in the deinterleaved sequence.

FIG. 24 shows a block diagram of a conventional interleave apparatus when n = m = 4. 16-bit error-correction-coded input data (301) a ₀ , a ₁ ,
a _2, ..., a ₁₅ is inputted from the input terminal 201 is written sequentially into the memory 202. At this time, the address signal (324) at the time of writing is output from the first address designation circuit 229 in the order of 0, 1, 2, ... A control signal (306) output from the control circuit 207
Thus, the switch 206 is connected to the upper terminal, and the memory 202 becomes writable by the control signal (307). As a result, the input data a _i (i = 0, 1, 2,
, 15) is written to the address i of the memory 202.

When the writing of all data is completed, the data is read from the memory 202. In the second address designating circuit 230, 0, 4, 8, 12, 1, 5, as the address signal (325) at the time of reading.
9,13,2,6,10,14,3,7,11,15 are output. At the time of reading, the switch 206 is connected to the lower terminal by the control signal (306), and the memory 20
16-bit data (302) read from 2
a ₀ , a ₄ , a ₈ , a ₁₂ , a ₁ , a ₅ , a ₉ , a ₁₃ , a
₂ , a ₆ , a ₁₀ , a ₁₄ , a ₃ , a ₇ , a ₁₁ , and a ₁₅ are output in this order from the output terminal 203.

On the other hand, the deinterleaver performs processing for returning the signals received in this order to the original order, and passes them to the error correction decoder. As a result, even if an error occurs in continuous 4-bit data on the transmission path as described below, the error is spread on the data series input to the decoder. Note that the capital letter A indicates that an error has occurred in the data.

Received signals: a ₀ , a ₄ , a ₈ , a ₁₂ , a ₁ , A ₅ , A
₉ , A ₁₃ , A ₂ , a ₆ , a ₁₀ , a ₁₄ , a ₃ , a ₇ ,
a _11, a ₁₅ deinterleaving _{after: a 0, a 1, A} 2, a 3, a 4,
_{A 5, a 6, a 7} , a 8, A 9, a 10, a 11, a 12, A
₁₃ , a ₁₄ , a _{15 As is} well known, in a convolutional code decoder, etc.,
If there are consecutive errors in the received signal that is input, the error correction capability deteriorates. However, if the error is diffused by interleaving as described above, it is possible to suppress the deterioration of the error correction capability of the decoder and obtain a performance close to the correction capability for random errors.

By the way, not only burst errors and random errors but also errors having periodicity may occur in the communication path and recording medium. For example, when a physical failure occurs in a disk-shaped recording medium, an error having a substantially constant length occurs in a reproduced signal at a substantially constant interval. Also, in the communication system, even when there is an interference source that repeatedly generates a pulse signal, a periodic error occurs in the received signal. In such a case, the interleaving may rather concentrate the errors and reduce the error correction capability of the decoder. For example, in the interleaving method (n = m = 4) of FIG. 24, when an error of the following 4-bit period occurs, the error of the signal after deinterleaving (input to the decoder) is caused by interleaving. Will be continuous.

Received signals: a ₀ , a ₄ , A ₈ , a ₁₂ , a ₁ , a ₅ , A
₉ , a ₁₃ , a ₂ , a ₆ , A ₁₀ , a ₁₄ , a ₃ , a ₇ ,
After deinterleaving A ₁₁ , a ₁₅ : a ₀ , a ₁ , a ₂ , a ₃ , a ₄ ,
_{a 5, a 6, a 7} , A 8, A 9, A 10, A 11, a 12, a
₁₃ , a ₁₄ and a _{15 In} general, when the n × m matrix of FIGS. 22 and 23 is used,
When an error of length b occurs in an n-bit cycle, the error in the sequence after deinterleaving becomes a burst error of mb bits in length, and interleaving may rather deteriorate the decoding error rate.

[0022]

As described above, the conventional data transmission apparatus does not use the fact that the error is periodic when correcting the periodic error added in the transmission path. Is a relatively long burst, and when an error is corrected using an error correction code, it is necessary to use a correction code having redundancy enough to handle the length. In this case, the amount of information that can actually be transmitted may be considerably reduced. If the error correction code has a high degree of redundancy, the decoder is generally complicated.

Further, in the case of a system that performs retransmission, the number of retransmissions may increase as described above, and the amount of information that can actually be transmitted may be considerably reduced.

If the cycle of the interleaver and the cycle of the error added in the transmission line are synchronized, the error is concentrated due to the deinterleaving, and the error correction capability of the decoder is deteriorated. was there.

The present invention has been made in view of the above problems. A first object of the present invention is to provide a data transmission apparatus that more efficiently corrects a periodic error added in a transmission line.

The second purpose is to sufficiently diffuse not only burst errors but also periodic errors,
An object of the present invention is to provide an interleave device capable of improving the error correction capability of a decoder.

[0027]

In order to solve the above problems and achieve the first object, a data transmission apparatus according to the present invention (Claim 1) encodes an information sequence to form a transmission data sequence. Encoding means, transmitting means for transmitting the transmission data sequence to the receiving side, decoding means for receiving the signal transmitted by the transmitting means, and decoding the received signal into a decoded data sequence, An error timing estimation means for estimating a timing at which an error occurs in the received signal, by receiving at least one of the received signal, the decoded data series, and the output of the decoding means other than the decoded data series, At least one of the decoding method and the encoding method is modified based on the error timing estimated by the error timing estimating means.

Here, when modifying the coding method in the above, the receiving side notifies the transmitting side of the error timing, and based on this, the coding means determines the coding method to be modified, and The decoding means that has transmitted from the receiving side to the transmitting side and has received this may be configured to set the corresponding decoding method. Alternatively, a method for modifying the encoding method and the decoding method is determined in advance, and the decoding means directly obtains the error timing estimated by the error timing estimating means, and then based on this, the encoding means is modified. The decoding method corresponding to the encoding method may be determined.

On the other hand, in order to solve the above problems and achieve the second object, the present invention (claim 2) inputs an error correction coded data sequence of a predetermined length and inputs the input data. In a data transmission device provided with an interleave device for changing the sequence order and outputting the data, the interleave device specifies a memory circuit for storing input data, and a first circuit for designating an address for writing data in the memory circuit. It has an addressing circuit and a second addressing circuit for designating an address when reading data from the memory circuit, and the output of the first addressing circuit and the output of the second addressing circuit are , Which are non-correlated integer sequences.

Here, the memory circuit is composed of two memories that alternately write data and read data at regular time intervals, and the first addressing circuit stores data in one of the memories. An address for writing is specified, and the second addressing circuit specifies an address for reading data from the other of the memories.
A switch circuit may be provided to alternately switch the connection destination of the first addressing circuit and the connection destination of the second addressing circuit at regular time intervals.

Further, at least one of the first addressing circuit and the second addressing circuit may be constituted by a linear feedback shift register which generates an M series. In this case, the exclusive OR of the M series generated by the linear feedback shift register forming the addressing circuit and the data read from the storage circuit may be output.

Further, at least one of the first address designating circuit and the second address designating circuit may be constituted by a table.

Further, it is preferable to provide a conversion circuit for converting an integer series output from at least one of the first address specifying circuit and the second address specifying circuit into a different integer series.

[0034]

In the data transmission apparatus of the present invention (claim 1) configured as described above, the timing at which a cyclic error occurs in the transmission path is estimated by the error timing estimator, and the error timing is input to the decoder. , Gives the received signal the reliability of the received signal input to the decoder,
By performing the decoding, the cyclic error is efficiently corrected. In addition, the timing at which a cyclic error occurs in the transmission path is estimated by the error timing estimator, the error timing is input to the encoder, and the value is used to optimize or semi-optimize the coding method to obtain information. By transmitting, the periodic error can be efficiently corrected.

On the other hand, in the present invention (claim 2), since the rearrangement of signals by the interleaver is determined by the integer sequence in random order, it has no specific periodicity. As a result, even if not only a burst error but also a periodic error occurs, the error can be diffused after deinterleaving, so that the error correction capability of the decoder can be improved.

[0036]

Embodiments will be described below with reference to the drawings. It should be noted that parts having similar functions are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, the first to third embodiments are constructed so that the timing of the periodic error added in the transmission path is estimated and the coding system is adaptively modified or changed based on the estimation result. Will be described.

(First Embodiment) FIG. 1 is a block diagram showing a main configuration of a data transmission apparatus according to the first embodiment of the present invention. This data transmission device comprises an error correction encoder 1, a modulator 2, a transmission line 3, a demodulator 4, an error correction decoder 5, a comparator 6, and an error timing estimator 7.

In the above configuration, the information sequence is input to the error correction encoder 1 and error correction encoded. The error correction coded information sequence is input to the modulator 2 and a transmission signal is output. The transmission signal becomes a reception signal through the transmission path 3 and is input to the demodulator 4. Here, the transmission line 3
In, it is assumed that a periodic error is added to the signal transmitted therethrough for some reason existing outside the transmission system. The demodulator 4 demodulates the received signal and outputs a received data sequence, which is input to the error correction decoder 5. The error correction decoder 5 performs error correction decoding on the input received data series and outputs the decoded data series.

Next, in the present embodiment, the comparator 6 is supplied with the received data series to which an error has been added, which is the output of the demodulator 4, and the decoded data series which has been error-corrected and decoded by the decoder 5. This comparator 6 compares the decoded data series again encoded and the received data series bit by bit, and estimates the error series added in the transmission path. As this error sequence, a block error sequence indicating the presence or absence of an error for each block can be considered in addition to the bit error sequence indicating the presence or absence of an error for each bit.

The estimated error sequence is input to the error timing estimator 7 and the timing at which an error occurs is estimated. The error timing estimated by the error timing estimator 7 is input to the error correction decoder 5.

In the subsequent communication, the error timing estimated as described above predicts that the received data has a high probability of being erroneous. Therefore, it is predicted that the received data sequence is erroneous due to the error timing. Decoding bits as erasure bits is expected to improve the decoding error rate. In addition, in the case of Viterbi decoding or the like, when a metric corresponding to a bit predicted to be erroneous is weighted with a small weight for decoding, the decoding error rate is improved.

Next, FIG. 2 shows a configuration example of the error timing estimator 7. The error sequence estimated by the comparator 6 is input to the error period estimator 9 and the error period is estimated. The period estimation is realized by using Fourier transform, Hadamard transform, or the like. The estimated error period and the error sequence are input to the correlator 10. The correlator 10 creates an appropriate window function according to the period estimated by the error period estimator 9, and slides it to estimate the error phase by correlating with the error sequence itself, and obtains it from the period and the phase. The error timing that is output is output. The timing at which an error occurs can be estimated from these operations.

As the error sequence input to the error timing estimator 7 in FIG. 1, in the case of soft decision decoding, the soft decision value of the received signal input to the decoder 4 and the sequence obtained by re-encoding the decoded data are used. The correlation value of can also be used.

When convolutional coding is used for the error correction coding and a Viterbi decoder is used for the error correction decoder,
The receiving unit 8 of FIG. 1 is replaced with the configuration of FIG. 3, and the fact that the increase of the path metric corresponds to the error sequence is used as the input of the error metric estimator 7a with the path metric in the Viterbi decoder. It is also possible to estimate the error timing. In this case, the output of the successive decoder or equalizer can be used instead of the Viterbi decoder.

When CRC is used for error correction coding and CRC check is performed by the error correction decoder, the state of error occurrence in frame units can be estimated by the CRC check bit. If this is used, the error timing in frame units can be estimated.

When the periodic error is caused by an interference signal having a received power larger than that of the desired signal, the receiving unit 8 in FIG. 1 is replaced with the configuration as shown in FIG.
If the envelope is observed as the received power of the received signal, it is judged that an error occurs in a section where the envelope is large compared to other times, and the error sequence judged by this is input to the timing estimator. The error timing can be estimated.

(Second Embodiment) FIG. 5 is a block diagram showing a main configuration of a data transmission apparatus according to a second embodiment of the present invention. The error timing estimator 7 has the same configuration as that of the first embodiment described above.
The error timing estimated by the second transmission line 3
It is characterized in that it is provided to the error correction encoder 1a on the transmission side via b to modify the encoding system.

In FIG. 5, the information sequence is input to the error correction encoder 1a and is error correction encoded, and the modulator 2 outputs a transmission signal. The transmission signal is input to the first transmission line 3a, and is input to the demodulator 4 through the first transmission line 3a. Here again, it is assumed that a periodic error is added to the first transmission line 3a. The demodulator 4 demodulates the received signal and outputs a received data sequence. This received data series is input to the error correction decoder 5a.

The received data series to which an error has been added and the decoded data series error-corrected and decoded by the error correction decoder 5a are input to the comparator 6. Then, the decoded data series is encoded again and the received data series are compared bit by bit, and the error series is estimated. The estimated error sequence is input to the error timing estimator 7 and the timing at which an error occurs is estimated.

Here, in this embodiment, the estimated error timing is given to the error correction encoder 1a via the second transmission line 3b. The error correction encoder 1a corrects the encoding system by using the error timing in order to efficiently correct the cyclic error.

For example, the error timing makes it possible to know whether the interleave is synchronized with the error period. Therefore, when it is determined that such synchronization occurs,
Change the interleave period to prevent synchronization. As a result, the deterioration of the decoding error rate due to the synchronization of the interleaving cycle and the error cycle can be improved.

Further, the decoding error rate can be improved by stopping the data transmission, changing the transmission rate, or changing the transmission power by utilizing the error timing. In addition, the parameter of the error correction code can be changed to correspond to the error cycle.

Further, if the error is caused by something like a disturbing wave of strong power, it is conceivable that reception synchronization may be lost. Therefore, if a signal for synchronization or data is transmitted at the end of the error section estimated by the estimated error timing, the loss of synchronization can be recovered.

The method of estimating the error timing may be the same as that of the first embodiment, and the estimation method may have the same variations as those of the first embodiment.

(Third Embodiment) FIG. 6 is a block diagram showing the arrangement of the essential parts of a data transmission apparatus according to the third embodiment of the present invention. Although this data transmission device has almost the same configuration as the device of FIG. 5, the error timing estimated by the error timing estimator 7 is
It is characterized in that it is given to the error correction encoder 1a via the second transmission line 3b and also given to the error correction decoder 5b.

That is, in the above-described second embodiment, the parameters of the coding system of the error correction encoder 1a are modified by the estimated error timing, and the modified parameters are error-correction decoded by some method. Bowl 5
However, in the data transmission apparatus of the present embodiment, the method of changing the parameters of encoding and decoding is determined in advance, and the same error timing is used as the error correction encoder 1a. It is input to the error correction decoder 5b.

Therefore, since the parameter to be corrected can be determined by each of the error correction encoder 1a and the error correction decoder 5b, the parameter correction information is transmitted from the error correction encoder 1a to the error correction decoder 5b. There is an advantage that the parameters can be modified without reducing the amount of information to be transmitted.

Next, fourth to tenth embodiments configured to randomly interleave transmission data sequences will be described. In the following description, description of the entire configuration of the system such as the data transmission device will be omitted, and the interleave device applied to the system will be described.

(Fourth Embodiment) FIG. 13 shows a fourth embodiment of the present invention.
FIG. 3 is a schematic configuration diagram showing an interleave apparatus according to the embodiment of FIG. This interleaving device comprises a memory 32, a first addressing circuit 34, a second addressing circuit 35, a switch 36, and a control circuit 37.

In the above configuration, the error correction coded N-bit data series (101) is sequentially input from the input terminal 31 and written in the memory 32. Memory 32
Has N addresses. The address signal (103) at the time of writing is output from the first addressing circuit 34. This signal is N from "0" to "N-1".
Output each integer once in random order. At the time of writing, the control signal (10
6), the switch 36 is connected to the upper terminal, and the memory 32 is made writable by the control signal (107).

When the writing of the N-bit input data is completed, the data is read from the memory 32. The address signal (104) at the time of reading is generated by the second address designating circuit 35. This signal is "0"
From N to “N−1” are once taken, and if the sequence is uncorrelated with the address signal (103) at the time of writing,
Any series will do. At the time of reading, the switch 36 is connected to the lower terminal by the control signal (106), and the signal (102) read from the memory 32 is output from the output terminal 33.

Since the address signal (103) at the time of writing is a random integer series and the address signal (104) at the time of reading is an integer series uncorrelated with it, the input data series (101) is almost the same. It is output to the communication path in a random order. As a result, no matter what cycle error occurs in the communication channel, the error will not be concentrated in the deinterleaved sequence. Of course, burst errors can be dispersed as before.

(Fifth Embodiment) FIG. 14 shows the fifth embodiment of the present invention.
FIG. 3 is a schematic configuration diagram showing an interleave apparatus according to the embodiment of FIG. This interleaving device includes a first memory 38, a first memory 39, a first addressing circuit 34, a second addressing circuit 35, a switch 40, a switch 41,
It is composed of a control circuit 42. That is, in the present embodiment, the two memories are alternately used for reading and writing so that data continuously input for N bits or more can be processed.

In the above structure, the error-correction-coded 2N-bit data sequence (101) is sequentially input from the input terminal 31, and the first N bits are the first memory 38.
Then, the subsequent N bits are written to the second memory 39.
In addition, the N address signals (103) at the time of writing are
The address signal (104) output from the first address specifying circuit 34 at the time of reading is generated by the second address specifying circuit 35. However, each of the two memories is N
Suppose it has 4 addresses.

The first N bits are input to the first memory 3
While the data is being written in 8, the N-bit data previously written is read from the second memory 39.
At this time, the control signal (11
0), switch 41 turns signal 103 to 108,
Connect signal 104 to 109. In addition, the control signal (11
1) makes the first memory 38 writable, and the control signal (113) connects the switch 40 to the left side and outputs the data (115) read from the second memory 39 from the output terminal 33.

The subsequent N bits are input to the second memory 39.
While being written to, the previously written N-bit data is read from the first memory 38. At this time, the switch 41 connects the signal 104 to 108 and the signal 103 to 109 by the control signal (110). Further, the control signal (112) makes the second memory 39 in a writable state, and the control signal (113) connects the switch 40 to the right side and outputs the signal (1) read from the first memory 38.
14) is output from the output terminal 33.

When the error-correction-coded data series exceeds 2N bits, the above operation is repeated appropriately.

Also in this embodiment, the address signal (103) at the time of writing is an integer series in a random order, and the address signal (104) at the time of reading is the address signal, as in the fourth embodiment. Since it is an integer sequence uncorrelated with (103), the input data sequence (101)
Are output to the communication path in a substantially random order. As a result, no matter what cycle error occurs in the communication channel, the error will not be concentrated in the deinterleaved sequence.

Next, in each of the following embodiments, a concrete configuration example of the address generating circuit for generating an integer series in a random order will be shown.

(Sixth Embodiment) FIG. 15 shows a sixth embodiment of the present invention.
FIG. 3 is a schematic configuration diagram showing an interleave apparatus according to the embodiment of FIG.

In this embodiment, the linear feedback shift register 43 for generating the M series (maximum period series) is used in the first addressing circuit. The number N of memory addresses in the fourth embodiment is set to "16", and the linear feedback shift register 4
3 comprises four shift registers 50 and adders 51.

The address signal (116) at the time of writing is
The contents of the shift register 43 are shown at each time. The initial value of the shift register 43 is 1, 0, 0, from the left.
When it is set to 0, this is shifted 14 times and the register is finally reset, the contents of the register change as shown in FIG. This becomes a pseudo-random integer series, which is used as the address signal (116) at the time of writing.

The address signal (11
7) is an integer series 0, 1, 2, 3, ..., 15 generated by the hexadecimal (4 bit) counter 14.

With this interleaver, the input data sequence (101) {a ₀ , a ₁ , a ₂ , ..., A ₁₅ } is
_{a 15, a 3, a 2} , a 6, a 1, a 9, a 5, a 11, a
₀ , a ₁₄ , a ₈ , a ₁₃ , a ₄ , a ₇ , a ₁₀ , and a ₁₂ are transmitted in this order. If a 4-bit burst error occurs in the received signal sequence, the following occurs and the error after deinterleaving is spread. The capital letter A
_It is assumed that _i indicates that an error has occurred in the original data a _i .

Received signals: a ₁₅ , a ₃ , a ₂ , a ₆ , a ₁ , a ₉ , A
₅ , A ₁₁ , A ₀ , A ₁₄ , a ₈ , a ₁₃ , a ₄ , a ₇ ,
a _10, a ₁₂ deinterleaving _{after: A 0, a 1, a} 2, a 3, a 4,
_{A 5, a 6, a 7} , a 8, a 9, a 10, A 11, a 12, a
₁₃ , A ₁₄ , a ₁₅ Also, when an error of period 4 occurs in the received signal sequence,
The error after deinterleaving is spread as follows.

Received signals: a ₁₅ , A ₃ , a ₂ , a ₆ , a ₁ , A ₉ , a
₅ , a ₁₁ , a ₀ , A ₁₄ , a ₈ , a ₁₃ , a ₄ , A ₇ ,
a _10, a ₁₂ deinterleaving _{after: a 0, a 1, a} 2, A 3, a 4,
_{a 5, a 6, A 7} , a 8, A 9, a 10, a 11, a 12, a
₁₃ , A ₁₄ , a _{15 In} this way, it is possible to spread the error after deinterleaving for any error.

(Seventh Embodiment) FIG. 16 shows a seventh embodiment of the present invention.
FIG. 3 is a schematic configuration diagram showing an interleave apparatus according to the embodiment of FIG.

In this embodiment, the two address designating circuits are both constructed of the feedback shift registers (45, 46). However, the output of the two feedback shift registers (11
8, 119) are N from 0 to (N-1), respectively.
It is an integer sequence containing one integer each, and it is desirable that they are uncorrelated with each other.

(Eighth Embodiment) FIG. 17 shows an eighth embodiment of the present invention.
FIG. 3 is a schematic configuration diagram showing an interleave apparatus according to the embodiment of FIG. The control circuit 37 is omitted in FIG.

In this embodiment, as in the sixth embodiment,
A linear feedback shift register 43 that generates an M sequence (maximum period sequence) is used in the first addressing circuit. This shift register is the M of 0001001101011110
Generate a sequence (120) (the last 1 bit is the bit at reset). This M series and the output series (102) from the memory 32 are added by the exclusive OR circuit 47,
Create an output signal sequence (121).

By doing so, an interleaver having a scramble function can be easily constructed.

(Ninth Embodiment) FIG. 18 shows a ninth embodiment of the present invention.
FIG. 3 is a schematic configuration diagram showing an interleave apparatus according to the embodiment of FIG. The control circuit 37 is omitted in FIG.

In this embodiment, the table 48 constitutes the first addressing circuit. The counter 44 is the memory 3
It is used as a circuit that generates an address when reading the address signal (122) from the table 48 when writing data to the memory 2, and is used as a circuit that generates a read address when reading data from the memory 32.
However, the table 48 stores a sequence of integers in a random order that includes one N integer each from 0 to (N-1).

As a method for generating a random-order integer sequence, for example, N from 0 to (N-1) is written.
It can be generated by preparing individual balls, randomly picking one ball from each, and arranging the numbers written on the balls in the order in which they are taken out.

(Tenth Embodiment) FIG. 19 is a schematic block diagram showing an interleaving apparatus according to the tenth embodiment of the present invention. The control circuit 37 is omitted in FIG.

In this embodiment, the first addressing circuit is composed of the feedback shift register 43 and the conversion circuit 49. If the content of the register of the feedback shift register 43 is used as it is as an address at the time of writing, continuous input data may not be sufficiently separated and output. For example, when the integer sequence of FIG. 20 (a) is used as in the sixth embodiment, a ₂ and a ₃ are transmitted while being adjacent to each other, so that a burst error occurs as a result. There is a possibility that continuous errors will occur even in the signal sequence after deinterleaving.

Therefore, the signal (116) output from the shift register 43 may be partially converted by the conversion circuit 49 so that the burst error on the communication path is sufficiently diffused.
For example, the signal (116) before conversion as shown in FIG.
If each of the two bits is 2,15, by converting each to 15,2, it becomes possible to output all two consecutive bits at the time of input, separated from each other at the time of output.

The present invention is not limited to the above-mentioned respective embodiments, and can be variously modified and carried out without departing from the scope of the invention.

[0090]

As described above, the present invention (Claim 1).
According to the method, the timing at which the error occurs is estimated with respect to the periodic error added in the transmission path, and the decoding method or the encoding / decoding method is corrected based on the estimated error timing. To do. As a result, the reliability of the transmission data can be improved.

According to the present invention (claim 2), the rearrangement of signals by the interleaver is determined by an integer sequence in a random order, so that the order of transmission signals does not have a specific periodicity. As a result, the error after deinterleaving can be spread even when a periodic error occurs as well as a burst error.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment according to the present invention.

FIG. 2 is a block diagram showing the timing estimator shown in FIG.

FIG. 3 is a block diagram showing another configuration example of the receiving unit shown in FIG.

FIG. 4 is a block diagram showing still another configuration example of the receiving section shown in FIG.

FIG. 5 is a schematic configuration diagram showing a second embodiment according to the present invention.

FIG. 6 is a schematic configuration diagram showing a third embodiment according to the present invention.

FIG. 7 is a block diagram showing the overall configuration of a data transmission device using FEC.

FIG. 8 is a block diagram showing the overall configuration of a data transmission device using ARQ.

FIG. 9 is a block diagram showing the overall configuration of a data transmission device using the interleave method.

FIG. 10 is a diagram illustrating a periodic error.

FIG. 11 is a diagram showing a memory matrix for explaining an interleaver.

FIG. 12 is a diagram for explaining synchronization between an interleaver cycle and an error cycle.

FIG. 13 is a schematic configuration diagram showing a fourth embodiment according to the present invention.

FIG. 14 is a schematic configuration diagram showing a fifth embodiment according to the present invention.

FIG. 15 is a schematic configuration diagram showing a sixth embodiment according to the present invention.

FIG. 16 is a schematic configuration diagram showing a seventh embodiment according to the present invention.

FIG. 17 is a schematic configuration diagram showing an eighth embodiment according to the present invention.

FIG. 18 is a schematic configuration diagram showing a ninth embodiment according to the present invention.

FIG. 19 is a schematic configuration diagram showing a tenth embodiment according to the present invention.

FIG. 20 is a diagram showing a first addressing circuit output in the sixth embodiment and a conversion table of a conversion circuit in the tenth embodiment.

FIG. 21 is a block diagram of a digital communication system.

FIG. 22 is a diagram showing a memory circuit of a conventional interleave device.

FIG. 23 is a diagram showing a memory circuit of a conventional deinterleave device.

FIG. 24 is a schematic configuration diagram of a conventional interleaving device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Error correction encoder 2 ... Modulator 3 ... Transmission path 3a ... 1st transmission path 3b ... 2nd transmission path 4 ... Demodulator 5 ... Error correction decoder 6 ... Comparator 7 ... Error timing estimator 8 ... Reception unit 9 ... Error period estimator 10 ... Correlator 11 ... Envelope detector 31 ... Input terminal 32 ... Memory 33 ... Output terminal 34 ... First address designation circuit 35 ... Second address designation circuit 36 ... Switch 37 Control circuit 101 N-bit data sequence 102 Deinterleaved sequence 103 Write address signal 104 Read address signal 105 Address signals 106, 107 Control signals

Claims (2)

[Claims] 1. An encoding unit for encoding an information sequence to form a transmission data sequence, a transmission unit for transmitting the transmission data sequence to a receiving side, and a signal transmitted by this transmission unit for receiving the signal. Decoding means for decoding a received signal into a decoded data sequence, and at least one of the received signal, the decoded data sequence, and the output of the decoding means other than the decoded data sequence as an input, and the received signal Error timing estimating means for estimating a timing at which an error occurs, and at least one of the decoding method and the encoding method is modified based on the error timing estimated by the error timing estimating means. A data transmission device characterized by: 2. A data transmission device comprising an interleave device for inputting a data sequence of a predetermined length that has been error-correction coded, and for outputting the data sequence by changing the order of the input data sequence, wherein the interleave device is an input device. Circuit for storing the stored data, a first addressing circuit for designating an address when writing data to the storage circuit, and a second addressing circuit for designating an address for reading data from the storage circuit And the output of the first addressing circuit and the output of the second addressing circuit are integer sequences that are uncorrelated with each other.