JPH1051299A - Pll frequency synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the circuit, preventing frequency fluctuation due to load fluctuation of a conventional PLL frequency synthesizer circuit adopting a conventional technology. SOLUTION: A switch SW 2 is provided between a PLL synthesizer 1 and an LPF 3, the switch SW 2 is open before an on/off timing of a power supply of an amplifier or a mixture being a load circuit, so as to disconnect an output of a phase comparator of the PLL synthesizer IC from the LPF, thereby keeping a frequency of a VCO 4 constant. After the on/off of a power supply for the load circuit, the switch SW 2 is closed to again connect an output of the phase comparator of the PLL to the LPF. Thus, frequency fluctuations due to the on/off of the power supply of the amplifier or the mixer which is the load circuit for the PLL frequency synthesizer is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer circuit, and more particularly to a PLL using a charge pump type PLL synthesizer IC in which the output of a phase comparator is used.
The present invention relates to a frequency synthesizer circuit.

[0002]

2. Description of the Related Art A conventional frequency synthesizer circuit is shown in FIG.
As shown in FIG. 3, a voltage controlled oscillator (hereinafter referred to as VCO) 4 for outputting a frequency corresponding to the control voltage, an output frequency thereof is divided, and an output (hereinafter referred to as PD) corresponding to a difference from a reference frequency is obtained.
OUT), a low-pass filter (hereinafter referred to as LPF) 3 for integrating the PD OUT output from the PLL 1 and converting it to a DC voltage, and a VCO 4 for preventing the PLL loop circuit from being affected. A buffer circuit (hereinafter b) provided to transmit the output to the next stage circuit
buff5) and a mixer 7 or an amplifier 8 which is a load circuit operated by an output of the buff5.
And a switch (hereinafter referred to as SW) SW6 for connecting these power supplies, and a control signal A for controlling the switch.

The operation of the PLL frequency synthesizer circuit configured as described above will be described below.

When the control signal A turns off the switch SWa6, the circuits PLL1, LPF3, VCO4 and buff5 are operated to converge the PLL synthesizer IC to a certain frequency. After that, the switch 6 is turned on by the control signal A, and the power of the mixer 7 or the amplifier 8 is turned on. The reason why there is a time difference in turning on the power is to reduce the current consumption due to the relatively large current consumption of the mixer or amplifier circuit, and as a power saving method for small portable wireless devices such as battery driven. This is a general method.

Next, FIG. 6 shows this operation on the time axis with respect to the timing of the control signal A and the output frequency of the VCO 4. The output frequency of the VCO 4 fluctuates greatly at the moment when the power is supplied to the mixer 7 or the amplifier 8, and after a short time, the fluctuation settles to the original frequency due to the convergence force of the PLL loop. Similarly, the output frequency of the VCO also fluctuates greatly at the moment when the power of the mixer 7 or the amplifier 8 is turned off. The time at which the frequency fluctuation stops depends on the design of the frequency loop and the design of buff5.

The cause of such a frequency variation is that the input impedance of the mixer 7 or the amplifier 8 changes abruptly when the power is turned on or off, and this sudden change in the impedance causes a sudden load change on the PLL loop. And causes frequency fluctuation. As described above, in the conventional PLL frequency synthesizer circuit, the frequency changes due to ON / OFF of the power supply of the amplifier or the mixer.

To solve the problem of the frequency fluctuation of the conventional PLL frequency synthesizer, the power supply of the amplifier is turned on / off.
A method has been proposed to keep the input impedance of the amplifier constant regardless of the circuit (Japanese Unexamined Patent Publication No. 2-44923). However, the use of a resistor and a capacitor in the circuit for keeping the impedance constant causes a circuit delay. However, there remains a problem that the frequency fluctuation cannot be completely suppressed and the circuit scale is large.

[0008] In addition, VC according to the power ON / OFF
A method of suppressing the frequency fluctuation by inputting a signal opposite to the frequency fluctuation to O as a modulation signal (Japanese Patent Laid-Open No. Hei.
However, this method also has a problem that it is difficult to set the level of the reverse signal.

[0009]

As described above, in the conventional PLL frequency synthesizer circuit, when the power supply of the mixer or the amplifier of the load circuit is turned on / off, the frequency fluctuation occurs in the VCO output. In addition,
In JP-A-44923, a circuit delay occurs and the circuit scale increases, and in JP-A-1-183920, there is a disadvantage that it is difficult to set the level of the reverse signal.

An object of the present invention is to provide a PL
The frequency fluctuation due to the power ON / OFF of the mixer or the amplifier of the load circuit of the L frequency synthesizer circuit is prevented, and the data transmission or reception can be performed immediately after the power of the mixer or the amplifier is turned ON. An object of the present invention is to provide a PLL frequency synthesizer circuit capable of avoiding the adverse effects of transmission and reception outside the frequency.

[0011]

SUMMARY OF THE INVENTION A PLL frequency synthesizer circuit according to the present invention comprises a PLL synthesizer IC using a phase-locked loop, a low-pass filter LPF for converting an output from the IC to DC, and a control voltage corresponding to a control voltage. In the PLL frequency synthesizer circuit including the VCO that outputs the output frequency, the output of the phase comparator of the PLL synthesizer IC is separated from the LPF before the ON / OFF timing of the power supply of the load circuit, and then the phase of the PLL synthesizer IC is There is switching means for connecting the output of the comparator to the LPF again.

The switching means includes a first switch circuit provided between a PLL synthesizer IC and the LPF, and an on / off switch of a power switch of the load circuit.
A preferred embodiment includes a control signal generating means for turning off the first switch circuit immediately before F and turning on the first switch circuit immediately after the power of the load circuit is turned on / off. .

[0013] Further, the switching means includes a switch for the VCO.
Is provided in a PLL synthesizer IC having an N counter for dividing the output of N by N, an R counter for dividing the reference frequency by R, and a phase comparator, and selectively switching between the output of the N counter and the output of the R counter. A second switch circuit connected to the phase comparator and a second switch circuit constantly connecting the output of the N counter to the phase comparator, and immediately before turning on / off a power switch of the load circuit, The output of the phase comparator is switched to high impedance by switching from the connection of the N counter to the connection of the R counter, and immediately after the power switch of the load circuit is turned ON / OFF, the connection of the R counter of the second switch circuit is switched to the connection of the N counter. A PLL frequency synthesizer circuit having a control signal generating means for restoring the connection is another preferred embodiment for simplifying the configuration.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a PL according to the present invention.
FIG. 2 is a schematic configuration diagram of a first example of an L frequency synthesizer circuit. This PLL frequency synthesizer circuit outputs a frequency corresponding to a control voltage, a VCO 4 and an output PD OUT corresponding to a difference from a reference frequency.
Synthesizer IC1 that sends out a signal, and an LP that integrates PD OUT that is the output of the IC and converts it into a DC voltage
F3, a switch (hereinafter referred to as SW) 2 for connecting / disconnecting the PD OUT to / from the LPF, a control signal B for controlling the SW2, and an output of the VCO 4 to the next stage so as not to affect the PLL loop circuit. Buff5 provided for transmission to the circuit of FIG. 1, and a mixer 7 or an amplifier 8 which is a load circuit operated by an output of the buff5.
And a switch SW6 for controlling the power supply thereof, and a control signal A for controlling the switch SW6. Here, the control signal B
Is a B signal generator 1 that outputs prior to the operation of the control SW 6
4 output.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG. SW6 by control signal A
Is OFF, PLL1, LPF3, VCO4, b
uff5 is operated to converge the PLL frequency synthesizer circuit to a certain frequency.

After that, when the control signals A and B are turned on / off at the timing shown in FIG. 2, the SW 6 is turned on by the control signal A, so that the mixer 7 or the amplifier 8 is turned on immediately before the power is turned on. SWb2 is turned off by the control signal B to disconnect PDOUT from the LPF. Immediately after SW6 is turned on, SWb2 is turned off by the control signal B.
2 is turned on to connect PD OUT to the LPF.

Similarly, SW6 is turned off by the control signal A.
SWb2 is turned off by the control signal B immediately before turning off the power of the mixer 7 or the amplifier 8 by setting the state.
Then, the PD OUT output is disconnected from the LPF, immediately after SW6 is turned on, and SW2 is turned on by the control signal B to turn on P2.
Connect the D OUT output to the LPF.

As described above, the PLL frequency synthesizer circuit of the present invention provides a power ON / OF of a mixer or an amplifier.
Before the timing F, the output PD OUT of the PLL phase comparator 13 (shown in FIG. 3) is disconnected from the LPF to keep the control voltage of the VCO constant, so that the power of the mixer or the amplifier is turned on / off. Does not occur (as shown in FIG. 6). This is shown in FIG.

FIG. 3 shows a second embodiment of the PLL frequency synthesizer circuit according to the present invention. In the embodiment of FIG. 3, the function of SW2 in the embodiment of FIG.
This is an example of a case where the processing is performed in C.

In FIG. 3, a PLL synthesizer IC1
2 is an N counter 9 for dividing the output of the VCO by N and an R counter 10 for dividing the reference frequency of the crystal oscillator or the like by R.
A phase comparator 13 for outputting an output corresponding to the phase difference between the outputs of the N counter and the R counter; and a switch SWc for switching an input to the phase comparator to an N counter output or an R counter output.

In the ordinary PLL synthesizer IC, the switch SW11 is fixedly connected to the side a. By switching the switch SW11 to the side b, the switch SW2 in FIG. Has the same effect. Hereinafter, the operation will be described with reference to FIG.

When the SW 11 is switched to the b side, the same output of the R counter 10 is input to the phase comparator 13. The phase comparator 13 outputs a pulse in accordance with the phase difference between the two input signals. However, in the case of the same phase (same frequency), high-impedance output is performed, so that charge is not supplied to the LPF and SW2 in FIG. Has the same effect as when you do

Therefore, a PL having the function shown in FIG.
If an L synthesizer IC is used, the portion of SWb2 in the embodiment in FIG. 1 is omitted, and the circuit is greatly simplified.
This is useful for reducing the size and weight of the device.

[0024]

As described above, according to the present invention, the PD OUT is connected to the LF immediately before the power supply of the mixer or the amplifier as the load circuit of the PLL frequency synthesizer is turned ON / OFF.
Disconnect from P, turn on mixer or amplifier power
By connecting PD OUT to the LPF immediately after / OFF, frequency fluctuation is prevented, so that data transmission or reception can be performed immediately after circuit maintenance and power supply connection to the load circuit. There is an effect that generation of a frequency other than the determined frequency can be avoided.

Further, the additional circuit according to the present invention is merely an insertion of a switch circuit, so that the circuit scale can be reduced, and it is possible to contribute to the reduction in size and weight.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a PLL frequency synthesizer circuit of the present invention.

FIG. 2 is a timing chart of a control signal of the PLL frequency synthesizer circuit of the present invention.

FIG. 3 shows a second embodiment of the PLL frequency synthesizer circuit of the present invention.
FIG. 3 is a block diagram of a PLL synthesizer according to the embodiment of FIG.

FIG. 4 is a diagram showing the effect of the PLL frequency synthesizer circuit of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional PLL frequency synthesizer circuit.

FIG. 6 is a diagram showing an operation of a conventional PLL frequency synthesizer circuit.

[Explanation of symbols]

 Reference Signs List 1 PLL synthesizer IC 2 SW 3 Low-pass filter (LPF) 4 Voltage controlled oscillator (VCO) 5 Buffer 6 SW 7 Mixer 8 Amplifier 9 N counter 10 R counter 11 SW 12 PLL synthesizer IC 13 Phase comparator 14 B signal generation Department

Claims (3)

[Claims] 1. A PL using a phase locked loop
A PLL frequency synthesizer circuit including an L synthesizer IC, a low-pass filter LPF for converting an output of the IC into a DC voltage, and a voltage control oscillator circuit VOC for outputting a frequency corresponding to a control voltage; Before the ON / OFF timing of
A PLL frequency synthesizer circuit comprising switching means for disconnecting an output of a phase comparator of a PLL synthesizer IC from an LPF and thereafter reconnecting an output of the phase comparator of the PLL synthesizer IC to the LPF. 2. The switching means includes: a first switch circuit provided between a PLL synthesizer IC and the LPF; and a first switch circuit immediately before turning on / off a power switch of the load circuit. 2. The PLL frequency synthesizer circuit according to claim 1, further comprising control signal generation means for turning off the first switch circuit immediately after the power supply of the load circuit is turned on / off. 3. The switching means includes an N counter for dividing the output of the VCO by N, and an R counter for dividing the reference frequency by R.
A second switch circuit provided in a PLL synthesizer IC having a counter and a phase comparator for selectively switching the output of the N counter and the output of the R counter and connecting to the phase comparator; The circuit connects the output of the N counter to the phase comparator, and switches the connection of the N counter to the connection of the R counter immediately before the power switch of the load circuit is turned on / off, thereby setting the output of the phase comparator to high. Impedance, ON / O of power switch of the load circuit
2. The PLL frequency synthesizer circuit according to claim 1, further comprising control signal generating means for restoring the connection of the R counter of the second switch circuit to the connection of the N counter immediately after the FF.