JPH1050869A - Method of manufacturing non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an erroneous program to be written in a memory cell by suppressing a reverse tunneling phenomenon as low as possible. SOLUTION: An LOCOS oxide film is formed on a semiconductor substrate 11 and is removed, a groove 11A is formed on the substrate 11, and a floating gate 17 is formed near the groove 11A, thereby forming a second gate insulating film so that the shape of an angle under the floating gate 17 is not sharp and consequently enabling a reverse tunneling phenomenon to be suppressed as low as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly, to an object of the present invention is to prevent a malfunction of a split gate type flash memory when writing information.

[0002]

2. Description of the Related Art A method of manufacturing a split gate flash memory, which is a conventional nonvolatile semiconductor memory device, will be described below with reference to the drawings. This split gate type flash memory is a flash memory in which a control gate 7 is formed from the upper part to the side part of the floating gate 5 via a gate insulating film 6 as shown in FIG.

In order to fabricate this, first, as shown in FIG. 7, a first gate insulating film made of a SiO2 film and a polysilicon film 3 are formed sequentially on a semiconductor substrate 1, and a LOCOS film is formed on the polysilicon film 3. An oxide film 4 is formed. Next, as shown in FIG. 8, the polysilicon film 3 is etched and removed using the LOCOS oxide film 4 as a mask to form a floating gate 5.

Next, as shown in FIG. 9, the insulating film 2 is isotropically etched with a hydrofluoric acid-based etchant so as to be etched and removed so as to remain only under the floating gate. Next, as shown in FIG.
Of the gate insulating film 6 is formed.

After that, a polysilicon film is formed on the second gate insulating film 6 and is patterned so as to remain from the upper part to the side part of the floating gate 5 to form the control gate 7, and the floating gate thus formed is formed. Using the gate 5 and the control gate 7 as a mask, impurities are implanted into the semiconductor substrate 1 to form source / drain regions 8 and 9. As a result, a split gate flash memory as shown in FIG. 11 is formed.

In the above-mentioned split-gate flash memory, a program is written by turning on a transistor of a memory cell to be written (hereinafter, referred to as a selected cell) and injecting electrons into a floating gate 5. I was

[0007]

However, according to the above-described conventional method for manufacturing a nonvolatile semiconductor memory device, the side surface of the floating gate 5 is straight, and the gate insulating film 6 is formed on the floating gate 5 by oxidation. In the process, the insulating film formed of the thermal oxide film formed on the side surface of the floating gate 5 tends to be generally thin, so that the shape of the second gate insulating film 6 at the corner KB is:
As shown in FIG. 10, the tip has a sharp shape.

For this reason, when the control gate 7 is formed thereafter, the shape of the corner 7A of the control gate 7 depending on the shape of the second gate insulating film 6 as the base becomes sharp, and the control gate 7 and the floating gate 5 becomes narrower. Thus, if a relatively high voltage is applied during this time, the movement of electrons tends to occur during that time.

Therefore, as shown in FIG. 12, the voltage (VCG) of the control gate 7 is 0 V, the source voltage (VS) is 12 V, and the voltage (VFG) of the floating gate induced by the source voltage (VS) is 10 V at the time of writing. Since the potential difference between the control gate 7 and the floating gate 5 becomes as large as about 10 V in the non-selected cell, electrons (e−) are discharged from the sharp corner 7A of the control gate 7 to the floating gate 5. (Hereinafter, this phenomenon is referred to as reverse tunneling).

As described above, there has been a problem that a program operation is mistakenly performed in a non-selected cell in which writing is prohibited, and a malfunction occurs. Therefore, the present invention provides a method of manufacturing a nonvolatile semiconductor memory device capable of suppressing the above-described reverse tunneling phenomenon as much as possible and suppressing writing of an erroneous program into a memory cell using the same. The purpose is to:

[0011]

Therefore, according to the present invention, after forming a LOCOS oxide film 13 on a semiconductor substrate 11, the oxide film 13 is removed to form a groove 11A in the substrate 11. Next, a first gate insulating film 14 and a polysilicon film 15 are sequentially formed on the entire surface, and a LOCOS oxide film 16 is formed on the polysilicon film 15 at least in the vicinity of the trench 11A. Subsequently, the polysilicon film 15 is etched and removed using the oxide film 16 as a mask to form a floating gate 17 adjacent to the end of the trench 11A. Next, after the entire surface is oxidized to cover the floating gate 17 and the second gate insulating film 18 is formed so that the shape of the corner at the lower corner of the floating gate 17 is not sharp, A control gate 19 is formed from the upper portion to the side portion of the floating gate 17, and impurities are implanted into the substrate using the floating gate 17 and the control gate 19 as a mask to form source / drain regions 20 and 21. .

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described below. The nonvolatile semiconductor memory device according to one embodiment of the present invention is characterized in that the control gate 19 is formed from the upper part to the side part of the floating gate 17 via the gate insulating film 18 as shown in FIG. This is a split gate type flash memory.

First, as shown in FIG. 1, an SiN film 12 having an opening formed on a semiconductor substrate 11 is used as a mask and thermally oxidized at a temperature of about 900.degree. Oxidation of Silicon) An oxide film 13 is formed. Next, the SiN film 12 and LOCO
After removing the S oxide film 13 to form the groove 11A, as shown in FIG. 2, a first gate insulating film 14 made of a SiO2 film is formed by dry oxidation at about 900.degree.
A polysilicon film 15 of 500 ° is formed. Thereafter, an SiN film (not shown) is deposited, an opening is formed in a predetermined region, and the polysilicon film 15 is thermally oxidized at a temperature of about 900 ° C. to form a LOCOS oxide film 16 in the opening of the SiN film.

Next, using the LOCOS oxide film 16 as a mask, as shown in FIG. 3, for example, in an ECR type etcher, the remaining amount of Cl2 gas at a flow rate of 80 sccm, O2 gas at a flow rate of 5 sccm, a pressure of 5 mTorr, a PF power of 50 W and a magnetron of 250 mA is used. The polysilicon film 15 is etched and completely selectively removed to remove the floating gate 17.
To form At this time, the lower portion of the floating gate 17 is formed so as to be adjacent to the end of the groove 11A.

Next, as shown in FIG. 4, the first gate insulating film 14 formed in a region other than the region immediately below the floating gate 17 is removed using a hydrofluoric acid-based etchant.
Next, by thermally oxidizing the entire surface at a temperature of about 950 ° C., a thermal oxide film having a thickness of about 250 ° is formed, and as shown in FIG. 5, the thermal oxide film integrated with the insulating film 14 and the LOCOS oxide film 16 is formed. A second gate insulating film 18 is formed.

At this time, since the trench 11A is formed in the semiconductor substrate 11 near the floating gate 17, the gate insulating film 18 at the corner KG below the floating gate 17 where reverse tunneling is likely to occur as shown in FIG. The cross-sectional shape of the insulating film 18 between the control gate 19 and the floating gate 17 formed in a later step is not sharp as compared with the conventional floating gate shown in FIG. It can be formed thick and can avoid reverse tunneling failure.

Next, a polysilicon film is formed in a thickness of about 1500 ° and a WSix film is formed in a thickness of about 1500 ° in sequence, and is patterned so as to remain from the upper part to the side part of the floating gate 17 to form a control gate 19. By implanting impurities into the semiconductor substrate 11 using the control gate 19 as a mask to form the source / drain regions 20 and 21, a split gate flash memory as shown in FIG. 6 is formed.

In the above process, even if the control gate 19 is formed on the gate insulating film 18, the shape of the control gate 19 depends on the shape of the gate insulating film 18, which is a base film. Therefore, even if the potential difference between the control gate 19 and the floating gate 17 becomes large after the device is formed, the movement of electrons between them becomes difficult to occur.

As a result, electron injection into the floating gate from the sharp corner of the control gate in the non-selected cell, which has conventionally occurred, can be suppressed as much as possible. For example, a program is erroneously written in the non-selected cell. Can be suppressed as much as possible.

[0020]

As described above, according to the present invention, by forming a groove in a semiconductor substrate near a floating gate forming position, even if a gate insulating film is subsequently formed, a lower corner portion of the floating gate where reverse tunneling easily occurs. The shape of the corner portion of the gate insulating film is not sharper than in the conventional case where the side surface shape of the floating gate is straight.

Therefore, even if a control gate is formed thereon, the corners thereof are not sharp, so that even if the potential difference between the control gate and the floating gate becomes large after the element is formed, even if the potential difference between them becomes large, Electron transfer is less likely to occur. As a result, the injection of electrons into the floating gate from the sharp corner of the control gate in the non-selected cell, which has conventionally occurred, can be suppressed as much as possible. It can be suppressed as much as possible.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a second sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a first cross-sectional view illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 8 is a second cross-sectional view illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 9 is a third sectional view illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 10 is a fourth sectional view showing the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 11 is a fifth sectional view showing the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 12 is a diagram for explaining a problem of a conventional nonvolatile semiconductor memory device.

Claims (2)

[Claims] A step of forming a first selective oxide film on a semiconductor substrate; removing the first selective oxide film to form a groove in the substrate; and forming a first gate insulating film and a polysilicon over the entire surface. Forming a silicon film sequentially, forming a second selective oxide film on at least the vicinity of the trench on the polysilicon film; etching and removing the polysilicon film using the second selective oxide film as a mask; Forming a floating gate by oxidizing the entire surface to form a second gate insulating film, and then forming a control gate from the top to the side of the floating gate; and masking the floating gate and the control gate. Implanting impurities into the substrate to form source / drain regions. The method of production. A step of forming a first selective oxide film on the semiconductor substrate; removing the first selective oxide film to form a groove in the substrate; and forming a first gate insulating film and a polysilicon over the entire surface. Forming a silicon film sequentially, forming a second selective oxide film on at least the vicinity of the trench on the polysilicon film; etching and removing the polysilicon film using the second selective oxide film as a mask; Forming a floating gate so as to be adjacent to the end of the groove; and oxidizing the entire surface to cover the floating gate, and the shape of the corner at the lower corner of the floating gate is sharp. Forming a control gate from the top to the side of the floating gate after forming a second gate insulating film so that the second gate insulating film is not formed; Method of manufacturing a nonvolatile semiconductor memory device characterized by a step of the impurity using the gate and the control gate as a mask injected into the substrate to form the source and drain regions.