JPH1041784A - Tuning device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a simple tuning operation by easily confirming a storage content stored in a memory. SOLUTION: This device is provided with a pulse generating means 1 which generates an up-down signal and a clock signal corresponding to a rotating operation, pulse counter 2 which counts the clock signal from the pulse generating means 1 based on the up-down signal from the pulse generating means 1, memory 4 in which information related with a received program including at least frequency information is stored, switches 21 and 22 which are manually opened and closed, and control means 7 to which the up-down signal and the clock signal from the pulse counter 2. Then, a prescribed value is added to or subtracted from the frequency information designated based on the up-down signal and the clock signal from the pulse generating means 1, and a radio wave with the addition-subtraction processed frequency is received.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel selection device used for a receiver.

[0002]

2. Description of the Related Art Hitherto, as a channel selecting device of a receiver for receiving a radio wave transmitted from a broadcasting station or the like, a device provided with a pulse generating means which is manually operated has been proposed. As a pulse generating means, a rotary encoder is used. The rotary encoder rotates an operation member such as an operation knob to rotate an up / down (U / D) signal corresponding to a rotation direction of the rotation operation member and a clock (CLK) corresponding to a rotation speed of the rotation operation member. ) Generate a signal. The up-down signal and the clock signal are supplied to a control circuit that controls a circuit that determines a reception frequency via a plurality of logic circuits. This control circuit increases or decreases the reception frequency in the direction indicated by the up-down signal at the speed indicated by the clock signal. Therefore, by rotating the rotary operation member of the rotary encoder in an arbitrary direction at an arbitrary speed, the reception frequency is changed in a direction and a speed corresponding to the direction and the speed, and a desired frequency is selected. Will be The control circuit controls the memory circuit by a key switch that is manually operated, and stores a specific frequency in the memory circuit. Further, the control circuit reads out the frequency stored in the memory circuit by operating the key switch, controls the device for determining the reception frequency, and selects the reception frequency for the memory circuit.
This is called preset tuning, in which a specific receiving frequency is stored in a memory circuit in advance, thereby realizing a tuning operation in which the receiving frequency is set only by operating a key switch without using a rotary encoder. is there. Further, the control circuit controls a display unit that displays the set reception frequency.

[0003]

By the way, in the above-mentioned tuning apparatus, in order to confirm the reception frequency stored in the memory circuit, the reception frequency stored in the memory circuit called the memory scan display provided in the control circuit is checked. The function of sequentially displaying the frequency in accordance with the address on the memory circuit is used. In this function, the time required for the sequential display is always constant because the direction and speed of the sequential display are set in advance under a constant condition. Therefore, the contents stored in the memory circuit cannot be displayed in any direction and at any speed as needed.

The reception frequency stored in the memory circuit can be displayed by operating a key switch. However, in order to confirm the stored reception frequency, it is necessary to operate many key switches. Therefore, the operation becomes complicated. In particular, in a channel selection device that stores a large number of reception frequencies, it is necessary to operate key switches according to the number of the stored reception frequencies, which further complicates the operation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a channel selection device that can quickly and easily check the contents stored in a memory and can easily perform a channel selection operation.

[0006]

According to the present invention, there is provided a channel selecting apparatus comprising: a pulse generating means for generating an up / down signal and a clock signal in accordance with a rotation operation; and a pulse generator based on the up / down signal from the pulse generating means. A pulse counter for counting a clock signal from the generating means, a memory storing information on a received program including at least frequency information, a switch which is manually opened / closed, and an up / down signal and a clock signal from the pulse counter are supplied. Control means for performing the control. Then, the control means adds or subtracts a predetermined value to the designated frequency information based on the up / down signal and the clock signal from the pulse generation means, and receives a radio wave of the adjusted frequency.

Further, the tuning apparatus according to the present invention comprises a display means for displaying the information read from the memory and the frequency being received.

This tuning apparatus receives a radio wave of a desired frequency based on an up / down signal and a clock signal obtained by operating a pulse generating means, and further relates to a received program read from a memory. Information and the frequency being received are displayed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A tuning apparatus according to the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the tuning apparatus according to the present invention includes a rotary encoder 1 as pulse generating means. A pulse counter 2 and a decoder 3 are sequentially connected to the rotary encoder 1.
And a control circuit 6 to which the display circuit 5 is connected via a switching circuit 7. In this tuning apparatus, the control circuit 6 performs a tuning operation by controlling a frequency determination circuit 9 provided in the receiver body 8.

The rotary encoder 1 has a rotary operation member 10 that is rotated by manual operation. When the rotary operation member 10 is rotated, the rotary encoder 1 is rotated as shown in FIG.
Generates various types of pulse signals. That is, an up / down signal U / D as shown in FIG. 2 is output from the up / down signal output terminal 11, and a clock signal CLK as shown in FIG. 2 is output from the clock signal output terminal 12. In FIG. 2, the section from A to B is the rotation operation member 1.
0 indicates an output when no operation is performed, a section from B to C indicates an output when the rotary operation member 10 is rotated clockwise, and a section from C to D indicates an output when the rotary operation member 10 is counterclockwise. It shows the output when rotating in the direction.

Here, when the rotary operation member 10 is rotated in any direction, an up / down signal U / D corresponding to the rotation direction of the rotary operation member 10 is output from the up / down signal output terminal 11, and a clock signal is output. The output terminal 12 outputs a clock signal CLK corresponding to the rotation speed of the rotation operation member 10. The up / down signal U / D and the clock signal CLK are input to the pulse counter 2 via the input terminals 13 and 14, and further input to the switching circuit 7. The pulse counter 2 to which the up / down signal U / D and the clock signal CLK are input outputs a signal representing a 4-bit binary number from an output terminal 15 thereof. The direction of increase or decrease of the binary number of this output signal is determined by the up / down signal U / D input from the input terminal 13, and the input terminal 1
4 is counted. The signal output from the output terminal 15 is input to the input terminal 16.
Is input to the decoder 3 via the. This decoder 3
An output terminal 17 composed of ten terminals is provided. The output terminal 17 corresponds to a numerical value obtained by converting a 4-bit binary number represented by a signal input to the input terminal 16 into a decimal number representing any one of numbers 1 to 10. A voltage is output to one of the ten terminals of the output terminal 17. The output of the output terminal 17 is input to the switching circuit 7. A switching circuit 7 to which an output from an output terminal 17, an up / down signal U / D which is an output of the rotary encoder 1, and a clock signal CLK are input.
Has input terminals 18, 19, and 20 to which the above three types of signals are input.

The switching circuit 7 has two input terminals 23 and 24 to which first and second switches 21 and 22 which are manually operated are respectively connected. Switching circuit 7
Has a plurality of input terminals 18, 19, 20, 23, 24;
It is composed of a plurality of logic circuits, ie, a tri-state gate, an AND gate, and a NOT gate. The plurality of logic circuits are controlled by signals input from input terminals 18, 19, 20, 23, and 24. The input terminal 18 is composed of ten terminals, each of which is a tri-state gate 25,.
25, a preset input terminal 26 of the control circuit 6,
..26. Further, the input terminal 18 is connected to program input terminals 28,... 28 of the control circuit 6 via tri-state gates 27,. The input terminal 19 is connected to a tri-state gate 29 and a knot gate 30, respectively. Not gate 30 is connected to tri-state gate 31. The tri-state gate 29 is connected to the frequency up terminal 32 of the control circuit 6, and the tri-state gate 3
1 is connected to the frequency down terminal 33 of the control circuit 6.
The input terminal 20 includes an AND gate 34 and an AND gate 35.
Connected to each other. The input terminal 23 is connected to an AND gate 34 and a NOT gate 36, respectively. The input terminal 24 is connected to each of the AND gate 34, the AND gate 37, and the NOT gate 38.
The NOT gate 36 is connected to the AND gate 35, and the AND gate 35 is connected to the AND gate 37. The NOT gate 38 is connected to the tri-state gate 27, the AND gate 34 is connected to the tri-state gate 25, and the AND gate 37 is connected to the tri-state gates 29 and 31.

When the second switch 22 is open and the input terminal 24 is at "L" level, the AND gate 34
And the AND gate 37 are shut off, and the tri-state gates 29 and 31 controlled by the output of the AND gate 37 and the tri-state gates 25,... 25 controlled by the output of the AND gate 34 are shut off. At this time, since the input terminal 24 is at the "L" level, the output terminal of the NOT gate 38 is at the "H" level, and this output controls the tri-state gates 27,. 27 is made conductive.
At this time, the rotary operation member 10 of the rotary encoder 1
Is operated, the up / down signal U / D and the clock signal C
When LK is generated, the output from the decoder 3 is input to one of the tri-state gates 27,... 27 via the input terminal 18, passes through the tri-state gate 27, and .. 28
Is input to one of.

Next, when the second switch 22 is closed and the input terminal 24 is at "H" level, this input is input to the AND gate 34, the AND gate 37, and the NOT gate 38. Since the input side of the NOT gate 38 is at the "H" level, the output side is at the "L" level, and the tristate gates 27,... At this time, when the first switch 21 is closed and the input terminal 23 is at “H” level, this input is input to the AND gate 34 and the NOT gate 36. When the rotation operation member 10 of the rotary encoder 1 is operated at this time, the clock signal CLK is input to the AND gate 34 via the input terminal 20. AND gate 34 has input terminals 23 and 24
Side is at the “H” level, so that the clock signal CL
Let K pass. The clock signal CLK passed through the AND gate 34 is supplied to the tri-state gates 25,.
To open and close according to the pulse of the clock signal CLK. The output of the decoder 3 is pulsed by opening and closing the tri-state gates 25,... 25, and is input to one of the preset input terminals 26,. At this time, since the input side of the NOT gate 36 is at the "H" level, the output side is at the "L" level, the output sides of the AND gates 35 and 37 are at the "L" level, and the tristate gates 29, 31
Is shut off.

Next, when the second switch 22 is kept closed and the first switch 21 is opened and the input terminal 23 goes low, the output of the AND gate 34 goes low. Tri-state gate 25, ...
25 is shut off. Since the input side of the NOT gate 36 is at “L” level, the output side is at “H” level, and this output is input to the AND gate 35. When the rotation operation member 10 of the rotary encoder 1 is operated, the clock signal CLK is input to the AND gate 35 via the input terminal 20. The AND gate 35 allows the clock signal CLK to pass because the output side of the NOT gate 36 is at the “H” level, and the clock signal CLK is input to the AND gate 37. Since the input terminal 24 is at the “H” level, the AND gate 37 outputs the clock signal CL.
The clock signal CLK controls the tri-state gates 29 and 31 and opens and closes according to the pulse of the clock signal CLK. At this time, the up / down signal U / D from the rotary encoder 1 is input to the tristate gate 29 and the knot gate 30 via the input terminal 19. When the up / down signal U / D is in the state of section B to C in FIG. 2, this input is pulsed by opening and closing the tristate gate 29 and input to the frequency up terminal 32 of the control circuit 6, and Signal U /
When D is in the state from C to D in FIG. 2, the output side of the knot gate 30 becomes “H” level, and this output is pulsed by opening and closing of the tri-state gate 31, and the frequency down terminal of the control circuit 6. 33.

The control circuit 6 includes the program input terminals 28,... 28 and the preset input terminals 26,.
.. And a frequency up terminal 32 and a frequency down terminal 33. When there is an input to one of the program input terminals 28,... 28, the control circuit 6 is designated by the address corresponding to the input terminal and the memory circuit 4
The information about the received program, such as the time as the first information and the frequency information as the second information, stored in the memory is read out, output to the display circuit 5, and displayed on the display unit.

When one of the preset input terminals 26,... 26 receives an input, the control circuit 6 designates the memory circuit 4 by an address corresponding to the input terminal.
The frequency control circuit 9 controls the frequency determination circuit 9 to receive the reception frequency stored in the display device and receive the radio wave of the frequency, and outputs the read frequency to the display circuit 5 to display it on the display unit.

Further, when there is an input to the frequency up terminal 32 or the frequency down terminal 33, the control circuit 6 controls the frequency determination circuit 9 in accordance with the input terminal to set a predetermined value to the reception frequency. The adjusted frequency is displayed on the display circuit 5.

The control circuit 6 has key switches 39,.
.. 39 are connected in parallel with the respective connections from the tri-state gates 25,... By operating the key switches 39,... 39, the key switches 39 can be used without using the rotary encoder 1.
And reads the frequency stored in the memory circuit 4 designated by the address corresponding to the address, controls the frequency determination circuit 9 to receive the radio wave of the frequency, outputs the frequency to the display circuit 5, and displays the frequency on the display unit. Let it.

The tuning device according to the present invention having the above-described structure is configured by the first and second switches 21 and 22.
An operation of displaying information on a received program stored in the memory circuit 4, an operation of receiving radio waves of a frequency stored in advance, and adding or subtracting a predetermined value to the reception frequency, and Radio wave reception operations can be selected, and in these operations, control corresponding to the direction and speed at which the rotary operation member 10 of the rotary encoder 1 is operated is performed. The operation for receiving the radio wave of the frequency previously stored in the memory circuit 4 can also be performed by the key switches 39,.

Next, as shown in FIG. 3, even if one microprocessor 40 is used instead of the one connected with the pulse counter 2, the decoder 3, the memory circuit 4, the control circuit 6, and the switching circuit 7, The same operation as the device can be performed. The microprocessor 40 has an input terminal 13 to which the up / down signal U / D is input, an input terminal 14 to which the clock signal CLK is input, an input terminal 23 to which the first switch 21 is connected, and a second switch 22. It has four input terminals of an input terminal 24 to be connected, and has an output terminal 41 for outputting to the display circuit 5 and an output terminal for outputting to the frequency determination circuit 9
Are provided.

As shown in the flow chart of FIG. 4, the microprocessor 40 first receives the clock signal CLK at the input terminal 14, and at steps 101 and 102, generates the CLK signal indicated by E in FIG. Detect negative edges. Next, in step 103, the level of the input terminal 24 is detected. If the input terminal 24 is at the "L" level, then at step 104, the up / down signal U / D input to the input terminal 13 is detected, and this up / down signal U / D is at the "H" level. In step 105, of the information on the received program such as the time and frequency value stored in the memory circuit in the microprocessor 40 in step 105, 1 is added to the address in the memory circuit of the information displayed last time. The information corresponding to the address of the result is read out, input to the display circuit 5 in step 107, and displayed on the display unit.

If the up / down signal U / D is at the "L" level, at step 106, among the information on the received program such as the time and frequency value stored in the memory circuit in the microprocessor 40, The information corresponding to the address is read by subtracting 1 from the address of the previously displayed information in the memory circuit, and is input to the display circuit 5 in step 107 to be displayed on the display unit.

After detecting the negative edge of the clock signal CLK in steps 101 and 102, if the input terminal 24 is at the "H" level in step 103, then the level of the input terminal 23 is determined in step 108. Is detected. When the input terminal 23 is at “H” level,
Next, in step 109, the up / down signal U / D input to the input terminal 13 is detected, and if the up / down signal U / D is at "H" level, step 11 is executed.
At 0, 1 is added to the address in the memory circuit of the previously used information from among the frequencies stored in the memory circuit in the microprocessor 40, and the frequency corresponding to the address is read. The frequency is input to the display circuit 5 and is displayed on the display unit. If the up / down signal U / D is at the "L" level, it is stored in the memory circuit in the microprocessor 40 in step 111. Of the frequencies, 1 is subtracted from the address of the previously used information in the memory circuit, the frequency corresponding to the address is read out, and the frequency is input to the display circuit 5 in step 112 and displayed on the display unit.

At steps 101 and 102, the clock signal C
After detecting the negative edge of LK, step 10
In step 3, the input terminal 24 is at the "H" level and
When the input terminal 23 is at the “L” level,
In step 113, the up / down signal U / D input to the input terminal 13 is detected, and the up / down signal U / D is detected.
If D is at the "H" level, a predetermined value is added to the frequency of the radio wave currently received at step 114, and the frequency determination circuit 9 is controlled so as to receive the radio wave of the resulting value. The output is output from the output terminal 41, and the received frequency is input to the display circuit 5 at step 115 to be displayed on the display unit. If the up / down signal U / D is at the "L" level, then at step 116 A predetermined value is subtracted from the frequency of the radio wave received at step (1), an output for controlling the frequency determination device 9 is received from the output terminal 41 so as to receive the radio wave of the resulting frequency, and
Then, the received frequency is input to the display circuit 5 and displayed on the display unit.

[0027]

As described above, according to the tuning apparatus of the present invention, the information stored in the memory is controlled by the control means for selectively reading out the information on the received program such as the frequency information stored in the memory. Information about the received program stored in the memory in the up direction or the down direction according to the up / down signal of the pulse generating means for generating the up / down signal and the clock signal according to the rotation operation. Since reading is performed, a quick tuning operation can be realized, and the operability of the tuning operation can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a tuning apparatus according to the present invention.

FIG. 2 is a waveform diagram showing an output of a rotary encoder included in the channel selection device according to the present invention.

FIG. 3 is a connection diagram of a microprocessor constituting another embodiment of the tuning apparatus according to the present invention.

FIG. 4 is a flowchart showing a tuning operation of a tuning device using a microprocessor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Rotary encoder, 2 ... Pulse counter, 3 ... Decoder, 4 ... Memory circuit, 6 ... Control circuit, 21 1st switch, 22 2nd switch.

Claims (2)

[Claims] A pulse generator for generating an up / down signal and a clock signal in accordance with a rotation operation; a pulse counter for counting a clock signal from the pulse generator based on an up / down signal from the pulse generator; A memory in which information on a received program including at least frequency information is stored; a switch that is manually opened / closed; and control means to which the up / down signal and the clock signal from the pulse counter are supplied; The channel selecting device adds or subtracts a predetermined value to designated frequency information based on an up / down signal and a clock signal from the pulse generating unit, and receives a radio wave of the adjusted frequency. 2. The channel selecting device according to claim 1, wherein said device further comprises display means for displaying information read from said memory and a frequency being received.