JPS63266931A - Radio receiver having clock function - Google Patents

Abstract

PURPOSE:To change over the display to the display with lower priority even if no operation of radio switch or time switch is applied by changing over the display from the display with high priority to the display with lower priority in response to the operation of a recall switch. CONSTITUTION:When a recall switch 341 is closed with the state of frequency display priority, a timer counter 501 is reset through a gate circuit 519. Then an output '0' of the timer counter 501 is inputted to a command signal output circuit 509 via a gate circuit 518, a Q output of the FF circuit 502, a gate circuit 512 and a FF circuit 503, and the output of the command signal output circuit 509 goes to '1' to command the clock display. While the recall switch 341 is closed and the timer counter 501 keeps its count, the state continues and when the count of the timer counter 501 is expired, the output of the circuit 509 goes to '0' to indicate the frequency display.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radio receiver having a clock and a frequency display function of a radio receiver. This is used to control display switching between frequency display and clock display when both can be displayed.

[Prior art and problems to be solved by the invention]

Conventionally, when displaying both a frequency and a clock on the display of a car radio, the clock was always set to be displayed, and (1) when the power to the radio receiver was cut off, , the clock will be displayed all the time, and when the radio receiver is turned on afterwards, the frequency will be displayed for a certain period of time. When these operations are completed, the display will remain in the clock display state for a certain period of time, and after these operations (1) and (2), the clock display state will be maintained at all times. It has become.

By the way, users of radio receivers have various requirements regarding the use of their radio receivers. One such request is simply checking a low-priority display, but as in the past, it is possible to temporarily switch to that display by operating a switch, etc. that corresponds to the low-priority display. In some cases, incorrect configuration may result in erroneous operation.

That is, when selecting a station using the conventional radio receiver described above, the frequency i number is displayed in response to a channel selection operation, such as raising or lowering the reception frequency, and the user can tune while checking the frequency. However, if you simply want to check the current reception frequency, if you perform a tuning operation to check the frequency, the reception frequency will change depending on the selection. Therefore, it is not possible to check the frequency that is currently being received. The present invention aims to solve these problems.

[Means for solving problems]

In the present invention, priority is given to the time switch for adjusting the time, the radio switch for operating the radio, the clock display, and the frequency display, and normally the time or frequency with a higher priority is displayed, and the time In a radio receiver having a frequency display function of a clock and a radio receiving section, which is equipped with display control means for displaying a low priority display for a predetermined period of time in response to an operation regarding a low priority display using a switch or a radio switch, Accordingly, there is provided a radio receiver having a clock function, characterized in that a recall switch is provided which acts on the display control means to display the low priority display for a predetermined period of time.

〔Example〕

A display control device as one embodiment of the present invention is applied.

A basic circuit diagram of a radio receiver is shown in FIG. 1st
The display device 9 in the circuit shown in the figure displays numbers using a seven-element display figure 91 as shown in FIG. 2, for example. The display is performed by sharing the display device 9, for example, to show 12:30^M (or PM).

The radio receiving circuit 1 includes a receiving input circuit 11, an integrated circuit phase-locked loop unit 12, a low-pass filter 13, a radio output circuit 14, and a speaker 15.

The tuning circuit 2 that supplies output to the phase-locked loop section includes a manual and d search operation holding circuit 41, an operation holding circuit 42, an operation holding circuit 43, and Band selection circuit 44
One of the outputs of the 0 tuning circuit 2 which receives the output signal is the output of the 0 frequency calculation circuit 6 which is supplied to the frequency calculation circuit 6,
The output of the clock counting circuit 7 based on the signal of the crystal oscillation XTL is supplied to the display selection circuit 8. The output of the display control circuit 5 receives the output signals of the operation holding circuit 41, the operation holding circuit 42, the operation holding circuit 43, and the band selection circuit 44, and is operated by the recall switch 341 and the clock/frequency priority switching switch 343. Display selection circuit 8 depending on the signal
is controlled. (The recall switch 341 is a switch for responding to a request to display the opposite side of what is currently being displayed.) The display device 9 is driven by the output signal of the display selection circuit 8.

A specific circuit diagram of the circuit of FIG. 1 is shown in FIG. 3, and a detailed circuit diagram of the display control circuit 5 in the circuit of FIG. 2 is shown in FIG. The circuit elements shown in FIGS. 3 and 4 will be explained as follows.

A0 phase-locked loop synthesizer type tuning circuit 12: Receives the received signal from the receiving input circuit 11, is controlled by the tuning circuit, and supplies an output to the low-pass filter.

B. Data selector 22: Generates output in synchronization with the 4-digit signal from the signal generator 21, and transfers the frequency division ratio N made up of BCD and 4 bits to the phase-locked loop tuning circuit 12 in parallel. I do.

BCD programmable up/down counters 241, 242, and 243: Perform up/down counting using signals from the decoder circuit 23, and take in preset data using signals from the random access memory 25. Change the upper and lower limits of the band.

4-bit programmable up/down counter 244: Outputs the most significant digit of the division ratio N value and a reference switching signal.

16-bit digital comparator 28: Determines whether the frequency division ratio N value has reached the upper or lower limit of the band.

Power, calculation circuit 6: A circuit that calculates the reception frequency f from the frequency division ratio N value.

When f is the reference frequency, f is the reception frequency, fo is the local oscillation frequency, and f is the intermediate frequency, the following relationship holds true. f,=N-f,,f,=f,±f5 km display device 9
: A device that displays either the receiving frequency or clock time.

4-bit or 16-bit random access
Memory 25: Random access memory (RA) that can be read and written freely.
M), which stores the upper or lower limit N value of the band, and outputs an output when the band limit value is reached during manual sweeping. It also outputs the contents of the preset. Also, when switching bands, the previous state of that band is output.

q. Read or write control circuit 26: When the write switch is closed and the preset contents are rewritten, and when the upper and lower limits of the band are reached, the next limit N value to be received is randomly accessed. Write to memory 25.

Thereby, the random access memory 25 is controlled.

Ko, long/medium wave selector 29: Automatically switches between long wave and medium wave bands.

Operation holding circuit 41: Holds manual operation up or down, search operation up or down, and determines priority.

Operation holding circuit 42: Holds the write state and is released by the preset key.

The operation holding circuit 43 maintains the preset state by the nib reset switches 331 to 33n.

C. Band selection circuit 44: The key is to logicalize the manually inputted bandwidth information.

Long/medium wave power selection circuit 291: Switches the power for the long wave tuner section and the medium wave tuner section according to the logic of the long/medium wave selector 29.

Sweep control decoder 23: According to the sweep clock, the BCD, 4-pin programmable up-down counter is switched up and down by the number of pulses.

When searching, the N value is automatically varied by outputting multiple keys from the signal generator 21, and when searching manually, the N value is varied by outputting as many times as the on/off of the manual key switch. let

H6 display control circuit 5: When the operation switch is pressed, a clock or frequency corresponding to the selected display is selected, and the result is output to the display signal selection circuit 8 as a clock/frequency display instruction signal.

Clock counting circuit 7: Sequentially divides and counts the clock reference signal based on the reference pulse.

Te0 display signal selection circuit 8: Selects the output of either the frequency calculation circuit 6 or the clock counting circuit 7 according to the clock/frequency display instruction signal sent from the display control circuit 5, and outputs the result to the display device 9. .

A specific circuit configuration example of the display control circuit 5 in the circuit of FIG. 3 is shown in FIG.

C. Timer counter 501: Counts time T seconds. During counting, the output is "0", and after counting is finished, the output is "1".

Flip-flop 7 flip circuit 502: Normally it is a through operation (input and output are equal), but when there is a "display priority switching" signal, it performs an inversion operation (input is inverted and output) and then latches, and the timer counter 501 When counting is completed, the latch is released and the through operation is resumed.

F, flip-flop circuit 503: Normally it operates through (input and output are equal), but if a trigger signal is generated by closing the recall switch while the timer counter 501 is counting, it inverts and then latches, and the timer counter 501 When counting is completed, the latch is released and the through operation is resumed.

1 Display priority switching detection circuit 526: Generates a pulse regardless of whether the display priority switch 343 is switched to clock or frequency.

E. Search and scan state holding circuit 505: Consists of a Frithop flop array. Outputs a "low" level signal when in the on state. It is reset when a receive (iF) signal is input in the search up/down state. When the search up/down switch is in the start state, any operation of any of the switches 331 to 33n1, 311, 312, and switch 351 will reset the search.

The scan state is toggled or reset.

Search amplifier down switch 313, 314, manual switch - 311° 312, band selection switch 35
It will be reset if any of the operations in step 1 are performed. When reset, it outputs a "high" level signal.

The instruction signal output circuit 509 consists of a D-type flip-flop circuit having preset (PSET) and clear (CLR) inputs.

Clear input has priority over preset input. During a clock adjustment operation or when the radio power is cut off, the preset input becomes a "high" level, and the output signal becomes a "high j level" regardless of the input signal from the circuit 503.

On the other hand, when a series of tuning operations are performed, such as searching up/down, scanning, tuning, manual up/down, band switching, or powering on the radio receiver, the clear input becomes "high" level. The output signal will be at a "low" level regardless of the input signal from circuit 503.

Mi1 time limit circuit 510: Prioritizes display of open wave number for a certain period of time after band switching or radio receiver power is turned on, and is then opened.

When the power to the radio receiver is turned on, the output is enabled, and when the power to the radio receiver is turned off, the output is at a "high" level or is open.

Gate circuits 512 to 522: Gate circuits 512 to 514 are 3-state buffer circuits, gate circuit 515 is a 3-state AND gate circuit, gate circuit 516 is a 3-state inverter circuit, and gate circuit 517
519 is an inverter circuit, gate circuit 520 is a Nantes gate circuit, and circuit 521 is a clock adjustment circuit.

By using the circuits shown in FIGS. 11, 3, and 4, the operations described below are performed.

1. [When a tuning operation is performed with priority given to the clock display, the open wave number is displayed during tuning and for a certain period of time (T seconds) after the operation is released, and then the clock is displayed.] For example, when the tuning switch 331 is closed, During this time, the operation holding circuit 43 holds the state, and the output of the gate circuit 511 becomes "0", passing through the gate circuit 514 to reset the timer counter 501, and passing through the gate circuit 516 to clear the instruction signal output circuit 509. The input signal is rl
J, the instruction signal output circuit 509 is cleared, and the output signal of the instruction signal output circuit 509 becomes "0", instructing frequency display.

When the channel selection switch 331 is opened, the In operation holding circuit 43
The output of the timer counter 501 becomes rlJ, and the output signal "0" of the timer counter 501 is inputted to the instruction signal output circuit 509 via the gate circuit 513 and the flip-flop circuit 503,
The output of 09 becomes "0" and instructs frequency display. This state continues until the timer counter 501 finishes counting (for T seconds), and when the timer counter 501 finishes counting, the output signal "1" of the timer counter 501 is transferred to the 100 output of the flip-flop circuit 502, the gate circuit 513, and the flip-flop circuit. The signal is inputted to the instruction signal output circuit 509 via 503, and the output of the instruction signal output circuit 509 becomes rlJ, which instructs clock display.

2. [Clock display is given priority and the clock is always displayed even if the clock adjustment operation is performed] When the clock adjustment switch in the clock adjustment circuit 521 is closed, the output of the clock adjustment circuit 521 becomes "0" and passes through the gate circuit 515. The timer counter 501 is reset, and the preset input signal of the instruction signal output circuit 509 passes through the gate circuit 517 and the gate circuit 522 and becomes "1".
'', the instruction signal output circuit 509 is preset and the output signal becomes ``1'', instructing clock display. However, since the gate circuit 515 is in the prohibited state, the timer counter 5
01 is not reset. When the clock adjustment switch is opened, the output signal of the timer counter 501 "1" is the 100 output of the flip-flop circuit 502, the instruction signal output circuit 50 via the gate circuit 513 and the flip-flop circuit 503.
9, and the output of the instruction signal output circuit 509 is "1".
will appear to indicate the clock display.

3. [When the recall switch is closed with priority given to the clock display, the sentencing wave number is displayed for a certain period of time (1 second) while the recall switch is closed and after the recall switch is opened, and then the clock is displayed] When the recall switch 341 is closed, the gate circuit 519
The timer counter 501 is reset through.

The output signal rOJ of the timer counter 501 is inputted to the instruction signal output circuit 509 via the 100 output of the flip-flop circuit 502, the gate circuit 513, and the flip-flop circuit 503, and the output of the instruction signal output circuit becomes rOJ, which instructs frequency display. This state continues while the recall switch is closed and the timer counter 501 is counting (for T seconds), and when the timer counter 501 finishes counting, the timer counter 501
When the output of 01 becomes "1", the output is inputted to the instruction signal output circuit 509 via the 100 output of the flip-flop circuit 502, the gate circuit 513, and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes "1". will appear to indicate the clock display.

4. [If the recall switch is closed again during a period in which a low-priority display is being performed for a predetermined period of time, a high-priority display will be performed from the moment the recall switch is closed.] While the timer counter 501 is counting, the recall switch 34
1 is closed, the timer counter 501 is reset, and the output "0" of the timer counter 501 becomes the signal "0" at the Q output and the hundred output of the flip-flop circuit 502, respectively.
” and rlJ are latched, the gate circuit 51
Depending on the state of the white display priority switch 343 of 2 or 513, a signal "0" or "1" is input to the flip-flop circuit 503 through either the signal rOJ or rlJ.

The flip-flop 503 inverts and latches the input for the trigger signal during counting by the timer counter 501, and the signal rlJ or "0" is output to the instruction signal output circuit 509. is input to instruct the display priority switch 343 to display the corresponding display. In the flip-flop circuit 502 and the flip-flop circuit 503, the timer counter 501 latches it during the counting operation and releases the latch when the counting is completed.

In this way, by operating the recall switch again during a period when a low priority display is being performed, the display is immediately switched to a high priority display, so even before the low priority display ends. Displays can be easily switched, further improving operability.

5. [If a clock adjustment operation is performed with frequency display priority, the clock is displayed for T seconds during the clock adjustment and after the clock adjustment is completed, and then the frequency is displayed] While the clock adjustment switch in the clock adjustment circuit 521 is closed. The output of the clock adjustment circuit 521 becomes rOJ,
The timer counter 501 is reset through the gate circuit 515, and the gate circuit 517 and the gate circuit 522
The preset input of the instruction signal output circuit 509 is
1'', the instruction signal output circuit 509 is preset, and the output signal becomes rlJ, instructing clock display. This state continues while the clock adjustment switch is closed, and when the clock adjustment switch is opened, the output of the clock adjustment circuit 521 becomes "1".
”, the output signal “0” of the timer counter 501 is input to the instruction signal output circuit 509 via the gate circuit 518, the Q output of the flip-flop circuit 502, the gate circuit 512, and the flip-flop circuit 503, The output becomes "1" and instructs the clock display. This state continues until the timer counter 501 finishes counting (1 second), and when the timer counter 501 finishes counting,
The output “1” of the timer counter 501 is the gate circuit 518
, Q output of flip-flop circuit 502, gate circuit 5
12. The signal “0” is input to the instruction signal output circuit 509 via the flip-flop circuit 503 and the instruction signal output circuit 5
The output of 09 becomes "0" and instructs frequency display.

6. [Always display the frequency even if you perform a tuning operation with frequency display priority] For example, while the tuning switch 331 is closed, the instruction signal output circuit 509 is cleared, and the instruction signal output circuit 50
9 outputs "0" to instruct frequency display. However, since the gate circuit 514 is in a prohibited state, the timer counter 50
1 is not reset. This state continues while the channel selection switch 331 is closed, and when the channel selection switch 331 is opened, the output signal rlJ of the timer count 501 is output from the gate circuit 518, the Q output of the flip-flop circuit 502, and the gate. "0" is input to the instruction signal output circuit 509 via the circuit 512 and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes "0", instructing frequency display.

7. [When the recall switch is closed with frequency display priority, the clock is displayed for T seconds while the recall switch is closed and after the recall switch is opened, and then the frequency is displayed] Recall switch 3
41 is closed, the timer counter 501 is reset through the gate circuit 519. timer counter 501
The output "0" is input to the instruction signal output circuit 509 via the gate circuit 518, the Q output of the flip-flop circuit 502, the gate circuit 512, and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes "1". Instructs clock display. This state continues while the recall switch 341 is closed and the timer counter 501 is counting, and when the timer counter 501 finishes counting (1 second), the output "1" of the timer counter 501 is transferred to the gate circuit 518, the Q output of the flip-flop circuit 502, and the gate The output of the instruction signal output circuit 509 via the circuit 512 and the flip-flop circuit 503 becomes "0" to instruct frequency display.

8. [When switching from clock display priority to frequency display priority, frequency display is performed from the moment of switching] When switching is performed using the display priority changeover switch 343, a pulse is selected from the display priority changeover detection circuit 504 and the gate circuit 520 The timer counter 501 is reset through. The output "0" of the timer counter 501 is input to the flip-flop circuit 502 through the gate circuit 51B, and in the flip-flop circuit 502, the output signal rlJ of the gate circuit 51B is inverted to "0" by a trigger pulse, and then latched. , outputs the latched result from the Q output to the gate circuit 512. This output signal rOJ is input to the instruction signal output circuit 509 via the gate circuit 512 and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes rOJ, which instructs frequency display. Note that the flip-flop circuit 1 releases the latch when the timer count 501 ends, and the output of the gate circuit 518 becomes the gate circuit 51.
is equal to 2 inputs.

9. [When switching from frequency display priority to clock display priority, the clock display is performed from the moment of switching] When switching is performed using the display priority changeover switch 343, a pulse from the display priority changeover detection circuit 504 passes through the gate circuit 520. The timer counter 501 is reset. The output of the timer counter 501 is “0” and below is the flip-flop circuit 502.
The signal is input to the R input of the flip-flop circuit 502 and is inverted by the trigger pulse to become rlJ and then latched.The latched signal is sent from the 100 output to the gate circuit 513 and the flip-flop circuit 503 to the instruction signal output circuit 50.
9 is input. The output of the instruction signal output circuit 509 is rl
J and instructs the clock display. Note that the flip-flop circuit 502 receives the count end signal "1" of the timer counter 501.
The latch is released at , and the output signal of the timer counter 501 and the input No. 8 of the gate circuit 513 become equal.

10. [A clock is displayed when the radio receiver power is cut off] When the radio receiver power is cut off by the switch 342, the signal passes through the gate circuit 522 and is sent to the signal output circuit 5.
The present input of 09 is set to "1", and the signal output circuit 50
9 is preset and instructs clock display regardless of the operation of the channel selection switch. At this time, even if the channel selection switch is operated, it has no effect because the gate circuit 516' is in the inhibited state.

11. [When switching the band and turning on the power of the radio receiver, the frequency is displayed for T seconds, and after that, the display according to the display priority is performed] Band switching by the band changeover switch 351 or the radio receiver power switch 342 or the radio receiver When the power is turned on, the pulse signal based on this becomes a trigger pulse to the timer circuit 510, and the timer circuit 510 prioritizes the frequency display for T seconds, and at the same time, the gate circuit 51
5, the timer counter 501 is reset.

In addition to the above, in the circuits shown in Figures 1, 3, and 4, when the operation switches on the tuning side and the watch side are pressed simultaneously, the operation on the tuning side takes priority over the operation on the watch side. It can be configured so that it is performed.

〔Effect of the invention〕

According to the present invention, since the display is configured to switch from a high-priority display to a low-priority display in response to the operation of a recall switch, the display can be switched from a high-priority display to a low-priority display without operating a radio switch, time switch, etc. This makes it possible to prevent accidental scratching when switching the display.

[Brief explanation of drawings]

Fig. 1 is a basic circuit diagram of a radio receiver to which a display control device as an embodiment of the present invention is applied, Fig. 2 is a diagram showing a display device in the circuit of Fig. 1, and Fig. 3 (A). (
B) is a circuit diagram showing a specific configuration of the circuit of FIG. 2, and FIG. 4 is a detailed circuit diagram of a display control circuit in the circuit of FIG. 2. l...Radio reception circuit, 11...Reception input circuit,
12... Phase-locked loop synthesizer, 13...
・Low pass filter, 14...Radio output circuit, 15
...Speaker, 2...Tuning selection circuit, 21...
Signal generator, 22...Data selector, 23...
・Decoder circuit, 241-244...Counter, 2
5... Random access memory, 26... Read/write control circuit, 27... Read only memory. 28... Comparator, 29... Long/medium wave selection circuit, 311, 312... Manual down/up switch, 313
, 314...Search descending/increasing switch, 32...Writing (memory) switch, 331.33n...Channel selection switch, 341...
...Recall switch, 342...Receiver power switch, 343...Clock/frequency priority display changeover switch, 35
1, 352...Band selection switch, 41, 42,
43... Operation holding circuit, 44... Band selection circuit,
5...Display control circuit, 501...Timer counter, 502, 503...Flip-flop circuit, 509...
...Indication signal output circuit, 510...Flip-flop circuit, 511-520...Gate circuit, 521...Clock adjustment circuit, 524...Delay circuit,
525...Radio receiver power supply opening/closing detection circuit, 526.
...Display priority switching detection circuit, 6...Frequency calculation circuit, 7...Clock counting circuit, 8
. . . Display signal selection circuit, 9 . . Display device, 91 . . . Display figure.

Claims (1)

[Claims] 1. Priority is given to a time switch for adjusting the time, a radio switch for operating the radio, a time display and a frequency display, and usually the time or frequency with a higher priority is displayed. In addition, in a clock and a radio receiver having a frequency display function of a radio receiving section, the clock is equipped with display control means for displaying a low priority display for a predetermined period of time in response to an operation related to a low priority display using a time switch or a radio switch. , A radio receiver having a frequency display function of a watch and a radio receiver, characterized in that a recall switch is provided which acts on the display control means when operated to display the low priority display for a predetermined period of time. . 2. The radio according to claim 1, wherein when the recall switch is operated during a period in which a display with a low priority is being displayed, the display is immediately switched to a display with a high priority. Receiving machine.