JPH0145073B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radio receiver having a time and frequency display function of a radio receiving section. The device according to the present invention is used, for example, to control display switching between the frequency display and the clock display when the display section of a car radio is capable of displaying both a frequency display and a clock display.

[Prior art and problems to be solved by the invention]

Conventionally, when displaying both a frequency and a clock on a car radio display, the clock is always displayed. (1) When the power to the radio receiver is cut off, the clock is always displayed When the radio receiver is turned on after that, the frequency will be displayed for a certain period of time, and (2) the frequency will be displayed while the radio receiver is being tuned. The clock display state will be maintained for a certain period of time, and when these operations are completed, the display will be maintained for a certain period of time, and after these operations (1) and (2), the clock display state will be maintained at all times. ing.

By the way, users of radio receivers have various requirements regarding the use of their radio receivers, and among these users, there are users who do not always need a clock display and place importance on a frequency display for channel selection. However, for users who do not need such a clock display all the time and want to make the frequency display for tuning as visible as possible, the conventional type described above is inconvenient because it does not satisfy the user's needs. There is a problem.

SUMMARY OF THE INVENTION In view of the above-mentioned problems with the conventional type, an object of the present invention is to enable display selection according to the user's preference regarding frequency/time display switching of a radio receiver, and to provide operability regarding frequency/time display switching. The aim is to improve

[Means for solving problems]

In the present invention, in a radio receiver having a clock and a frequency display function, a time switch for adjusting the time, a radio switch for operating the radio, and a radio receiver that normally displays the time and displays the radio for a predetermined period of time after the radio switch is operated. Display control means having a first mode for displaying the frequency of the receiving section, and a second mode for normally displaying the frequency and displaying the time for a predetermined time after operation of the time switch; and the display control means. a mode changeover switch for switching between a first mode and a second mode in the means, and the display control means causes the time to be displayed regardless of the first and second modes when the radio power is cut off; A clock and a radio receiver having a frequency display function, characterized in that the frequency display is performed for a predetermined period of time when the switch is turned on, and then the mode is shifted to a first or second mode depending on the mode changeover switch. machine is provided.

〔Example〕

A display control device as an embodiment of the present invention is applied. A basic circuit diagram of a radio receiver is shown in FIG. The display device 9 in the circuit of FIG. 1 is, for example, a seven-element display figure 91 as shown in FIG.
The frequency f display shows, for example, 76.0MHz, and the clock c display shows, for example, 76.0MHz.
The display device 9 is shared to display 12:30 AM (or PM).

The radio receiving circuit 1 includes a receiving input circuit 11, an integrated circuit phase lock loop unit 12, and a low-pass filter 1.
3, a radio output circuit 14 and a speaker 15. The tuning circuit 2 that supplies output to the phase lock loop section includes a manual and search operation holding circuit 41, an operation holding circuit 42, and an operation holding circuit 4 operated by switch sections 31, 32, 33, 34, and 35.
3, and receives the output signal of the band selection circuit 44. One of the outputs of the tuning circuit 2 is the frequency calculation circuit 6.
supplied to The output of the frequency calculation circuit 6 and the output of the clock counting circuit 7 based on the crystal oscillation XTL signal are supplied to the display selection circuit 8. Upon receiving the output signals of the operation holding circuit 41, operation holding circuit 42, operation holding circuit 43, and band selection circuit 44, the recall switch 341 and normally the time are displayed, and the radio receiving section is activated for a predetermined period of time after the radio switch is operated. A mode for switching between a radio priority mode, which is a first mode that displays the frequency of A clock that is a switch
The display selection circuit 8 is activated by the output signal of the display control circuit 5 operated by the frequency priority changeover switch 343.
is controlled. (The recall switch 341 is a switch for responding to a request to display something opposite to what is currently being displayed.) The display device 9 is driven by the output signal of the display selection circuit 8.

A specific circuit diagram of the circuit in FIG. 1 is shown in FIG.
A detailed circuit diagram of the display control circuit 5 in the circuit of FIG. 2 is shown in FIG. The circuit elements shown in FIGS. 3 and 4 will be explained as follows.

A. Phase-locked loop synthesizer type tuning circuit 12: Receives the received signal from the receiving input circuit 11, is controlled by the tuning circuit, and supplies an output to the low-pass filter.

B Data selector 22: Generates output in synchronization with the 4-digit signal from the signal generator 21, and transfers the frequency division ratio N, which is composed of BCD and 4 bits, to the phase lock loop tuning circuit 12 in parallel. .

BCD programmable up/down counters 241, 242, 243: Performs up/down counting based on the signal from the decoder circuit 23. Random access memory 2
The preset data is taken in by the signal from 5. Change the upper and lower limits of the band.

D. 4-bit programmable up/down
Counter 244: Outputs the highest digit of the frequency division ratio N value and a reference switching signal.

16-bit digital comparator 28: Determines whether the division ratio N value has reached the upper or lower limit of the band.

Calculation circuit 6: A circuit that calculates the reception frequency _s from the frequency division ratio N value.
When _r is the reference frequency, _s is the receiving frequency, _p is the local oscillation frequency, and _i is the intermediate frequency, the following relationship holds. _p = N・_r・_s = _p ± _i Display device 9: A device that displays either the receiving frequency or clock time.

4-bit or 16-bit random access memory 25: Random access memory (RAM) that can be read and written freely, and has an upper or lower bandwidth limit of N
It stores the value and outputs when the band limit value is reached during sweep or manual operation. It also outputs the contents of the preset. Also, when switching bands, the previous state of that band is output.

(f) Read or write control circuit 26: When the write switch is closed and the preset contents are rewritten, and when the upper and lower limits of the band are reached, the N value of the next limit to be received is stored in the random access memory. Write to 25. Thereby, the random access memory 25 is controlled.

Long/medium wave selector 29: Automatically switches between long wave and medium wave bands.

Operation holding circuit 41: Holds up or down manual operation, up or down search operation, and determines priority.

Operation holding circuit 42: Holds the write state and is released by the preset key.

Operation holding circuit 43: Holds the preset states set by the preset switches 331 to 33n.

C Band selection circuit 44: Logicizes key input band information.

E. Long/medium wave power selection circuit 291: Switches the power of the long wave tuner section and the medium wave tuner section according to the logic of the long/medium wave selector 29.

Sweep control decoder 23: Uses the sweep clock to switch up and down the BCD and 4-bit programmable up-down counter by the number of pulses. When searching, the clock from the signal generator 21 is output to automatically vary the N value, and when searching is manual, the N value is varied by outputting as many times as the manual key switch is turned on and off.

H. Display control circuit 5: When the operation switch is pressed, it selects the appropriate clock or frequency to display, and outputs the result to the display signal selection circuit 8 as a clock/frequency display instruction signal.

Clock counting circuit 7: Sequentially divides and counts the clock reference signal based on the reference pulse.

Display signal selection circuit 8: Selects the output of either the frequency calculation circuit 6 or the clock counting circuit 7 according to the clock/frequency display instruction signal sent from the display control circuit 5, and outputs the result to the display device 9.

A specific circuit configuration example of the display control circuit 5 in the circuit of FIG. 3 is shown in FIG.

C. Timer counter 501: Counts time T seconds. During counting, the output is "0",
After the counting is completed, the output becomes "1".

High flip-flop circuit 502: Usually operates through operation (input and output are equal), but when there is a “display priority switching” signal, it performs inversion operation (outputs with inverted input) and then latches, and the timer counter 501 finishes counting. At the same time, the latch is released and the through operation is resumed.

Flip-flop circuit 503: Normally operates through operation (input and output are equal), but when the timer counter 501 is counting, recall and
When a trigger signal is generated by closing the switch, the circuit performs an inversion operation and then latches, and when the timer counter 501 finishes counting, it is unlatched and returns to the through operation.

F. Display priority switching detection circuit 526: Generates a pulse regardless of whether the display priority switch 343 is switched to clock or frequency.

E Search and scan state holding circuit 505: Consists of a flip-flop array. Outputs a "low" level signal when in the on state. Search up・
It is reset when a receive (iF) signal is input in the down state. When the search up/down switch is in the starting state, any operation of switches 331 to 33n, switches 311, 312, and switch 351 will reset the search. The scan state is set or reset by a toggle operation. Search up/down switches 313, 314, manual switches 311, 312, band change switch 351
It will be reset if any of these operations are performed. When reset, it outputs a "high" level signal.

Instruction signal output circuit 509: Consists of a D-type flip-flop circuit with preset PSET and clear CLR inputs. Clear input has priority over preset input. During a clock adjustment operation and when the radio power is cut off, the preset input is at a "high" level, and the output signal is at a "high" level regardless of the input signal from circuit 503. On the other hand, when a series of tuning operations are performed, such as search up/down, scanning, tuning, manual up/down, band switching, or powering on the radio receiver, the clear input becomes "high" level. circuit 50
The output signal is "low" regardless of the input signal from 3.
level.

Time limit circuit 510: Gives priority to frequency display for a certain period of time after band switching or radio receiver power is turned on, and is then opened.

Gate circuit 511: The output is enabled when the power to the radio receiver is turned on, and the output is at the "high" level or open when the power to the radio receiver is turned off.

Gate circuits 512 to 522: Gate circuits 512 to 514 are 3-state buffer circuits, gate circuit 515 is a 3-state AND gate circuit, gate circuit 516 is a 3-state inverter circuit, gate circuits 517 to 519 are inverter circuits, gates Circuit 520 is a NAND gate circuit, and circuit 521 is a clock adjustment circuit.

By using the circuits of FIGS. 1, 3, and 4, the operations described below are performed.

1 [When a tuning operation is performed with priority given to the clock display, the frequency is displayed during tuning and for a certain period of time (T seconds) after the operation is released, and then the clock is displayed.] For example, while the tuning switch 331 is closed. , the operation holding circuit 43 holds that state, and the output of the gate circuit 511 becomes "0" and the gate circuit 5
14, the timer counter 501 is reset, and the clear input signal of the instruction signal output circuit 509 becomes "1" through the gate circuit 516.
The instruction signal output circuit 509 is cleared and the output signal of the instruction signal output circuit 509 becomes "0" to instruct frequency display.

When the channel selection switch 331 is opened, the output of the operation holding circuit 43 becomes "1" and the timer counter 50
1 output signal “0” is the flip-flop circuit 50
2 is input to the instruction signal output circuit 509 via the gate circuit 513 and flip-flop circuit 503, and the output of the instruction signal output circuit 509 is "0".
will appear, indicating the frequency display. timer counter 5
This state continues until the timer counter 501 finishes counting (T seconds), and the output signal "1" of the timer counter 501 is output from the flip-flop circuit 502 and the gate circuit 51.
3. Input to the instruction signal output circuit 509 via the flip-flop circuit 503, and input to the instruction signal output circuit 5
The output of 09 becomes "1" and instructs clock display.

2 [The clock is always displayed even if the clock adjustment operation is performed with priority to the clock display] When the clock adjustment switch in the clock adjustment circuit 521 is closed, the output of the clock adjustment circuit 521 becomes "0" and passes through the gate circuit 515. The timer counter 501 is reset and the preset input signal of the instruction signal output circuit 509 becomes "1" through the gate circuit 517 and the gate circuit 522, and the instruction signal output circuit 509 is preset and the output signal becomes "1" and the clock starts. Instruct display. However, since the gate circuit 515 is in a prohibited state, the timer counter 501 is not reset. When the clock adjustment switch is opened, the timer counter 501
The output signal “1” of the flip-flop circuit 502
The output is inputted to the instruction signal output circuit 509 via the gate circuit 513 and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes "1", instructing clock display.

3 [When the recall switch is closed with priority given to the clock display, the frequency is displayed for a certain period of time (T seconds) while the recall switch is closed and after the recall switch is opened, and then the clock is displayed.] When the recall switch 341 is closed, the gate circuit 519 is The timer counter 501 is reset. Output signal of timer counter 501 “0”
is inputted to the instruction signal output circuit 509 via the output of the flip-flop circuit 502, the gate circuit 513, and the flip-flop circuit 503, and the output of the instruction signal output circuit becomes "0" to instruct frequency display. This state continues while the recall switch is closed and the timer counter 501 is counting (for T seconds).
When the timer counter 501 finishes counting and the output of the timer counter 501 becomes "1", the output is inputted to the instruction signal output circuit 509 via the output of the flip-flop circuit 502, the gate circuit 513, and the flip-flop circuit 503, and outputs the instruction signal. The output of circuit 509 becomes "1" and instructs clock display.

4 [If the recall switch is closed again during the period in which a low-priority display is being performed for a predetermined period of time, a high-priority display will be performed from the moment the recall switch is closed] When the circuit is closed, the timer counter 50
1 is reset, and the output "0" of the timer counter 501 is output from the gate circuit 512 or 51 because the signals "0" and "1" are latched at the Q output and output of the flip-flop circuit 502, respectively.
A signal "0" or "1" is input to the flip-flop circuit 503 through either signal "0" or "1" depending on the state of the display priority switch 343. The flip-flop 503 inverts and latches the input for the trigger signal that is being counted by the timer counter 501, and the signal "1" or "0" is input to the instruction signal output circuit 509 to display the display corresponding to the display priority switch 343. Instruct. In the flip-flop circuit 502 and the flip-flop circuit 503, the timer counter 501 latches during the counting operation and releases the latch when the counting is completed.

In this way, by operating the recall switch again while a low-priority display is being performed, the display is immediately switched to a high-priority display, so even before the low-priority display ends, Displays can be easily switched, further improving operability.

5 [If the clock adjustment operation is performed with frequency display priority, the clock is displayed for T seconds during the clock adjustment and after the clock adjustment is completed, and then the frequency is displayed] While the clock adjustment switch in the clock adjustment circuit 521 is closed, the clock is The output of the adjustment circuit 521 becomes "0", the timer counter 501 is reset through the gate circuit 515, and the preset input of the instruction signal output circuit 509 becomes "1" through the gate circuit 517 and gate circuit 522.
The instruction signal output circuit 509 is preset and the output signal becomes "1", instructing clock display. This state continues while the clock adjustment switch is closed, and when the clock adjustment switch is opened, the clock adjustment circuit 521
The output of the timer counter 501 becomes "1", and the output signal "0" of the timer counter 501 is transmitted to the gate circuit 518, the Q output of the flip-flop circuit 502, the gate circuit 512,
It is input to the instruction signal output circuit 509 via the flip-flop circuit 503, and the instruction signal output circuit 509
The output becomes "1" and instructs the clock display. This state continues until the timer counter 501 finishes counting (T seconds). When the timer counter 501 finishes counting, the output "1" of the timer counter 501 is output to the gate circuit 518 and the flip-flop circuit 502.
A signal "0" is inputted to the instruction signal output circuit 509 through the Q output of the Q output, the gate circuit 512, and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes "0" to instruct frequency display.

6 [The frequency is always displayed even if the channel selection operation is performed with frequency display priority] For example, while the channel selection switch 331 is closed, the instruction signal output circuit 509 is cleared, and the instruction signal output circuit 509 outputs "0". to instruct the frequency display. However, since the gate circuit 514 is in a prohibited state, the timer counter 501 is not reset. This state continues while the channel selection switch 331 is closed, and when the channel selection switch 331 is opened, the output signal "1" of the timer count 501 is output from the gate circuit 518, the Q output of the flip-flop circuit 502,
Gate circuit 512, flip-flop circuit 503
After that, "0" is input to the instruction signal output circuit 509, and the output of the instruction signal output circuit 509 becomes "0" to instruct frequency display.

7 [When the recall switch is closed with frequency display priority, a clock is displayed for T seconds while the recall switch is closed and after the recall switch is opened, and then the frequency is displayed.] When the recall switch 341 is closed, the timer counter 501 passes through the gate circuit 519. is reset. Output “0” of timer counter 501
are gate circuit 518 and flip-flop circuit 50
The Q output of 2 is input to the instruction signal output circuit 509 via the gate circuit 512 and flip-flop circuit 503, and the output of the instruction signal output circuit 509 is "1".
will appear to indicate the clock display. Recall switch 3
This state continues while the 41 circuit is closed and the timer counter 501 is counting, and when the timer counter 501 finishes counting (T seconds), the output "1" of the timer counter 501 is output to the gate circuit 518, the Q output of the flip-flop circuit 502, and the flip-flop of the gate circuit 512. Instruction signal output circuit 509 via circuit 503
The output becomes "0" and instructs frequency display.

8 [When switching from clock display priority to frequency display priority, frequency display is performed from the moment of switching] When switching is performed using the display priority changeover switch 343, a pulse is selected from the display priority changeover detection circuit 504 and the gate circuit 520 is activated. The timer counter 501 is reset. timer counter 50
The output signal "0" of 1 is input to the flip-flop circuit 502 through the gate circuit 518, and in the flip-flop circuit 502, the output signal "1" of the gate circuit 518 is inverted to "0" by a trigger pulse, and then latched. The latched result is output from the Q output to the gate circuit 512. This output signal "0" is input to the instruction signal output circuit 509 via the gate circuit 512 and the flip-flop circuit 503, and the output of the instruction signal output circuit 509 becomes "0" to instruct frequency display. Note that the flip-flop circuit 1 releases the latch when the timer count 501 ends, and the output of the gate circuit 518 becomes the gate circuit 5.
equals 12 inputs.

9 [When switching from frequency display priority to clock display priority, the clock display is performed from the moment of switching] When switching is performed by the display priority changeover switch 343, the pulse from the display priority changeover detection circuit 504 passes through the gate circuit 520. timer counter 5
Reset 01. The output "0" of the timer counter 501 is input to the R input of the flip-flop circuit 502, which inverts it to "1" by the trigger pulse and latches it, and the latched signal is sent from the output to the gate circuit 513, The signal is inputted to an instruction signal output circuit 509 via a flip-flop circuit 503. The output of the instruction signal output circuit 509 becomes "1" and instructs clock display. Incidentally, the flip-flop circuit 502 releases the latch when the timer counter 501 count end signal is "1", and the output signal of the timer counter 501 and the input signal of the gate circuit 513 become equal.

10 [The clock is displayed when the radio receiver power is cut off] When the radio receiver power is cut off by the switch 342, the signal passes through the gate circuit 522 and sets the preset input of the signal output circuit 509 to "1". The signal output circuit 509 is preset and instructs clock display regardless of the operation of the channel selection switch.
At this time, the gate circuit 51 is
6 is in a prohibited state, so it has no effect.

11 [When switching the band and turning on the power to the radio receiver, the frequency is displayed for T seconds, and thereafter the display is displayed according to the display priority.] Band switching by the band change switch 351 or the radio receiver power switch 342 or the power supply to the radio receiver When the power is turned on, the pulse signal based thereon becomes a trigger to the timer circuit 510, which gives priority to the frequency display for T seconds, and at the same time resets the timer counter 501 via the gate circuit 515.

In addition to the above-mentioned matters, the first, third and fourth
In the circuit shown in the figure, when the operating switches on the tuning side and the watch side are pressed simultaneously, the tuning side operation can be performed with priority over the watch side operation.

[Effects of the Invention] According to the present invention, the first mode normally displays the time using the mode changeover switch, and also displays the frequency of the radio receiving section for a predetermined period of time after the radio switch is operated; In addition to displaying the frequency, it is also possible to switch between a second mode in which the time is displayed for a predetermined period of time after the time switch is operated, so the frequency and time display of the radio receiver can be changed according to the user's preference. In the first mode, the frequency is temporarily displayed in response to the operation switch of the radio receiver, and in the second mode, the frequency is temporarily displayed in response to the operation of the time switch. Since the time is displayed at the same time, the operability of frequency and time display switching can be improved.

Furthermore, when the radio power is turned off, that is, when there is no need to display the frequency, the time is displayed, and when the radio power is turned on, that is, when the frequency display is necessary for radio reception, the frequency is displayed for a predetermined period of time. let it be,
Since a display with a high priority is then performed, necessary displays are selectively performed, further improving operability.

[Brief explanation of drawings]

FIG. 1 is a basic circuit diagram of a radio receiver to which a display control device as an embodiment of the present invention is applied, FIG. 2 is a diagram showing a display device in the circuit of FIG. 1, and FIGS. 3A and B are FIG. 2 is a circuit diagram showing a specific configuration of the circuit, and FIG. 4 is a detailed circuit diagram of a display control circuit in the circuit of FIG. 1...Radio receiving circuit, 11...Receiving input circuit, 1
2... Phase locked loop synthesizer, 13... Low pass filter, 14... Radio output circuit, 15... Speaker, 2... Tuning circuit, 21... Signal generator, 22... Data selector, 23... Decoder circuit, 241-2
44...Counter, 25...Random access memory, 26...Read/write control circuit, 27...Read only memory, 28...Comparator, 29...
Long/medium wave selection circuit, 311, 312...Manual lowering/
Up switch, 313, 314... Search down/up switch, 32... Write (memory) switch, 33
1 to 33n...Channel selection switch, 341...Recall switch, 342...Receiver power switch,
343...Clock/frequency priority display switch, 3
51,352...Band selection switch, 41,42,
43...operation holding circuit, 44...band selection circuit, 5...
Display control circuit, 501... timer counter, 50
2,503...Flip-flop circuit, 509...Indication signal output circuit, 510...Flip-flop circuit, 511-520...Gate circuit, 521...Clock adjustment circuit, 524...Delay circuit, 522...Radio receiver power supply opening/closing detection circuit, 526...Display Priority switching detection circuit, 6... Frequency calculation circuit, 7... Clock counting circuit, 8... Display signal selection circuit, 9... Display device, 91
...Display figure.

Claims (1)

[Scope of Claims] 1. A radio receiver having a clock and a frequency display function, which includes: a time switch for adjusting the time; a radio switch for operating the radio; display control means having a first mode in which the frequency of the radio receiving section is displayed only when the radio receiver is operated; and a second mode in which the frequency is normally displayed and the time is displayed for a predetermined time after the time switch is operated; The first mode and the second mode in the display control means
a mode changeover switch for switching the mode, and the display control means causes the time to be displayed regardless of the first and second modes when the radio power is turned off, and displays the frequency for a predetermined time when the radio power is turned on. 1. A radio receiver having a clock and frequency display function, characterized in that the radio receiver is configured to shift to a first or second mode depending on the mode changeover switch after the timer is set.