JPH1041557A - Superconducting plane circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of heat and also, avoid the process deterioration of a superconductor wiring. SOLUTION: A dielectric layer with a specified thickness is interposed between the superconducting wirings 3-9 and metallic contacts 10 and 11 for supplying these superconductor wirings 3-9 with signals or taking out signals from these superconducting wirings 3-9. Since the dielectric layer with a specified thickness is interposed between the superconductive wirings 3-9 and the metallic wirings, both are coupled in capacity, and the effective power consumption becomes zero. Accordingly, the heat generation at the junction does not occur at all, and because the metallic contacts 10 and 11 and the superconducting wirings 3-9 are out of contact, it does not need heat-treatment at high temperature, and the process deterioration accompanying this does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting planar circuit having a thin-film wiring made of a high-temperature superconductor (hereinafter referred to as "superconductor wiring") and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a YBCO-based high temperature superconductor (HTS) has been used for wiring in a chip of a superconducting planar circuit such as a microwave integrated circuit.
Attempts have been made to use superconductor wiring consisting of H
This is because the electrical resistance of the TS is extremely small (however, in the superconducting state), so that excellent characteristics not found in metal wiring, such as a significant reduction in signal loss and an improvement in frequency response, can be obtained.

The use of superconductor wiring is limited, and other wirings are still normal conductors (ie, metal). Therefore, connection (contact) of both wirings is inevitably required. However, there is an inconvenience that the contact resistance is too high (Note 1), the connection is weak, and the connection is weak (Note 2). Note 1: The carrier concentration of the superconductor material is one order of magnitude lower than that of the metal material, and an electrical barrier occurs at the contact interface between the two. Note 2: Superconductor wiring and metal contacts are connected only by van der Waals force (intermolecular force acting between two neutral stable molecules).

[0004] As a prior art which has solved such inconvenience,
For example, Japanese Patent Application Laid-Open No. Hei 6-232462 discloses that an alloy of gold (Au) and germanium (Ge) is interposed between a superconductor wiring and a metal contact, and a heat treatment at 400 ° C. is performed for 5 minutes to superconduct Ge. By spreading to body wiring,
Improvement of bonding strength and reduction of contact resistance (according to the publication, 1 ×
It is described that 10 ⁻⁷ Ω · cm ² ) can be achieved.

[0005]

However, in the prior art, even if the contact resistance can be reduced,
The achieved value is still higher than the electrical resistance of the superconductor wiring (infinitely close to zero), and especially in applications where the signal current is large (for example, a frequency filter used in the transmission stage of communication equipment), the current value is 2%. Since heat is generated in proportion to the product (power) of the power and the contact resistance, there is a serious problem that a superconducting state (a state of zero electric resistance) cannot be maintained by the heat.

Further, in the prior art, since high-temperature heat treatment is required, there is a problem that the process deterioration of the superconductor wiring cannot be denied. Accordingly, an object of the present invention is to suppress the generation of heat and to avoid the process deterioration of the superconductor wiring.

[0007]

According to the present invention, there is provided a superconducting planar circuit comprising: a superconductor wiring; and a metal contact for supplying a signal to the superconductor wiring or extracting a signal from the superconductor wiring. And a dielectric layer having a predetermined thickness is interposed between them. 3. The method for manufacturing a superconducting planar circuit according to claim 2, wherein a superconductor layer and a dielectric layer having a predetermined thickness are laminated on a substrate, and the dielectric layer and the superconductor layer are patterned through a mask. Forming a metal contact at a required position on the dielectric layer.

According to a third aspect of the present invention, there is provided a method for manufacturing a superconducting planar circuit, comprising: laminating a superconductor layer and a dielectric layer having a predetermined thickness on a substrate; and forming a metal contact at a required position on the dielectric layer. Patterning the dielectric layer and the superconductor layer via a mask. A method for manufacturing a superconducting planar circuit according to claim 4 is the method for manufacturing a superconducting planar circuit according to claim 3, wherein the dielectric layer and the superconductor layer are covered with a protective film after the patterning. A contact hole is formed in the film to expose a metal contact.

In the first, second or third aspect of the present invention, since a dielectric layer having a predetermined thickness is interposed between the superconductor wiring and the metal wiring, the two layers are capacitively coupled to each other, and the effective power consumption is increased. Is zero, so no heat is generated at the joint. In addition, since the metal contact and the superconductor wiring are not in contact with each other, a high-temperature heat treatment for increasing the affinity of the contact surface is not required, and the accompanying process deterioration does not occur.

According to the present invention, the exposed cross-section of the superconductor layer is covered with the protective film during the period from the patterning of the superconductor layer to the formation of the contact hole. (Air and chemicals) are reliably eliminated. Therefore, a change in the composition of the superconductor layer is avoided, and good superconductivity is maintained.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 5 are views showing a first embodiment of a superconducting planar circuit and a method of manufacturing the same according to the present invention, and are not particularly limited, but are examples of application to a superconductor filter.
FIG. 1 is a chip layout diagram of the superconductor filter 1. 2 is a dielectric substrate, 3 is a superconductor wiring on the signal input side,
Reference numeral 4 denotes a superconductor wiring on the signal extraction side, and reference numerals 5 to 9 denote resonance superconductor wirings whose sizes, shapes, intervals, and the like are adjusted according to appropriate frequencies. As will be described later, a dielectric layer having a predetermined thickness is stacked on the surface of each of the superconductor wirings 3 to 9, and when viewed from above as shown in the drawing, each of the superconductor wirings 3 to 9 has a dielectric layer. Hidden beneath the body layer and invisible.

Reference numeral 10 denotes a metal contact for supplying a signal from outside the chip to the superconductor wiring 3 on the signal input side, and reference numeral 11 denotes a signal for extracting a signal from the superconductor wiring 4 on the signal extraction side to the outside of the chip. The metal contacts 10 and 11 are stacked on the superconductor wirings 3 and 4 via a dielectric layer having a predetermined thickness.

The superconductor filter having such a configuration is manufactured through the following steps. First, a superconductor layer 20 is formed on the dielectric substrate 2 (FIG. 2A). Next, a dielectric layer 21 having a predetermined thickness is formed on the superconductor layer 20 (FIG. 2).
(B)) Then, a superconductor layer 22 and a metal layer 23 (which becomes a ground electrode of a strip line) are sequentially formed on the lower surface of the dielectric substrate 2 (FIGS. 2C and 2D). However, since the ground electrode is unique to the stripline structure, the steps shown in FIGS. 2C and 2D are not required unless this structure is adopted.

Next, each layer (the superconductor layer 20 and the dielectric layer 21) on the surface of the dielectric substrate 2 is patterned through a mask having a required pattern. Resist 2 patterned on
4 (FIG. 3E), and the dielectric layer 21 and the superconductor layer 20 are etched through the resist 24 (FIG. 3E).
After (f)), the flow is such that unnecessary resist 24 is removed (cleaned). FIG. 3G shows the resist 24.
When the mask pattern is the layout pattern of FIG. 1, the superconductor wiring 3 on the signal input side and the superconductor wiring 4 on the signal extraction side of FIG.
And, superconductor wirings 5 to 9 for resonance (represented by reference numerals 5 and 9 in the figure), that is, wirings except the metal contacts 10 and 11 are formed (see FIG. 5).

Finally, metal contacts 10 and 11 are formed. The metal contacts 10 and 11 are formed on the surface of the patterned dielectric layer 21, more specifically, on one metal contact 10, on the signal input side. Superconductor wiring 3
Is formed on the surface (referred to as A-plane for convenience) of the dielectric layer 21 located immediately above the other metal contact 11.
In this case, the dielectric layer 21 is formed on the surface of the dielectric layer 21 located immediately above the superconductor wiring 4 on the signal extraction side (referred to as the surface B for convenience). In this step, first, a resist 25 patterned so as to expose only the A and B surfaces is placed (FIG. 4 (h)).
After the metal layer 26 is formed on the surface of the substrate (FIG. 4 (i)), the unnecessary metal film 26 and the resist 25 are removed (cleaned) (FIG. 4).
(J)). Here, the metal film 26 corresponds to FIG.
In (i), the film is formed with steps indicated by reference numerals 26a and 26b. In general, the step portion of the metal film formed on the element surface by the sputter deposition method or the like does not have a uniform thickness due to the shadowing effect, and tends to produce a gap called so-called step coverage. When immersed in the cleaning liquid, the resist 26 is removed through gaps (not shown) between the steps 26a and 26b, and at the same time, the unnecessary metal film 26 on the resist 26 is removed. This is a technique called a lift-off method. It is preferable that an adhesion layer such as titanium-nickel is interposed between the metal contacts 10 and 11 and the dielectric layer 21 because the adhesion strength of the metal contacts 10 and 11 can be improved and the metal contacts 10 and 11 can be hardly peeled off.

In such a structure, the metal contact 10 (11) faces the superconductor wiring 3 (4) via the dielectric layer 21 having a predetermined thickness, and the metal contact 10 (11)
And a superconducting wire 3 (4), a capacitance is determined by the facing area, the thickness of the dielectric layer 21, and the dielectric constant of the dielectric layer 21. Therefore, since the capacitance between the metal contact 10 (11) and the superconductor wiring 3 (4) is capacitively coupled and the effective power consumption is zero, no heat is generated at the coupling portion.
For this reason, the superconducting state of the superconductor wirings 3 to 9 can be stably maintained, and particularly, a technique suitable for a large current application can be provided.

The entire surface of the superconductor layer 20 on the substrate 2 is covered with a dielectric layer 21.
Is protected from damage in the middle of the process, and is patterned together with the dielectric layer 21, so that damage in the patterning process can be minimized and the metal contacts 10, 1
1 and the superconductor wirings 3 and 4 are not in contact with each other, so that a high-temperature heat treatment for increasing the affinity of the contact surface is not required, and the process deterioration accompanying this is not caused.

In the steps of the first embodiment (FIGS. 2 to 4), the metal contacts 10 and 11 are formed after the superconductor layer 20 and the dielectric layer 21 are patterned. Not exclusively. After the metal patterns 10 and 11 are formed at required positions on the dielectric layer 21, the superconductor layer 20 and the dielectric layer 21 may be patterned. This way,
At the time of forming the metal contacts 10 and 11, the superconductor layer 20 is covered with the dielectric layer 21, which is preferable because the effect of avoiding damage can be further enhanced.

Next, a second embodiment of the present invention will be described. This second embodiment is an improvement of the first embodiment. As described above, the first embodiment does not generate heat at the joint.
Does not require high-temperature heat treatment and does not cause process deterioration.
Since the surface of the superconductor layer 20 is covered with the dielectric layer 21, it is excellent in that damage to the surface can be suppressed, but the side wall of the superconductor layer 20 after patterning is exposed unprotected (FIG. 3).
(F)), and this side wall has three steps (FIG. 3 (g)).
Since (h) and (j)) are exposed to the atmosphere or a chemical solution, the method is not sufficient in terms of suppressing the damage to the superconductor layer 20 (). FIG. 6 is a process flow chart of the first embodiment, in which the entire process is divided into "film formation", "photolithography", and "etching". Although film formation and etching are performed in a vacuum, only photolithography is performed in the air (in the case of removing a resist, in a chemical solution). The lowercase letters in parentheses in the figures correspond to the process numbers in FIGS. 2 to 4, and the white arrows indicate the process movement in a state where the entire superconductor layer 20 is completely covered, and Black arrows indicate the process movement in a state where the side walls of the superconductor layer 20 (specifically, the side walls of the superconductor wirings 3 to 9) are exposed.
As can be understood from this figure, in the first embodiment, (f)
From (j) to (j), the side wall of the superconductor layer 20 is exposed, and the three steps (g), (h), and (j) are performed in the atmosphere (or in a chemical solution). ing. Therefore, the superconductor layer 2 is affected by the influence of the air and moisture in the chemical solution.
However, there is a drawback that the composition of 0 tends to change, and in some cases, the required superconductivity may not be obtained.

FIGS. 7 to 10 are process diagrams of the second embodiment. In these figures, components common to the first embodiment are denoted by the same reference numerals. In the second embodiment,
After performing the same steps (a) to (d) as in the first embodiment (see FIG. 2), first, a patterned resist 30 is placed on the surface of the dielectric layer 21 (FIG. 7 (e)), and then ,
A metal layer 31 is formed on the entire surface (FIG. 7F), and then the resist 3 is formed by the lift-off method used in the first embodiment.
Unnecessary metal film 31 is removed along with metal contact 1
0 and 11 are formed (FIG. 7G).

Next, a predetermined material (preferably metal) is coated on the entire surface.
The first protective film 32 (the reason will be described later) is formed (FIG. 7).
(H)) A patterned resist 33 is placed thereon (FIG. 8 (i)), the first protective film 32 is etched through the resist 33 (FIG. 8 (j)), and then the resist 33 is removed. (FIG. 8 (k)), and the patterned first
Using the protective film 32 as a mask, the dielectric layer 21 and the superconductor layer 20 are etched (FIG. 9 (l)), and the superconductor wiring 3 on the signal input side, the superconductor wiring 4 on the signal extraction side, and resonance Superconductor wirings 5 to 9 (represented by reference numerals 5 and 9 in the figure) are formed (FIG. 9 (m)).

Here, when the first protective film 32 is made of metal (for example, niobium or tungsten in terms of ease of etching),
Since the first protective film 32 is simultaneously etched in the step (l), the film thickness of the first protective film 32 is optimally set in consideration of the etching rates of the dielectric layer 21 and the superconductor layer 20. At this stage, the first protective film 32 can be completely removed, and the surfaces of the metal contacts 10 and 11 can be exposed. However, even if the first protective film 32 slightly remains (in FIG. (The remaining amount is shown as over). The metal can be easily oxidized into an insulator, and the insulator can be partially removed in a contact hole forming step described later to connect the metal contacts 10 and 11 to other wirings. is there. A dash (') on the first protective film 32 in FIG. 9 (m) indicates oxidation.

Finally, a new second protective film 33 (having chemical resistance; for example, typically a silicon oxide film) is formed on the entire surface.
(FIG. 9 (n)), and a patterned resist 34 is placed on the surface of the second protective film 33 (FIG. 10 (n)).
(O)) Using the resist 34 as a mask, the second protective film 33 is exposed until the surfaces of the metal contacts 10 and 11 are exposed.
And the first protective film 32 'is removed, and the contact hole 3 is removed.
After forming 5 and 36 (FIG. 10 (p)), a resist 34 is formed.
Is completed (FIG. 10 (q)). Second protective film 33
Corresponds to the “protective film” according to the fourth aspect of the present invention.

FIG. 11 is a process flow chart of the second embodiment.
In this embodiment, the superconductor layer 20 is formed between steps (l) to (n).
(Specifically, the side walls of the superconductor wirings 3 to 9) are exposed. As can be understood from the flowchart, steps (l) to (l) are performed.
There is no "photolithography" between (n). Therefore, according to the present embodiment, since the side wall of the superconductor layer 20 is not exposed to the atmosphere or the chemical at all, the superconductor layer 20 is superior to the first embodiment in that damage to the superconductor layer 20 is suppressed. Thus, a particularly advantageous effect is obtained that the composition change of the superconductor layer 20 can be prevented and the required superconducting characteristics can be accurately maintained.

[0025]

According to the first, second or third aspect of the present invention, since a dielectric layer having a predetermined thickness is interposed between the superconductor wiring and the metal wiring, both are capacitively coupled. Since the effective power consumption becomes zero, no heat is generated at the junction and the superconducting state can be stably maintained. In addition, since the metal contact and the superconductor wiring are not in contact with each other, a high-temperature heat treatment for increasing the affinity of the contact surface is not required, and the accompanying process deterioration does not occur.

According to the fourth aspect of the present invention, during the period from the patterning of the superconductor layer to the formation of the contact hole,
Since the exposed cross section of the superconductor layer is covered with a protective film, the effect of the photolithography process performed during that time (atmosphere and chemicals)
Can be reliably eliminated to avoid a change in the composition of the superconductor layer,
Good superconductivity can be maintained.

[Brief description of the drawings]

FIG. 1 is a plan layout diagram of a first embodiment.

FIG. 2 is a process drawing (1/3) of the first embodiment.

FIG. 3 is a process drawing (2/3) of the first embodiment.

FIG. 4 is a process drawing (3/3) of the first embodiment.

FIG. 5 is a plan layout diagram after patterning of the first embodiment.

FIG. 6 is a process flow chart of the first embodiment.

FIG. 7 is a process drawing (1/4) of the second embodiment.

FIG. 8 is a process drawing (2/4) of the second embodiment.

FIG. 9 is a process drawing (3/4) of the second embodiment.

FIG. 10 is a process drawing (4/4) of the second embodiment.

FIG. 11 is a process flow chart of the second embodiment.

[Explanation of symbols]

 2: substrate 3 to 9: superconductor wiring 10, 11: metal contact 20: superconductor layer 21: dielectric layer 33: second protective film (protective film)

Claims (4)

[Claims] 1. A dielectric layer having a predetermined thickness is interposed between a superconductor wiring and a metal contact for supplying a signal to the superconductor wiring or extracting a signal from the superconductor wiring. A superconducting planar circuit, characterized in that: 2. A superconductor layer and a dielectric layer having a predetermined thickness are laminated on a substrate, and the dielectric layer and the superconductor layer are patterned through a mask. A method for manufacturing a superconducting planar circuit, comprising forming a metal contact. 3. A superconductor layer and a dielectric layer having a predetermined thickness are laminated on a substrate, a metal contact is formed at a required position of the dielectric layer, and the dielectric layer and the superconductor are superimposed via a mask. A method for manufacturing a superconducting planar circuit, comprising patterning a body layer. 4. The method according to claim 3, wherein the dielectric layer and the superconductor layer are covered with a protective film after the patterning, and thereafter, a contact hole is formed in the protective film to expose a metal contact. Manufacturing method of superconducting planar circuit.