JPH1041399A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to form a shallow junction. SOLUTION: When a first diffusion layer 18 and a second diffusion layer 16 are formed in the same substrate 11, impurities are so doped that the first diffusion layer 18 and the second diffusion layer 16 may be different in either the impurity density or the junction depth. The doping of impurities for forming the first diffusion layer 18 is conducted by vapor-phase doping.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device to which a bipolar transistor belongs.

[0002]

2. Description of the Related Art In order to improve the maximum cutoff frequency (fTmax) of a bipolar transistor, there has been proposed a silicon-based heterojunction bipolar transistor employing a silicon germanium (Si _1-x Ge _x ) layer as a base layer.
In such a bipolar transistor, fTmax ≧ 10
One at 0 GHz has been reported. Here, a method of manufacturing a bipolar transistor using a silicon germanium layer formed by an epitaxial method as a base layer will be briefly described below with reference to FIG.

An n-type silicon substrate 101 as shown in FIG. 8A is used. Then, as shown in FIG. 8B, the silicon substrate 1 is formed by an epitaxial technique.
A base layer 102 including a silicon-germanium heterojunction is formed on the substrate 01. When the silicon germanium base layer 102 is formed, the base layer 102 is formed while doping impurities (for example, a P-type impurity such as boron in an NPN transistor). Thereafter, as shown in FIG. 8C, an emitter layer 103 is formed on the base layer 102. As described above, a silicon germanium heterojunction bipolar transistor is formed. On the other hand, as a method of doping impurities into the base layer 102, an ion implantation technique is generally adopted in addition to the above-described method.

The above base profile will be described with reference to FIG. In FIG. 9, the vertical axis indicates the impurity concentration, and the horizontal axis indicates the depth. As shown in FIG. 9, the impurity (boron) profile of the base is distributed throughout the base layer including the silicon germanium heterojunction. The impurity (phosphorus) profile of the emitter is also distributed over the upper layer of the silicon germanium heterojunction. The distribution of germanium extends to the substrate near the interface of the base layer together with the base layer.

[0005]

However, with the epitaxial technique, it is not possible to form one type of base profile in a single base formation process. At present, it is necessary to sacrifice the withstand voltage, VA and the like of the element to some extent in order to improve fTmax.
Therefore, even if a single transistor is put into practical use, it is not always preferable in terms of circuit design when configuring an integrated circuit.

[0006] In short, a high withstand voltage is not required but a high f
A high fT transistor is used for the portion where T
Although it is not necessary to use a high-breakdown-voltage transistor in a portion where a withstand voltage is required, a degree of freedom and a margin in design can be secured. To do so, the concentration of the base layer and the junction depth of each transistor must be determined so as to be a high fT transistor and a high breakdown voltage transistor. In the ion implantation method, the implanted impurity causes channeling, so that there is a limit in forming a shallow junction. Therefore, regarding the improvement of fTmax,
The formation of the base layer by the epitaxial technique is considered to be an advantageous technique.

[0007]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems. That is, when the first diffusion layer and the second diffusion layer are formed in the same substrate, the impurities are introduced so that at least one of the impurity concentration and the junction depth of the first and second diffusion layers is different. Accordingly, in the method for manufacturing a semiconductor device in which the first and second diffusion layers are formed, the introduction of impurities for forming the first diffusion layer is performed by diffusion from a gas phase, thereby solving the problem.

In the above manufacturing method, since the impurity introduction for forming the first diffusion layer is performed by diffusion from the gas phase, a shallower junction is formed as compared with the conventional ion implantation method. It becomes possible.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the first embodiment of the present invention will be described below.
This will be described with reference to the manufacturing process diagram of FIG. In FIG. 1, (a) on the left side of the drawing shows a high f for signal processing or logic formation.
A first diffusion layer serving as a base layer of a transistor requiring T is formed, and a second diffusion layer serving as a base layer of a transistor requiring a high withstand voltage for power supply is formed in (b) on the right side of the drawing.
A diffusion layer is to be formed.

As shown in FIG. 1A, the surface of a substrate (eg, a silicon substrate) 11 is sufficiently cleaned. afterwards,
As shown in FIG. 1 (2), molecular beam epitaxy (hereinafter, referred to as MBE), gas source MBE, ultra-high vacuum chemical vapor deposition (hereinafter, UHV-CVD) method, reduced pressure chemical vapor deposition (hereinafter, LP) A silicon germanium / silicon hetero layer is formed as the silicon semiconductor layer 12 containing germanium on the substrate 11 by a film forming technique such as a method such as CVD. The concentration of germanium in the silicon germanium layer was 3% to 30%, and the thickness of the silicon germanium layer was in the range of 10 nm to 500 nm. The thickness of the silicon layer is 0.1 nm to 200 nm.
Range.

Subsequently, as shown in FIG. 1C, a first mask layer 15 is formed which covers the region 13 where the first diffusion layer is to be formed and has an opening on the region 14 where the second diffusion layer is to be formed.
The first mask layer 15 is formed of a resist by, for example, a lithography technique. And the first mask layer 1
The silicon semiconductor layer 12 containing germanium in the region 14 where the second diffusion layer is to be formed is doped with an impurity by an ion implantation method using 5 as an ion implantation mask. On the other hand, the region 13 where the first diffusion layer is to be formed and which is covered with the first mask layer 15 is not doped with an impurity.

As for the ion implantation conditions, when boron ions (B ⁺ ) are used as impurities, the acceleration energy is 10 keV to 200 keV, and the dose is 5.0 × 10 5
It was set to ¹¹ pieces / cm ² ~2.0 × 10 about ¹⁴ / cm ^2. When boron difluoride ion (BF ₂ ⁺ ) is used as the impurity, the acceleration energy is 5 keV to 200 kV.
eV, dose amount: 5.0 × 10 ¹¹ / cm ^{2 to} 2.0 ×
It was set to about 10 ¹⁴ / cm ² . As a result, the substrate 11
-Containing silicon semiconductor layer 1 near the interface with silicon
2, a second diffusion layer 16 is formed. Here, the first
Although the mask layer 15 is formed of a resist, it may be formed of, for example, an insulating film such as a silicon oxide film or a silicon nitride film.

Next, the first mask layer 15 is removed. Thereafter, as shown in FIG. 1D, a second mask layer 17 is formed which covers the region 14 where the second diffusion layer is to be formed and has an opening on the region 13 where the first diffusion layer is to be formed. The second mask layer 17 is formed of, for example, silicon oxide. Then, gas phase doping (Rapid Vapor) using the second mask layer 15 is performed.
The silicon semiconductor layer 12 containing germanium in the region 13 where the first diffusion layer is to be formed is doped with impurities by por-Phase Direct Doping). On the other hand, the region 14 where the second diffusion layer is to be formed, which is covered with the second mask layer 17, is not doped with impurities.

The conditions of the above-mentioned vapor-phase doping include, for example, an atmosphere at a temperature of 750 ° C. to 1200 ° C., and hydrogen (H
50 cm ³ / min flow rate of _2), set the flow rate of diborane (B ₂ H ₆₎ in 5 cm ³ / min ~200cm ³ / min extent,
The doping time was set between 0.5 minutes and 60 minutes. As a result, the first diffusion layer 18 is formed on the silicon semiconductor layer 12 containing germanium. Here, the second mask layer 17 is formed of silicon oxide, but may be formed of an insulating film such as a silicon nitride film.

Then, the mask layer 17 is removed. Thereafter, as shown in FIG. 1 (5), a semiconductor layer 19 is formed on the silicon semiconductor layer 12 containing germanium.

In the above manufacturing method, the first diffusion layer 18 is formed by gas-phase doping, and the second diffusion layer 16 is formed by ion implantation.
The diffusion layer 16 is formed at a concentration and depth different from those of the diffusion layer 16. In addition, since gas-phase doping does not cause channeling, it is advantageous for forming a shallow junction. Therefore, the first diffusion layer 18 can be used as a base layer of a high fT transistor, and the second diffusion layer 16 can be used as a base layer of a high breakdown voltage transistor. Before forming each of the above base layers,
By forming a region serving as a collector on the substrate 11 and using the semiconductor layer 19 as each emitter layer, a heterojunction bipolar transistor based on the first diffusion layer 18 and requiring a high fT is formed. This makes it possible to form a heterojunction bipolar transistor based on the second diffusion layer 16 and requiring a high breakdown voltage.

The impurity profile of the first embodiment will be described with reference to FIG. 2A shows an impurity profile of the first diffusion layer 18 and FIG. 2B shows an impurity profile of the second diffusion layer 16. Each vertical axis indicates an impurity concentration, and each horizontal axis indicates a depth.

As shown in FIG. 2, the first diffusion layer 1 shown in FIG.
In the impurity profile of No. 8, the profile of boron (B) is formed in a shallow junction. Therefore, a bipolar transistor using the first diffusion layer 18 as a base layer can operate at high speed. On the other hand, the second diffusion layer 16 shown in FIG.
In the impurity profile of (1), the profile of boron (B) is formed at a deep junction. Therefore, a high withstand voltage can be ensured in the bipolar transistor using the second diffusion layer 16 as the base layer. The impurity (phosphorus) profile of each semiconductor layer 19 is distributed from the semiconductor layer 19 to each surface layer of the first and second diffusion layers 18 and 16, and the profile of each germanium is distributed from the first and second diffusion layers 18 and 16. It is distributed over the surface layer of the silicon substrate 11.

Next, an example of the second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. 3 to 6, a high fT transistor for signal processing or logic formation is formed on the left side of the drawing, and a high withstand voltage transistor which is not a high fT for power supply but requires element withstand voltage is shown on the right side of the drawing. Is formed.

As shown in FIG. 3A, a silicon oxide film 32 having a thickness of, for example, 300 nm is formed on a P-type <100> silicon substrate (hereinafter referred to as a silicon substrate) 31 by a thermal oxidation method.
Formed to a thickness of And N by lithography technology
^After forming a resist mask (not shown) having an opening on a region where a ⁺ -type buried layer is to be formed, an opening is formed in the silicon oxide film 32 on the region where each transistor is formed by etching using the resist mask. I do. Thereafter, gas phase diffusion of antimony (Sb) using antimony oxide (Sb ₂ O ₃ ) as a solid diffusion source (diffusion temperature is 1200 ° C.)
Is performed), and an N ⁺ -type buried layer 34 is formed in the silicon substrate 31 in a region where each transistor is formed.
To form The N ⁺ type buried layer 34 is formed by setting the sheet resistance ρs to, for example, 10Ω / □ to 50Ω / □, and setting the diffusion depth xj to, for example, about 1 μm to 2 μm.

Thereafter, the silicon oxide film 12 is removed by etching. Then, as shown in FIG. 3B, an N-type epitaxial layer 35 is formed on the entire surface of the silicon substrate 31 by, for example, a resistivity of 0.3 Ωcm to 5.0 Ωcm and a thickness of 0.5 μm to
It is formed to about 2.5 μm.

Next, as shown in FIG. 3C, a local oxidation method [for example, LOCOS (Local Oxidation of Silico)
n) method, a silicon oxide film 36 to be a buffer layer is formed to a thickness of, for example, 20 nm to 50 nm. Further, by chemical vapor deposition (hereinafter referred to as CVD), LOCO
The silicon nitride film 37 serving as a mask for the S method is
It is formed to a thickness of m to 100 nm. The thickness of each of the silicon oxide film 36 and the silicon nitride film 37 is LOCOS
It is determined by the length of the bird's beak generated by oxidation, the stress associated with the LOCOS method, and the controllability of defect generation.

Subsequently, the LO
Window 3 in the area where the field oxide film is formed by the COS method
A resist mask (not shown) having openings 8 is formed.
Therefore, the resist mask is formed on the formation region of the high fT transistor and the formation region of the high breakdown voltage transistor. Using the resist mask, the silicon nitride film 37, the silicon oxide film 36 and the N-type epitaxial layer 35 are etched. The amount of etching of the N-type epitaxial layer 35 is preferably set to about 1/2 of the field oxide film thickness so that the surface becomes flat after forming the field oxide film by the LOCOS method.

Thereafter, the resist mask is removed.
Then, as shown in FIG.
A field oxide film 39 is formed on the N-type epitaxial layer 35 by oxidation at 00 ° C. to 1100 ° C. The thickness of the field oxide film 39 is, for example, 0.5 μm to 1.5 μm.
The thickness is set to be approximately twice as large as the etching depth of the N-type epitaxial layer 35 in the range of μm. Next, the silicon nitride film 38 (see FIG. 1C) is removed by wet etching using hot phosphoric acid.

Next, a resist mask 40 having an opening 41 is formed on a region for forming a collector extraction region of each transistor by a lithography technique. Using this resist mask 40, a collector extraction region (N ⁺⁾ connected to the N ⁺ -type buried layer 34 of each transistor.
In order to form the mold plug 43, phosphorus ions (P ⁺ ) are implanted. As the ion implantation conditions, for example, the acceleration energy is set to 40 keV to 100 keV, and the dose is set to 1 × 10 ¹⁵ / cm ² to 1 × 10 ¹⁶ / cm ² .

Thereafter, the resist mask 40 is removed. Subsequently, in order to flatten the bird's head generated by the LOCOS method, a silicon oxide film (not shown) is formed by a CVD method, and a resist is applied to form a resist film (not shown). Then, the surface composed of the N-type epitaxial layer 35 and the field oxide film 39 is planarized by etching back by general reactive ion etching (hereinafter referred to as RIE).

Thereafter, as shown in FIG. 4A, a resist mask 44 having an opening 45 is formed on a region for forming an element isolation region by lithography.
Using the resist mask 44, boron ions (B ⁺ ) are implanted to form a P ⁺ -type element isolation region 46 for isolating each transistor region. The ion implantation conditions include, for example, an acceleration energy of 200 keV
500 keV, dose amount is 1 × 10 ¹³ / cm ² to 1 ×
Set to 10 ¹⁴ pieces / cm ² . Usually, before the boron-based impurity is ion-implanted, the surface of the epitaxial layer 35 is oxidized at a temperature of about 900 ° C. by 10 nm.
It is preferable to form a silicon oxide film (not shown) having a thickness of about 30 nm.

After that, the resist mask 44 is removed. Next, as shown in FIG. 4B, an oxide film (not shown) formed on the surface of the N-type epitaxial layer 35
Then, the surface of the N-type epitaxial layer 35 is cleaned and cleaned. Next, MBE, gas source MB
E, silicon germanium (Si _1-x) is formed on the N-type epitaxial layer 35 on which the field oxide film 39 is formed by a film forming technique such as an EHV-CVD method or an LP-CVD method.
A Ge _x ) layer 47 or a silicon germanium / silicon layer is continuously formed. At this time, the crystal layer grows in the region where the single crystal silicon layer is exposed as the base, and the polycrystal grows in the region where the polycrystalline silicon layer is exposed as the base, and the oxide film is exposed as the base. An amorphous layer grows in the region.

Subsequently, as shown in FIG. 4C, the high fT
A first mask layer 49 is formed on the silicon germanium layer 47, covering the formation region of the transistor for use and opening a window 48 on the base formation region of the high breakdown voltage transistor.
The first mask layer 49 is formed of a resist by, for example, a lithography technique. And the first mask layer 4
The silicon germanium layer 47 in the base formation region of the high breakdown voltage transistor is doped with an impurity by an ion implantation method using 9 as an ion implantation mask. on the other hand,
The formation region of the high fT transistor covered with the first mask layer 49 is not doped with an impurity.

As for the ion implantation conditions, when boron difluoride ion (BF ₂ ⁺ ) is used as the impurity, the acceleration energy is 5 keV to 200 keV, and the dose is 5.0 × 10 ¹¹ / cm ² . 2.0 × 10 ¹⁴ pieces / cm ²
Set to about. When boron ions (B ⁺ ) are used as impurities, the acceleration energy is 10 keV to 200 keV.
KeV, dose amount of 5.0 × 10 ¹¹ / cm ^{2 to} 2.0
It was set to about × 10 ¹⁴ pieces / cm ² . As a result, a base layer 50 composed of a P-type impurity diffusion layer was formed near the interface between the N-type epitaxial layer 35 and the silicon germanium layer 47. This base layer 50 corresponds to the second diffusion layer described in the first embodiment. Here, the first mask layer 49 is formed of a resist, but may be formed of, for example, an insulating film such as a silicon oxide film or a silicon nitride film.

After that, the first mask layer 49 is removed. Next, as shown in FIG. 4D, a second mask layer 51 is formed on the entire surface of the silicon germanium layer 47 by a CVD method using a silicon oxide film having a thickness of, for example, 50 nm to 300 nm. Then, using lithography technology,
High fT covering the region where the high breakdown voltage transistor is to be formed
A resist mask (not shown) having an opening on a region where the base of the transistor for forming is to be formed is formed. A window 52 is opened in the second mask layer 51 by etching (for example, RIE) using this resist mask. And this second
Gas-phase doping using the mask layer 51 (Rapid Vapor-Ph
The silicon germanium layer 47 in the region where the base of the high fT transistor is to be formed is doped with impurities by ase direct doping. On the other hand, the region where the high breakdown voltage transistor is to be formed covered with the second mask layer 51 is not doped with impurities.

The conditions for the gas phase doping include, for example, an atmosphere at a temperature of 750 ° C. to 1200 ° C., and hydrogen (H
50 cm ³ / min flow rate of _2), set the flow rate of diborane (B ₂ H ₆₎ in 5 cm ³ / min ~200cm ³ / min extent,
The doping time was set between 0.5 minutes and 60 minutes. As a result, a base layer 53 composed of a P-type impurity diffusion layer serving as a base layer was formed above the silicon germanium 48.
This base layer 53 is formed of the first layer described in the first embodiment.
It corresponds to a diffusion layer. Also, by this gas phase doping,
The impurities of the base layer 50 formed by the ion implantation are activated. Here, the second mask layer 51 is formed of silicon oxide, but may be formed of an insulating film such as a silicon nitride film.

Then, the second mask layer 51 is removed.
Thereafter, as shown in FIG. 5A, an N ⁺ type semiconductor layer 54 containing an N type impurity such as phosphorus (P) is formed on the silicon germanium layer 47 by an epitaxial technique. The N ⁺ type semiconductor layer 54 may be formed by forming an amorphous (or polycrystalline) silicon layer doped with phosphorus (P) by a CVD method and then diffusing impurities by annealing. Alternatively, after a non-doped amorphous (or polycrystalline) silicon layer is formed, arsenic (As) or phosphorus (P) may be ion-implanted, and then impurities may be diffused by annealing.

Next, a silicon oxide film 55 is formed on the entire surface of the N ⁺ type semiconductor layer 54 by the CVD method. Subsequently, a resist mask 56 is formed on the region where the emitter of each transistor is to be formed (that is, on the base layers 50 and 53 of each transistor) by lithography.

By the RIE using the resist mask 56, the silicon oxide film 55 and the N ⁺ type semiconductor layer 54 are formed.
Is patterned. As a result, as shown in FIG. 5B, an emitter layer 57 on which the silicon oxide film 55 is mounted is formed on the base layer 53, and an emitter layer 58 on which the silicon oxide film 55 is mounted is formed on the base layer 50. Is done.

Thereafter, the resist mask 57 is removed. Further, the silicon oxide film 55 is formed by CVD.
A silicon oxide film (not shown) is formed to a thickness of, for example, 200 nm to 400 nm so as to cover the emitter layers 57 and 58 on which the substrate is mounted. Thereafter, the silicon oxide film is etched back, and the silicon oxide film 55 and the emitter layer 57 are etched.
Sidewall insulating films 59 and 60 are formed on each side wall of the silicon oxide film 55 and the emitter layer 58.

Next, a resist mask 62 having an opening 61 on a region necessary for forming a graft base is formed by lithography. The P ⁺ -type region 63 is formed by ion implantation using the resist mask 62.
To form As the ion implantation conditions, for example, when boron ions (B ⁺ ) are used as impurities, the acceleration energy is 5 keV to 50 keV, and the dose is 1.0 ×
It was set to about 10 ¹⁵ / cm ² to about 1.0 × 10 ¹⁶ / cm ² . After that, the resist mask 62 is removed.

Next, the respective emitter layers 5 are formed by RIE.
The silicon oxide film 55 on 7, 58 is removed. This RI
Due to E, the width of each of the sidewall insulating films 59 and 60 is also reduced as shown in FIG. Next, a resist mask 64 is formed on a region where a base region of each transistor is to be formed by a lithography technique. Next, the silicon germanium layer 47 is patterned by RIE using the resist mask 64, and FIG.
As shown in FIG. 5, an intrinsic base layer composed of a base layer 53 and a graft base layer 65 composed of a P ⁺ -type region 63 connected thereto are formed, and an intrinsic base layer composed of a base layer 50 and a P ⁺ -type region connected thereto are formed. A graft base layer 66 made of 63 is formed. After that, the resist mask 64 is removed.

Next, a metal film for forming silicide is formed on the entire surface of each of the emitter layers 57 and 58 by a film forming technique such as sputtering. This metal film is made of, for example, titanium (Ti), nickel (Ni), platinum, cobalt (C
o), palladium (Pd), and tungsten (W). Then, after annealing at a temperature of about 400 ° C. to 800 ° C., each of the emitter layers 57 and 58,
The respective interface portions where the graft base layers 65 and 66 and the respective collector extraction regions 43 are in contact with the metal film are silicided to form a silicide layer 67. afterwards,
The unreacted metal film is removed by etching. Here, when forming the silicide layer 67, each of the sidewall insulating films 59 and 60 has a function of separating an emitter and a base.

Next, as shown in FIG.
By a method, a silicon oxide film 68 is formed to a thickness of, for example, about 300 nm on the entire surface on the side of each of the emitter layers 57 and 58. Then, a resist mask 70 having a window 69 opened on a region where each electrode is to be formed is formed by lithography technology. Subsequently, RI using the resist mask 70 is performed.
The silicon oxide film 68 is etched by E to form contact holes 71 in the respective electrode forming regions of the emitter, base and collector. After that, the resist mask 7
Remove 0.

Subsequently, as shown in FIG. 6C, after a barrier metal and an aluminum-based metal are formed by a film forming technique such as sputtering, the barrier metal and the aluminum-based metal are formed by ordinary lithography and etching techniques. Pattern the aluminum-based metal. As a result, the graft base layer 65 is formed in each contact hole 71.
A base electrode 72 connected to the base layer 75, an emitter electrode 73 connected to the emitter layer 57, a collector electrode 74 connected to the collector extraction region 43 of the high fT transistor, and a base electrode 75 connected to the graft base layer 66. An emitter electrode 76 connected to the transistor 58 and a collector electrode 77 connected to the collector extraction region 43 for the high breakdown voltage transistor are formed. Then, after removing the resist mask formed by the lithography technique, a known multi-layer wiring process is performed, although not shown.

As described above, the high fT transistor 1 composed of a mesa heterojunction bipolar transistor
And the high voltage transistor 2 are formed. And high f
The transistor 1 for T and the transistor 2 for high breakdown voltage have different base profiles. In particular, since the base layer 54 of the high fT transistor 1 is formed by gas phase doping, channeling does not occur. Therefore, since it is formed in a shallow junction state, a high fTmax is obtained.

In the above-described manufacturing method, the base layer 54 of the high fT transistor 1 is formed with a shallow junction by vapor phase doping using the same silicon germanium layer 48, and the base layer 51 of the high breakdown voltage transistor 2 is formed. Is formed with a deep junction by ion implantation, the high fT transistor 1 has a high performance with excellent cut-off frequency characteristics, and the high withstand voltage transistor 2 has a high withstand voltage. Further, since the base layers 51 and 54 of each transistor are formed using the same silicon germanium layer 48, high density and high integration can be achieved. In other words, in one lithography step and etching step,
This is because the base layers 51 and 54 of transistors having different characteristics can be formed. By using the high fT transistor 1 and the high withstand voltage transistor 2 formed by the above-described manufacturing method, a highly reliable LSI device can be realized.

Next, an example of the third embodiment of the present invention will be described with reference to FIG.
It will be explained by. The manufacturing method described in the third embodiment is different from the second embodiment described above in that phosphorus (P) is selectively ion-implanted into the N-type epitaxial layer 35 (corresponding to the collector region) of the high fT transistor 1. However, by forming a so-called SIC structure, the Kirk effect is suppressed and fTmax is further improved. In addition,
The same processes as those described in the second embodiment will be omitted. Therefore, please refer to the description of the second embodiment for the process whose description is omitted.

A great effect can be obtained by performing the SIC forming step before or immediately after the step of epitaxially growing the silicon germanium layer 47. Although not shown,
For example, when the etching is performed before the silicon germanium layer 47 is formed, a resist mask having an opening is formed on the N-type epitaxial layer serving as a collector region of the high fT transistor by a lithography technique. N-type impurities are ion-implanted by an ion implantation method using the resist mask. The ion implantation conditions at that time were as follows:
Using phosphorus ions (P ⁺ ) as impurities, the acceleration energy is 50 keV to 500 keV, and the dose is 1.0 × 1.
It was set to about 0 ¹² / cm ^{2 to} 1.0 × 10 ¹³ / cm ² .

By adding the above ion implantation step, as shown in FIG. 7, the N-type epitaxial layer 35 serving as the collector region of the high fT transistor 1 can have the SIC structure. The components of the high fT transistor 1 and the high withstand voltage transistor 2 other than the SIC structure have the same configuration as that described in the second embodiment.

In the second and third embodiments, the mesa-type NPN transistor has been described as an example. However, any heterojunction bipolar transistor formed by the selective epitaxial growth technique may be used.
The method of the present invention can be applied.

[0048]

As described above, according to the present invention,
Since the impurity introduction for forming the first diffusion layer is performed by diffusion from the gas phase, it becomes possible to form a shallower junction as compared with the conventional impurity implantation method by ion implantation. Further, according to the present invention, the first diffusion layer and the second diffusion layer can be formed by the same layer. Therefore, by employing the first diffusion layer as the base layer of the high fT transistor and the second diffusion layer as the base layer of the high breakdown voltage transistor, each base layer can be formed of the same hetero layer, and different base layers can be formed. It becomes possible to obtain a profile. Therefore, by forming one transistor as a high fT transistor and forming the other transistor as a high breakdown voltage transistor, heterojunction bipolar transistors having different characteristics can be formed over the same substrate.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a first embodiment according to the present invention.

FIG. 2 is an explanatory diagram of an impurity profile according to the first embodiment.

FIG. 3 is a manufacturing process diagram of a second embodiment according to the present invention.

FIG. 4 is a manufacturing process diagram (continued) of the second embodiment.

FIG. 5 is a manufacturing process diagram (continued) of the second embodiment.

FIG. 6 is a manufacturing process diagram (continued) of the second embodiment.

FIG. 7 is an explanatory diagram of a third embodiment.

FIG. 8 is a manufacturing process diagram of a conventional bipolar transistor.

FIG. 9 is an explanatory view of a conventional impurity profile.

[Explanation of symbols]

 11 substrate 16 second diffusion layer 18 first diffusion layer

Claims (6)

[Claims] When forming a first diffusion layer and a second diffusion layer in the same substrate, at least one of an impurity concentration and a junction depth of the first diffusion layer and the second diffusion layer are different. In the method of manufacturing a semiconductor device in which the first diffusion layer and the second diffusion layer are formed by introducing an impurity into the semiconductor device, the impurity introduction for forming the first diffusion layer is performed by diffusion from a gas phase. A method of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity introduction for forming the second diffusion layer is performed by ion implantation. 3. The method according to claim 1, wherein the first diffusion layer is a base layer of a first bipolar transistor, and the second diffusion layer is a base layer of a second bipolar transistor. A method for manufacturing a semiconductor device. 4. The method according to claim 2, wherein the first diffusion layer is a base layer of a first bipolar transistor, and the second diffusion layer is a base layer of a second bipolar transistor. A method for manufacturing a semiconductor device. 5. The method according to claim 3, wherein the semiconductor layers forming the base layer of the first bipolar transistor and the base layer of the second bipolar transistor are silicon semiconductor layers containing germanium. A method for manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor layers forming the base layer of the first bipolar transistor and the base layer of the second bipolar transistor are silicon semiconductor layers containing germanium. A method for manufacturing a semiconductor device.